Markus Niebel [Thu, 23 Oct 2014 14:09:38 +0000 (16:09 +0200)]
SPI: mxc_spi: remove second reset from ECSPI config handler
the second reset prevents other registers to be written.
This will prevent to have the correct signal levels for
SCLK before writing to the config reg in spi_xchg_single.
Tested with GPIO based chipselect and SPI_MODE_3 on i.MX6S
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Wed, 22 Oct 2014 19:56:04 +0000 (21:56 +0200)]
spi: altera: Move the config options to the top
Just move the configuration options scattered all over the driver
to the top of the source file. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Wed, 22 Oct 2014 19:56:03 +0000 (21:56 +0200)]
spi: altera: Add short note about EPCS/EPCQx1
Add short documentation-alike note on how to use the Altera SPI
driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V
into doc/SPI/README.altera_spi
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Wed, 22 Oct 2014 19:56:02 +0000 (21:56 +0200)]
spi: altera: Clean up the use of variable d
The variable d is used in rather questionable way. Rework the code
a bit so it's clearer what it does. Also, rename the variable from
d to data to make it's name less mysterious. Finally, change it's
data type to uint32_t , since it's accessed as a 32bit number.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Wed, 22 Oct 2014 19:56:01 +0000 (21:56 +0200)]
spi: altera: Zap endless loop
The driver contained an endless loop when waiting for TX completion,
this is a bad idea since if the hardware fails, the loop might spin
forever. Add timeout and handle it.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Wed, 22 Oct 2014 19:56:00 +0000 (21:56 +0200)]
spi: altera: Clean up most checkpatch issues
This patch just zaps most of the checkpatch cries present in the
driver. There is one more left, which will be addressed separately.
There is no functional change.
This patch also adds a bunch of newlines all around the place, this
is to make the code much more readable.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Wed, 22 Oct 2014 19:55:59 +0000 (21:55 +0200)]
spi: altera: Clean up bit definitions
Clean up the definitions of bits in the Altera SPI driver, there
is no need to put braces around numbers afterall. No functional
change.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Marek Vasut [Wed, 22 Oct 2014 19:55:58 +0000 (21:55 +0200)]
spi: altera: Use struct-based register access
Zap the offset-based register access and use the struct-based one
as this is the preferred method.
No functional change, but there are some line-over-80 problems in
the driver, which will be addressed later.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Andreas Bießmann [Fri, 24 Oct 2014 21:39:10 +0000 (23:39 +0200)]
tools/socfpgaimage.c: fix build on darwin
socfpgaimage utilizes htole32 and friends, unfortunately these functions are
not available on darwin. Fix it by using the cpu_to_le32 and friends defined
in compiler.h as other parts in mkimage do.
This patch fixes the following error:
---8<---
HOSTCC tools/socfpgaimage.o
tools/socfpgaimage.c:77:22: warning: implicit declaration of function 'htole32' is invalid in C99 [-Wimplicit-function-declaration]
header.validation = htole32(VALIDATION_WORD);
^
tools/socfpgaimage.c:80:22: warning: implicit declaration of function 'htole16' is invalid in C99 [-Wimplicit-function-declaration]
header.length_u32 = htole16(length_bytes/4);
^
tools/socfpgaimage.c:95:6: warning: implicit declaration of function 'le32toh' is invalid in C99 [-Wimplicit-function-declaration]
if (le32toh(header.validation) != VALIDATION_WORD)
^
tools/socfpgaimage.c:97:6: warning: implicit declaration of function 'le16toh' is invalid in C99 [-Wimplicit-function-declaration]
if (le16toh(header.checksum) != hdr_checksum(&header))
^
4 warnings generated.
...
HOSTLD tools/dumpimage
Undefined symbols for architecture x86_64:
"_htole16", referenced from:
_socfpgaimage_set_header in socfpgaimage.o
"_htole32", referenced from:
_socfpgaimage_set_header in socfpgaimage.o
"_le16toh", referenced from:
_verify_buffer in socfpgaimage.o
"_le32toh", referenced from:
_verify_buffer in socfpgaimage.o
ld: symbol(s) not found for architecture x86_64
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Pavel Machek <pavel@denx.de>
Marek Vasut [Thu, 16 Oct 2014 10:25:40 +0000 (12:25 +0200)]
arm: socfpga: Zap spl.h and ad-hoc related syms
Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h
contained various ad-hoc symbols, zap those symbols as well and rework the
board configuration a little so it doesn't depend on them.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
Marek Vasut [Sat, 18 Oct 2014 01:52:36 +0000 (03:52 +0200)]
arm: socfpga: Move code from misc_init_r() to arch_early_init_r()
Move this initialization code to proper place. The misc_init_r()
function is called way too late and the platform initialization
code should be executed much earlier.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
Jeroen Hofstee [Wed, 8 Oct 2014 20:57:23 +0000 (22:57 +0200)]
cti_flash.c: use __weak when requested for flash_(read|write){8,16,32,64}
For various reasons (design, errata) boards may need to implement their
own versions of these accessors. So in the case of
CONFIG_CFI_FLASH_USE_WEAK_ACCESSOR mark the functions as weak. In the
normal case mark them as static to allow for better optimization.
Add a Kconfig option which users can select when they want to boot older
kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces the pll5
"p" value to 1 (divide by 2) as that is what those kernels are hardcoded too,
in the future this may enable further workarounds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@ti.com>
--
Changes in v2:
-s/CONFIG_OLD_KERNEL_COMPAT/CONFIG_OLD_SUNXI_KERNEL_COMPAT.
-Move the code block setting P(1) for old kernels to where P gets cleared
Hans de Goede [Wed, 22 Oct 2014 08:47:45 +0000 (16:47 +0800)]
ARM: sunxi: Add support for R_PIO gpio banks
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.
Also add a clear description about SUNXI_GPIO_BANKS, stating it only
counts the number of pin banks in the _main_ pin controller.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: expanded commit message]
[wens@csie.org: add pin bank M and expand comments]
[wens@csie.org: add comment on SUNXI_GPIO_BANKS macro] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Chen-Yu Tsai [Tue, 7 Oct 2014 07:11:49 +0000 (15:11 +0800)]
ARM: sunxi: Fix build break when CONFIG_MMC is not defined
BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when
CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally
include it when CONFIG_MMC is enabled, as we do for CONFIG_AHCI.
This is used when we want to use uart0 from port F, which conflicts
with mmc0.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 13 Oct 2014 05:41:16 +0000 (07:41 +0200)]
sunxi: Add CONFIG_MACH_TYPE defines to sun4i, sun5i and sun7i
Many people are still using old linux-sunxi-3.4 kernels on sunxi devices,
adding the proper MACH_TYPE defines for this allows people to switch to
upstream u-boot, so that we can stop maintaining the linux-sunxi u-boot fork.
These machine-ids are all properly registered at:
http://www.arm.linux.org.uk/developer/machines/
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Fri, 3 Oct 2014 14:58:04 +0000 (16:58 +0200)]
sunxi: Enable second sdcard slot found on some boards
Enable the second sdcard slot found on some boards. Note that we do not
set CONFIG_MMC_SUNXI_SLOT_EXTRA for the SPL, as having it there is not useful,
Except for on the Mele-M3 where the second sdcard is an eMMC, from which the
device can also boot, and there we want to have both in the SPL, so that
a single u-boot binary can both from both. So for the M3 we do prefix the
defconfig setting with the special "+S:" syntax so that it applies to the
SPL too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Fri, 3 Oct 2014 14:44:57 +0000 (16:44 +0200)]
sunxi: Use PG3 - PG8 as io-pins for mmc1
None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Thu, 2 Oct 2014 19:13:54 +0000 (21:13 +0200)]
sunxi: When we've both mmc0 and mmc2, detect from which one we're booting
sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.
When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Thu, 2 Oct 2014 18:43:50 +0000 (20:43 +0200)]
sunxi: Turn MMC_SUNXI_SLOT_EXTRA into a proper Kconfig option
Note we also drop the SPL check for initializing the 2nd mmc slot, the SPL
check is not necessary with Kconfig, because only options explicitly marked
as also being for the SPL get set during SPL builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Maxime Ripard [Fri, 3 Oct 2014 12:16:29 +0000 (20:16 +0800)]
ARM: sunxi: Add basic A31 support
Add a new sun6i machine that supports UART and MMC.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
around mmc and smp code, drop MACH_TYPE] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Maxime Ripard [Fri, 3 Oct 2014 12:16:28 +0000 (20:16 +0800)]
ARM: sun6i: Setup the A31 UART0 muxing
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
[wens@csie.org: reorder #ifs by SUN?I]
[wens@csie.org: replace magic numbers with GPIO definitions] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Fri, 3 Oct 2014 12:16:26 +0000 (20:16 +0800)]
ARM: sunxi-mmc: Add mmc support for sun6i / A31
The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use setbits_le32 for reset control, drop obsolete changes,
rewrite different FIFO address handling, add commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Chen-Yu Tsai [Fri, 3 Oct 2014 12:16:25 +0000 (20:16 +0800)]
ARM: sun6i: Add clock support
This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.
This includes changes from the following commits from u-boot-sunxi:
a92051b ARM: sunxi: Add sun6i clock controller structure 1f72c6f ARM: sun6i: Setup the UART0 clocks 5f2e712 ARM: sunxi: Enable pll6 by default on all models 2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31 12e1633 ARM: sun6i: Add initial clock setup for SPL 1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code 0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe b54c626 sunxi: avoid sr32 for APB1 clock setup. 68fe29c sunxi: remove magic numbers from clock_get_pll{5,6} c89867d sunxi: clocks: clock_get_pll5 prototype and coding style 501ab1e ARM: sunxi: Fix sun6i PLL6 settings 37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets 61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: styling fixes reported by checkpatch.pl]
[wens@csie.org: drop unsupported SPL code block and unused gpio.h header] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Tom Cubie <Mr.hipboi@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Oliver Schinagl [Fri, 3 Oct 2014 12:16:24 +0000 (20:16 +0800)]
ARM: sun6i: Add support for the power reset control module found on the A31
The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.
This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: spacing fixes reported by checkpatch.pl]
[wens@csie.org: Use setbits helper in PRCM init function]
[wens@csie.org: rephrase commit message to explain what the hardware
supports and what we actually enable] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Oliver Schinagl [Fri, 3 Oct 2014 12:16:23 +0000 (20:16 +0800)]
ARM: sun6i: Add base address for the new controllers in A31
A31 has several new and changed memory address. This patch adds them.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Chen-Yu Tsai [Fri, 3 Oct 2014 12:16:22 +0000 (20:16 +0800)]
ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined
BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
projects / u-boot / log