Tom Warren [Mon, 28 Jan 2013 13:32:11 +0000 (13:32 +0000)]
Tegra114: Dalmore: Add DT files
These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).
Tom Warren [Mon, 28 Jan 2013 13:32:09 +0000 (13:32 +0000)]
Tegra114: Add CPU (armv7) files
These files are for code that runs on the CPU (A15) on T114 boards.
At this time, there is no A15-specific code here.
As T114-specific run-time code is added, it'll go here.
Tom Warren [Mon, 28 Jan 2013 13:32:07 +0000 (13:32 +0000)]
Tegra114: Add arch-tegra114 include files
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Allen Martin [Tue, 29 Jan 2013 13:51:28 +0000 (13:51 +0000)]
tegra: add SPI SLINK driver
Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Tue, 29 Jan 2013 13:51:24 +0000 (13:51 +0000)]
tegra: spi: add fdt support to tegra SPI SFLASH driver
Add support for configuring tegra SPI driver from devicetree.
Support is keyed off CONFIG_OF_CONTROL. Add entry in seaboard dts
file for spi controller to describe seaboard spi.
Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
AM335X: Set fdt_high for AM335X devices to enable booting with Device Tree
For AM335X boards, such as the EVM and Bone Linux kernel fails to
locate the device tree blob on boot. The reason being is that
u-boot is copying the DT blob to the upper part of RAM when booting
the kernel and the kernel is unable to access the blob.
By setting the fdt_high variable to 0xffffffff (to prevent the copy)
the kernel is able to locate the DT blob and boot.
This patch is tested on BeagleBone platform.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Tom Rini <trini@ti.com>
Jeff Lance [Mon, 14 Jan 2013 05:32:20 +0000 (05:32 +0000)]
Add DDR3 support for AM335x-EVM (Version 1.5A)
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.
[Hebbar Gururaja <gururaja.hebbar@ti.com>]
- Resolve merge conflict while rebasing. File structure is
changed in the mainline. So re-arrange the code accordingly.
- Update commit message to reflect the DDR3 part number
Signed-off-by: Jeff Lance <j-lance1@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
Lars Poeschel [Fri, 11 Jan 2013 00:53:32 +0000 (00:53 +0000)]
am335x: display msg when reading MAC from efuse
When ethaddr is not set in environment the MAC address is read
from efuse. The message was only printed in debug case, but this
message could be of interest for the ordinary user, so printf it.
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
Lars Poeschel [Fri, 11 Jan 2013 00:53:31 +0000 (00:53 +0000)]
pcm051: Add support for Phytec phyCORE-AM335x
The board is named pcm051 and has this hardware:
SOC: TI AM3359
DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB
ETH 1: LAN8710AI
SPI-Flash: W25Q64BVSSIG
RTC: RV-4162-C7
I2C-EEPROM: CAT32WC32
NAND: MT29F4G08_VFPGA63
PMIC: TPS65910A3
LCD
Supported:
UART 1
MMC/SD
ETH 1
USB
I2C
SPI
Not yet supported:
NAND
RTC
LCD
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
[trini: Add #define CONFIG_PHY_ADDR 0 to config] Signed-off-by: Tom Rini <trini@ti.com>
omap4: allow the use of a plain text env file instead boot scripts
For production systems it is better to use script images since
they are protected by checksums and carry valuable information like
name and timestamp. Also, you can't validate the content passed to
env import.
But for development, it is easier to use the env import command and
plain text files instead of script-images.
Since both OMAP4 supported boards (Panda and TI SDP4430) are used
primarily for development, this patch allows U-Boot to load env var
from a text file in case that an boot.scr script-image is not present.
The variable uenvcmd (if existent) will be executed (using run) after
uEnv.txt was loaded. If uenvcmd doesn't exist the default boot sequence
will be started.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Nishanth Menon <nm@ti.com>
Even when the IGEPv2 board and the IGEP Computer-on-Module
are different from a form factor point of view, they are
very similar in the fact that share many components and how
they are wired.
So, it is possible (and better) to have a single board file
for both devices and just use the CONFIG_MACH_TYPE to make
a differentiation between each board when needed.
This change avoids code duplication by removing 298 lines of
code and makes future maintenance easier.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
After stress test, I found some of kzm9g board occures memory failure.
This patch adust SDRAM setting.
- Enlarge drivability on both SDRAM controller and SDRAM itself
- Raise core voltage
Marek Vasut [Tue, 22 Jan 2013 15:01:00 +0000 (15:01 +0000)]
mxs: dma: Fix APBH DMA driver for MX23
The MX23 has less channels for the APBH DMA, sligtly different register
layout and some bits in those registers are placed differently. Reflect
this in the driver. This patch fixes MMC/DMA issue on MX23.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Mon, 14 Jan 2013 08:59:24 +0000 (08:59 +0000)]
mx6qsabre_common: Let mmc partition be board specific
commit 49ea0ff5 (49ea0ff5) introduced CONFIG_SYS_MMC_ENV_PART into mx6qsabresd.h
to store the mmc partition, but in order for it to have effect we should place
it into 'mmcpart' variable.
Also add CONFIG_SYS_MMC_ENV_PART into mx6qsabreauto.h.
Marek Vasut [Fri, 11 Jan 2013 03:19:06 +0000 (03:19 +0000)]
mx23: Add POWER and CLKCTRL register definitions
Add register definitions for the i.MX23 power control block and
clock control block. These are essential for the basic bootstrap
of the i.MX23. Also, properly include them in imx-regs.h .
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
Otavio Salvador [Fri, 11 Jan 2013 03:19:04 +0000 (03:19 +0000)]
mx23: Add register base addresses
This adds the base addresses of i.MX23 and easy the detection of wrong
order in board setup, in case no SoC has been set, an error is raised
during build.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Fri, 11 Jan 2013 03:19:02 +0000 (03:19 +0000)]
mxs: ssp: Pull out the SSP bus to regs conversion
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
Allen Martin [Tue, 8 Jan 2013 16:07:54 +0000 (16:07 +0000)]
fdt: fix dts preprocessor options
Using "-ansi" preprocessor option will cause dts lines that begin with
'#' to choke the preprocessor. Change to "-x assembler-with-cpp"
instead which is what the kernel uses to preprocess dts files.
Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Warren [Fri, 21 Dec 2012 22:59:15 +0000 (15:59 -0700)]
Tegra30: fdt: Update DT files with I2C info for T30/Cardhu
Note that T30 does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
DVC_I2C is still used to designate the controller intended for
power control (PWR_I2C in the schematics). On Cardhu, it's used
to access the PMU and EEPROM, as well as the audio codec, temp
sensor, and fuel gauge devices from the OS.
Tom Warren [Tue, 11 Dec 2012 13:34:16 +0000 (13:34 +0000)]
Tegra30: Cardhu: Add DT files
These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tom Warren [Tue, 11 Dec 2012 13:34:14 +0000 (13:34 +0000)]
Tegra30: Add CPU (armv7) files
These files are for code that runs on the CPU (A9) on T30 boards.
At this time, there are no T30-specific ARMV7 files. As T30-specific
run-time code is added, it'll go here.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidai.com>
Tom Warren [Tue, 11 Dec 2012 13:34:12 +0000 (13:34 +0000)]
Tegra30: Add arch-tegra30 include files
Common Tegra files are in arch-tegra, shared between T20 and T30.
Tegra30-specific headers are in arch-tegra30. Note that some of
these will be filled in as more T30 support is added (drivers,
WB/LP0 support, etc.). A couple of Tegra20 files were changed
to support common headers in arch-tegra, also.
Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
Thierry Reding [Fri, 23 Nov 2012 00:58:51 +0000 (00:58 +0000)]
tegra: Enable LCD on TEC
The TEC ships with a 7" LCD panel that provides a resolution of 800x480
pixels. Add a corresponding panel description to the device tree and
enable LCD support in the configuration.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Fri, 23 Nov 2012 00:58:50 +0000 (00:58 +0000)]
tegra: Enable LCD on Medcom-Wide
The Medcom-Wide has a 15" LCD panel with a resolution of 1366x768
pixels. Add a corresponding panel description to the device tree and
enable LCD support in the configuration.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Thierry Reding [Fri, 23 Nov 2012 00:58:49 +0000 (00:58 +0000)]
video: tegra: Update line length to match resolution
Instead of storing the computed line length in a local variable, store
it in the global lcd_line_length variable to make sure the LCD subsystem
can properly draw content for the display resolution.
This probably wasn't noticed yet because the only board where LCD
support is currently enabled is Seaboard, which runs at a 1366x768
resolution. As it happens this is the maximum resolution supported and
also the default that is used to initialize the framebuffer before the
configuration from DT is available.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Łukasz Dałek [Sat, 12 Jan 2013 11:39:27 +0000 (11:39 +0000)]
pxa: Save lr register in relocate_code function
When u-boot is compiled for PXA25x processor, pxa/start.S is calling
cpu_init_crit by BL instruction. BL is overwriting lr register so
relocate_code is going into infinite loop. This patch preservs lr
register in r12 before calling cpu_init_crit and after function returns
restores it.
Signed-off-by: Lukasz Dalek <luk0104@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
projects / u-boot / log