Stefan Roese [Thu, 7 Jan 2016 13:12:04 +0000 (14:12 +0100)]
arm: mvebu: Add runtime detection of UART (xmodem) boot-mode
This patch adds runtime detection of the Marvell UART boot-mode (xmodem
protocol). If this boot-mode is detected, SPL will return to the
BootROM to continue the UART booting.
With this patch its now possible, to generate a U-Boot image that
can be booted either from the strapped boot-device (e.g. SPI NOR, MMC,
etc) or via the xmodem protocol from the UART. In the UART case,
the kwboot tool will dynamically insert the UART boot-device type
into the image. And also patch the load address in the header, so
that the mkimage header will be skipped (as its not expected by the
Marvell BootROM).
This simplifies the development for Armada XP / 38x based boards.
As no special images need to be generated by selecting the
MVEBU_BOOTROM_UARTBOOT Kconfig option.
Since the Kconfig option MVEBU_BOOTROM_UARTBOOT is not needed any
more, its now completely removed.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Stefan Roese [Thu, 7 Jan 2016 13:09:09 +0000 (14:09 +0100)]
arm: mvebu: Add runtime boot-device detection
This patch adds runtime boot-device detection to SPL U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Stefan Roese [Thu, 7 Jan 2016 13:04:51 +0000 (14:04 +0100)]
arm: mvebu: Make local structs static const
As these structs are local only and const, declare them accordingly.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Stefan Roese [Thu, 7 Jan 2016 13:03:11 +0000 (14:03 +0100)]
arm: mvebu: Move SAR register defines into header
This is preparation for the runtime bootmode detection in spl.c.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Stefan Roese [Mon, 21 Dec 2015 13:30:30 +0000 (14:30 +0100)]
arm: mvebu: Remove leftover Makefile
This Makefile was not used since quite some time. I only missed to
remove it in the move to mach-mvebu. So lets remove it now so
that the mvebu-common directory is really removed completely.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 21 Dec 2015 12:56:33 +0000 (13:56 +0100)]
arm: mvebu: Move SoC selection (A38X vs AXP) into Kconfig
Until now, the SoC selection for the ARCH_MVEBU platforms has been done
in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As
it needed to get selected for AXP and A38x based boards. This patch
now changes this to move the SoC selection to Kconfig. And also
uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x.
This makes things a bit clearer - especially for new board additions.
Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and
CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available
CONFIG_ARMADA_38X and CONFIG_ARMADA_XP.
And CONFIG_DDR3 is removed, as its not referenced anywhere.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Fri, 11 Dec 2015 07:24:20 +0000 (08:24 +0100)]
arm: mvebu: Don't include "netdev.h" in cpu.c
This is not needed any more since the switch to DM / DTS network
initialization on MVEBU. Lets remove it, as it otherwise leads
to compilation warning when CONFIG_NET is not enabled.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 10 Dec 2015 14:02:38 +0000 (15:02 +0100)]
arm: mvebu: Make ECC support configurable on Armada XP
Currently, ECC support is enabled for all Armada XP boards. So the
DDR3 driver tries to configure the controller with ECC support, even
on boards without ECC. This patch makes this ECC optional which now
can be configured on a board-per-board basis.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
Stefan Roese [Wed, 9 Dec 2015 10:00:51 +0000 (11:00 +0100)]
arm: mvebu: Add support for MV78260
This patch adds support for the dual core Armada XP variant, the
MV78260. It has some minor differences to the 4-core MV78460,
e.g. only 12 serdes lanes.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
Stefan Roese [Thu, 3 Dec 2015 11:39:45 +0000 (12:39 +0100)]
arm: mvebu: Don't disable cache at startup on Armada XP at all
This patch leaces the cache configuration untouched for the AXP in the
setup done by the BootROM. Resulting in the cache still being enabled
at the startup of U-Boot. This leads to a slightly faster boot to the
U-Boot prompt (or Linux of course).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 3 Dec 2015 11:39:45 +0000 (12:39 +0100)]
arm: mvebu: Don't call arch_cpu_init() from SPL at all
This patch removes the call to arch_cpu_init() in the SPL U-Boot version.
As SPL does not need all the configuration done in this function. And
also does not need the reconfiguration of the internal register
address to 0xf1000000. This will be done by the main U-Boot later on.
This also fixes a problem with the timer not beeing initialized on AXP,
as needed for the mdelay in the setup_usb_phys(). This will now only
be called once in main U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 14 Dec 2015 11:31:48 +0000 (12:31 +0100)]
arm: mvebu: Add v7_outer_cache_disable function for AXP & A38x
Add functionality to correctly disable the L2 cache on the Armada XP
and 38x platforms.
Without this, booting into Linux on ClearFog (A38x) results in a hangup
without any output on the serial console at all. Even with earlyprintk
enabled.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 3 Dec 2015 11:39:45 +0000 (12:39 +0100)]
arm: mvebu: Enable L2 cache on Armada XP
Until now, the L2 cache was never enabled again in U-Boot. To get
even better performance (bootup time), lets enable the L2 cache
in U-Boot. This code was taken from the Linux kernel.
A performance gain was measured on the DB-MV784MP-GP board by testing
with tftpboot and sata commands.
This patch also cleans up the L2 cache related code. And makes sure that
the L2 cache is only disabled once.
Please note that A38x still runs with L2 cache disabled. And needs
to be enabled for this SoC in a separate patch if needed or desired.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 3 Dec 2015 11:39:45 +0000 (12:39 +0100)]
arm: mvebu: db-mv784mp-gp: Switch from IDE to SATA support
Enable the newly introduced SATA driver for the Marvell AXP with DMA
support instead of the PIO-only IDE driver. This increases the
transfer speed. And is also more in-line with the Armada 38x
ports, which also use a SATA driver (AHCI) and the "sata" U-Boot
commands.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Tor Krill [Thu, 3 Dec 2015 11:38:02 +0000 (12:38 +0100)]
sata: Add SATA driver with DMA support for Marvell Kirkwood and Armada XP
This patch adds a new SATA driver for the Marvell Kirkwood and Armada
370 / XP SoC's.
This driver supports the SATA controller of some Mavell SoC's.
Here a (most likely incomplete) list of the supported SoC's:
- Kirkwood
- Armada 370
- Armada XP
This driver implementation is an alternative to the already available
driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
But this driver only supports PIO mode and as this new driver also
supports transfer via DMA, its much faster.
Please note, that the newer SoC's (e.g. Armada 38x) are not supported
by this driver. As they have an AHCI compatible SATA controller
integrated.
The original version of this driver was sent by Tor Krill to the U-Boot
list a few years ago. Here the link:
Changes by Stefan:
- Coding-style cleanup
- Support for Armada XP added
- MBUS window setup added
- D-cache flush and invalidation added - works with dcache enabled on
Armada XP
- Removed mdelay() from ata_wait_register() and add timer based timeout
detection to speed up the transfer
Signed-off-by: Tor Krill <tor@excito.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Tom Rini <trini@konsulko.com>
Stefan Roese [Tue, 20 Oct 2015 13:14:47 +0000 (15:14 +0200)]
arm: mvebu: Add SolidRun ClearFog Armada 38x initial support
This patch adds basic support for the SolidRun ClearFog Armada 38x based
board to mainline U-Boot. Supported interfaces / devices are:
- DDR3
- UART
- MMC
- Ethernet port 0 (connected to dedicated PHY)
- I2C
The included DT source was taken from Russell King's ftp server:
http://www.home.arm.linux.org.uk/~rmk/clearfog/
With only minor modifications, like the addition of some aliases and the
"u-boot,dm-pre-reloc" property.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 19 Nov 2015 06:46:15 +0000 (07:46 +0100)]
net: mvneta: Convert to driver model
Update this driver to support driver model. As all MVEBU boards using
this driver are converted with this patch, the non-driver-model code
can be removed completely. This is also the reason why this patch
is quite big and includes a) the driver change and b) the
platform change. As its not git-bisect save otherwise.
With this conversion, some parameters are now extracted from the
DT instread of using the config header defines. The supported
properties right now are:
PHY-mode ("phy-mode") and PHY-address ("reg").
The base addresses for the ethernet controllers can be removed from
the header files as well.
Please note that this patch also removes the E1000 network driver
from some MVEBU config headers. This is necessary, as with DM_ETH
configured and the e1000 driver enabled, the PCI driver also needs
to support DM. But the MVEBU PCI(e) driver still needs to get
ported to DM. When this is done, the E1000 driver can be enabled
again.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Simon Glass <sjg@chromium.org>
Stefan Roese [Thu, 19 Nov 2015 10:03:25 +0000 (11:03 +0100)]
arm: mvebu: Add armada-xp-maxbcm.dts for maxbcm board
This is needed for the upcoming ethernet DM conversion of the maxbcm
board. The configuration of the PHY is then extracted from the DT
instead of using the defines from the config header.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Fri, 20 Nov 2015 12:51:57 +0000 (13:51 +0100)]
arm: mvebu: Add SPI driver model support
This patch enables the DM support for the SPI driver and the
SPI NOR flash chips. Some MVEBU boards boot from SPI NOR, so
adding the aliases and enabling CONFIG_DM_SEQ_ALIAS is needed
here.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 20 Nov 2015 12:39:43 +0000 (13:39 +0100)]
spi: kirkwood_spi.c: Add driver model support
This patch adds driver model support to the kirkwood SPI driver. Which
is also used on the MVEBU SoC's, now being converted to DM. Non-DM
support is still available for the "older" platforms using this
driver, like kirkwood.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 20 Nov 2015 07:44:21 +0000 (08:44 +0100)]
spi: kirkwood_spi.c: Prepare for driver model support
This patch prepares the Kirkwood SPI driver, also used on the MVEBU board
(Armada XP / 38x), for the conversion to driver model.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
Stefan Roese [Wed, 25 Nov 2015 06:37:00 +0000 (07:37 +0100)]
arm: mvebu: Add DM and OF_CONTROL support to SPL
This patch adds full DM support to the SPL on MVEBU. Currently
only serial is supported. Other drivers will follow.
This patch also adds the necessary config values for the DEBUG UART
to the MVEBU defconfig files. This came in handy while implementing
this DM support.
Additionally, the mvebu specific SPL linker script is removed and
this common one is used instead:
arch/arm/cpu/u-boot-spl.lds
This common linker script already handles all special cases. No need
to reinvent the wheel for MVEBU here.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Simon Glass <sjg@chromium.org>
Stefan Roese [Thu, 19 Nov 2015 12:50:10 +0000 (13:50 +0100)]
arm: mvebu: ddr: Fix compilation warning
gcc 5.1 generates this new warning (for Armada 38x platforms):
drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result':
drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array
function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument]
memcpy(result, training_result, sizeof(result));
^
drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here
u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
^
Since this functions is not referenced anywhere, lets just remove it.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Peng Fan [Tue, 12 Jan 2016 09:23:12 +0000 (17:23 +0800)]
common: env_flags: fix loop condition when using env_flags_varaccess_mask
We should use ARRAY_SIZE, but not sizeof. The size of
env_flags_varaccess_mask is 16bytes, but we only need 4 loops.
If using 16 as the end condition, we may access memory that
not belong to array env_flags_varaccess_mask.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: York Sun <yorksun@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Peng Fan [Sun, 10 Jan 2016 05:01:22 +0000 (13:01 +0800)]
common: cli_simple: use strlcpy instead of strcpy
Report Coverity log:
Destination buffer too small (STRING_OVERFLOW)
string_overflow: You might overrun the 1024 byte destination string
lastcommand by writing 1025 bytes from console_buffer
Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Add a 'poweroff' command to boot commands, this only gets enabled if the
board Kconfig does a "select CMD_POWEROFF".
Signed-off-by: Michael van Slingerland <michael@deviousops.nl>
[hdegoede@redhat.com: Make the cmd conditional on a CMD_POWEROFF Kconfig] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
net: lpc32xx: fix ignored MDIO busy wait status on read
The change fixes PHY write operation, which incorrectly waits for
released busy state before issuing a write operation, this breaks
sequential write/read operation logic, because read operation
starts immediately on request and it completes, when busy state is
gone.
Instead of adding the second preceding busy state check to read
function, do busy state release check after issuing a write operation,
this method of operation is also recommended by the LPC32xx User's
Manual, see MII Mgmt Indicators Register notes:
For PHY Write if scan is not used:
1. Write 0 to MCMD
2. Write PHY address and register address to MADR
3. Write data to MWTD
4. Wait for busy bit to be cleared in MIND
Reported-by: Alexandre Messier <amessier@tycoint.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Alexandre Messier <amessier@tycoint.com>
The change updates DevKit3250 board powerd by NXP LPC3250 SoC:
* due to increased resulting U-boot image size give more space to
store loaded and relocated versions,
* add DMA support, which is used by NAND SLC driver,
* add NXP OHCI and PHY drivers to the image,
* add USB, JFFS and FAT commands.
For NXP LPC32xx boards the change enables SPL_DM option, this allows
to use any driver model UART driver in SPL images, hence a restriction
on HSUART in SPL image is removed and well as definitions for non-DM
NS16550 driver, its DM version is used instead.
Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE
for LPC32xx boards.
The change adds about 5KB to the resulting SPL image (for devkit3250
board SPL image is increased from 10672 to 15608 bytes).
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
arm: lpc32xx: switch serial console to driver model
On NXP LPC32xx platform for non-SPL builds the change adds
standard (NS16550) and high-speed UARTs to driver model.
Due to specific of DM NS16550 device description UART clock can not be
got in runtime and by default it is set to 13MHz, if board PERIPH_CLK
is different, this should be specified in board configuration file.
For SPL builds HSUARTs are disabled and non-DM NS16550 driver is
compiled, if needed.
The change also updates default configs of devkit3250 and work_92105
boards to reflect updates in platform files.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Mon, 14 Dec 2015 22:01:15 +0000 (15:01 -0700)]
test/fs: error case fixes/enhancements
- Use "mkdir -p" to avoid errors when intermediate directories are
missing.
- Fall back to "dd" when "fallocate" fails. For example, fallocate isn't
supported on ext4.
- Add error checking for test image generation. Without this, the test
simply plows on spewing all kinds of errors which are hard to
immediately root-cause.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tom Rini [Thu, 10 Dec 2015 21:42:21 +0000 (16:42 -0500)]
ext4_common.c: Clean up failure cases in alloc_triple_indirect_block
As noted by Coverity, when we have an error in
alloc_triple_indirect_block we will leak ti_pbuff_start_addr as it's not
being freed. Further inspection here shows that we could also leak
ti_cbuff_start_addr in one corner case so free that as well.
Reported-by: Coverity (CID 131205, 131206) Signed-off-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Mon, 7 Dec 2015 18:38:50 +0000 (11:38 -0700)]
ums: support multiple LUNs at once
Extend the ums command to accept a list of block devices. Each of these
will be exported as a separate LUN. An example use-case would be:
ums 0 mmc 0,0.1,0.2
... which would export LUNs for eMMC 0's user data, boot0, and boot1 HW
partitions. This is useful since it allows the host access to everything
on the eMMC without having to somehow stop the ums command from executing
and restart it with different parameters.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Mon, 7 Dec 2015 18:38:49 +0000 (11:38 -0700)]
mmc: store hwpart in the block device
This will allow us to have multiple block device structs each referring
to the same eMMC device, yet different HW partitions.
For now, there is still a single block device per eMMC device. As before,
this block device always accesses whichever HW partition was most recently
selected. Clients wishing to make use of multiple block devices referring
to different HW partitions can simply take a copy of this block device
once it points at the correct HW partition, and use each one as they wish.
This feature will be used by the next patch.
In the future, perhaps get_device() could be enhanced to return a
dynamically allocated block device struct, to avoid the client needing to
copy it in order to maintain multiple block devices. However, this would
require all users to be updated to free those block device structs at some
point, which is rather a large change.
Most callers of mmc_switch_part() wish to permanently switch the default
MMC block device's HW partition. Enhance mmc_switch_part() so that it does
this. This removes the need for callers to do this. However,
common/env_mmc.c needs to save and restore the current HW partition. Make
it do this more explicitly.
Replace use of mmc_switch_part() with mmc_select_hwpart() in order to
remove duplicate code that skips the call if that HW partition is already
selected.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Mon, 7 Dec 2015 18:38:48 +0000 (11:38 -0700)]
block: pass block dev not num to read/write/erase()
This will allow the implementation to make use of data in the block_dev
structure beyond the base device number. This will be useful so that eMMC
block devices can encompass the HW partition ID rather than treating this
out-of-band. Equally, the existence of the priv field is crying out for
this patch to exist.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Albert ARIBAUD [Wed, 25 Nov 2015 16:56:33 +0000 (17:56 +0100)]
arm: move gd handling outside of C code
As of gcc 5.2.1 for Thumb-1, it is not possible any
more to assign gd from C code, as gd is mapped to r9,
and r9 may now be saved in the prolog sequence, and
restored in the epilog sequence, of any C functions.
Therefore arch_setup_gd(), which is supposed to set
r9, may actually have no effect, causing U-Boot to
use a bad address to access GD.
Fix this by never calling arch_setup_gd() for ARM,
and instead setting r9 in arch/arm/lib/crt0.S, to
the value returned by board_init_f_alloc_reserve().
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Simon Glass <sjg@chromium.org>
Albert ARIBAUD [Wed, 25 Nov 2015 16:56:32 +0000 (17:56 +0100)]
Fix board init code to respect the C runtime environment
board_init_f_mem() alters the C runtime environment's
stack it is actually already using. This is not a valid
behaviour within a C runtime environment.
Split board_init_f_mem into C functions which do not alter
their own stack and always behave properly with respect to
their C runtime environment.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Thomas Chou <thomas@wytron.com.tw>
The function hash_show is now only called by hash_command, so mark it as
static (and drop from hash.h). We only call hash_command when any of
CONFIG_CMD_CRC32, CONFIG_CMD_SHA1SUM or CONFIG_CMD_HASH are set. Since
hash.c is linked in unconditionally we must take extra care with
functions that bring in read-only strings as these will not be
discarded.
Masahiro Yamada [Thu, 17 Dec 2015 08:19:35 +0000 (17:19 +0900)]
image: check "bootm_low" and "bootm_size" if "initrd_high" is missing
To boot Linux, we should prevent Initramdisk and FDT from going too
high.
Currently, boot_relocate_fdt() checks "fdt_high" environment first,
and then falls back to getenv_bootm_mapsize() + getenv_bootm_low()
if "fdt_high" is missing.
On the other hand, boot_ramdisk_high() only checks "initrd_high" to
get the address limit for the Initramdisk. We also want to let this
case fall back to getenv_bootm_mapsize() + getenv_bootm_low().
Mugunthan V N [Wed, 23 Dec 2015 15:09:36 +0000 (20:39 +0530)]
dm: core: Add a new api to get indexed device address
Add new api to get device address based on index.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Jagan Teki <jteki@openedev.com>
[Rebased on master] Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 5 Jan 2016 08:14:26 +0000 (13:44 +0530)]
power: pmic.h: Drop include <spi.h>
include/power/pmic.h never used any generic spi code
from include/spi.h, but this has been added in below commit.
"dm: pmic: add implementation of driver model pmic uclass"
(sha1: 4d9057e82be11a862db411c4867e859fe0d4ca2a)
Adding functionalities in include/spi.h will trigger a build
issue as this been added used in include/power/pmic.h
Build issue on trats2 with adding BIT macro on spi.h:
----------------------------------------------------
CC lib/asm-offsets.s
In file included from include/power/pmic.h:15:0,
from include/power/max77686_pmic.h:11,
from include/configs/trats2.h:212,
from include/config.h:5,
from include/common.h:18,
from lib/asm-offsets.c:15:
include/spi.h: In function 'spi_w8r8':
include/spi.h:327:2: warning: implicit declaration of function 'BIT' [-Wimplicit-function-declaration]
Cc: Simon Glass <sjg@chromium.org> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
Mugunthan V N [Wed, 23 Dec 2015 15:09:49 +0000 (20:39 +0530)]
defconfig: am437x_sk_evm: enable spi driver model
enable spi driver model for am437x_sk_evm as ti_qspi supports
driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Mugunthan V N [Wed, 23 Dec 2015 15:09:46 +0000 (20:39 +0530)]
defconfig: dra74_evm: enable spi driver model
enable spi driver model for dra74_evm as ti_qspi supports
driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Mugunthan V N [Wed, 23 Dec 2015 15:09:45 +0000 (20:39 +0530)]
defconfig: dra72_evm: enable spi driver model
enable mmc driver model for dra72_evm as ti_qspi supports
driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Mugunthan V N [Wed, 23 Dec 2015 15:09:40 +0000 (20:39 +0530)]
drivers: spi: ti_qspi: convert driver to adopt device driver model
adopt ti_qspi driver to device driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Mugunthan V N [Wed, 23 Dec 2015 15:09:37 +0000 (20:39 +0530)]
spi: Add support for dual and quad mode
spi bus can support dual and quad wire data transfers for tx and
rx. So defining dual and quad modes for both tx and rx. Also add
support to parse bus width used for spi tx and rx transfers.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Mugunthan V N [Wed, 23 Dec 2015 15:09:34 +0000 (20:39 +0530)]
drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion
Changing the ti_qspi_priv structure and its instance names from
to priv for driver mode conversion.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Mugunthan V N [Wed, 23 Dec 2015 15:09:33 +0000 (20:39 +0530)]
drivers: spi: ti_qspi: do not hard code chip select for memory map configuration
To enable memory map in dra7xx, specific chip select must be
written to control module register. But this hard coded to chip
select 1, fixing it by writing the specific chip select value to
control module register.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 28 Dec 2015 17:25:50 +0000 (22:55 +0530)]
spi: Add SPI_TX_DUAL mode
Added SPI_TX_DUAL mode flag.
Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 29 Dec 2015 06:42:30 +0000 (12:12 +0530)]
spi: Minor cleanup
- Add comments on mode_rx
- Tab space's
Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 28 Dec 2015 16:54:08 +0000 (22:24 +0530)]
spi: Use BIT macro
Used BIT macro like 1 << nr as BIT(nr) where nr is 0...n
Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Wed, 16 Dec 2015 10:21:06 +0000 (15:51 +0530)]
spi: Fix bit assignment with flags
Fixed bit assignment with flags members on spi_slave{}
Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 28 Dec 2015 16:53:14 +0000 (22:23 +0530)]
spi: Move flags macro's to spi_slave{} members
This patch moves flags macro's to respective member
position on spi_slave{}, for better readabilty and
finding the respective member macro's easily.
Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Wed, 16 Dec 2015 09:54:24 +0000 (15:24 +0530)]
spi: Rename op_mode_rx to mode_rx
Since spi rx mode macro's are renamed to simple and
meaninfull, this patch will rename the respective
structure members.
Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Wed, 16 Dec 2015 09:31:23 +0000 (15:01 +0530)]
spi: Remove SPI_OPM_RX_DIO|QIOF
SPI_OPM_RX_DIO and SPI_OPM_RX_QIOF are rx IO
commands/opmodes for dual and quad. Usually IO
operation's are referred to flash protocol rather
with spi controller protocol, these are still present
in flash side for the usage of spi-nor controllers.
Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Wed, 16 Dec 2015 09:23:59 +0000 (14:53 +0530)]
spi: Remove SPI_OPM_RX_EXTN
SPI_OPM_RX_EXTN is a combination of all rx opmode's
and spi driver shall use any one of the rx mode at
a time not the combination and it is true in case of
flash where spi_flash_table mention combination of
supported read opmodes so-that the required one
will pick based on the rx mode from spi driver.
Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Wed, 16 Dec 2015 08:18:08 +0000 (13:48 +0530)]
sf: Write quad bit along with read status
While setting quad bit on spansion, macronix code
is writing only particular quad bit this may give
wrong functionality with other register bits,
So this patch fix the issue where it with write
previous read reg status along particular quad bit.
Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 15 Dec 2015 07:12:02 +0000 (12:42 +0530)]
sf: Read back and check once macronix quad bit set
One macronix quad bit set using SR, it's good to
read back and check the written bit and also if
it's already been set check for the bit and return.
Cc: Vignesh R <vigneshr@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Tue, 15 Dec 2015 06:58:39 +0000 (12:28 +0530)]
sf: Read back and check once spansion quad bit set
One spansion quad bit set using CR, it's good to
read back and check the written bit and also if
it's already been set check for the bit and return.
Cc: Vignesh R <vigneshr@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Mon, 14 Dec 2015 12:45:39 +0000 (18:15 +0530)]
sf: Fix quad bit set for micron devices
Setting up quad bit for micron devices need to do the
same way as other flash devices like spansion, winbond
etc does using enhanced volatile config register so this
patch adds this support instead of printing "QEB is volatile"
Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Peter Pan <peterpandong@micron.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Sun, 13 Dec 2015 14:40:33 +0000 (20:10 +0530)]
spi: Use mode instead of op_mode_tx
Used mode member from spi_slave{} instead of op_mode_tx.
Cc: Simon Glass <sjg@chromium.org> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>