]> git.sur5r.net Git - u-boot/log
u-boot
11 years agoomap-common/hwinit-common.c: Mark omap_rev_string as static
Tom Rini [Fri, 31 May 2013 14:44:23 +0000 (10:44 -0400)]
omap-common/hwinit-common.c: Mark omap_rev_string as static

Only called in this file, mark as static.

Signed-off-by: Tom Rini <trini@ti.com>
11 years agoarm: factorize relocate_code routine
Albert ARIBAUD [Sun, 19 May 2013 01:48:15 +0000 (01:48 +0000)]
arm: factorize relocate_code routine

Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
11 years agoarm: do not compile relocate_code() for SPL builds
Albert ARIBAUD [Sun, 19 May 2013 01:48:14 +0000 (01:48 +0000)]
arm: do not compile relocate_code() for SPL builds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
11 years agotx25: copy SPL directly, not using relocate_code.
Albert ARIBAUD [Sun, 19 May 2013 01:48:13 +0000 (01:48 +0000)]
tx25: copy SPL directly, not using relocate_code.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
11 years agomx31pdk: copy SPL directly, not using relocate_code.
Albert ARIBAUD [Sun, 19 May 2013 01:48:12 +0000 (01:48 +0000)]
mx31pdk: copy SPL directly, not using relocate_code.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
11 years agoMerge branch 'u-boot/master' into 'u-boot-arm/master'
Albert ARIBAUD [Thu, 30 May 2013 12:45:06 +0000 (14:45 +0200)]
Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c

11 years agotegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL build
Axel Lin [Tue, 21 May 2013 13:45:18 +0000 (13:45 +0000)]
tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL build

Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_crit
Axel Lin [Tue, 21 May 2013 13:44:10 +0000 (13:44 +0000)]
ARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_crit

cpu_init_crit() can be skipped, but the code is still enabled requiring a
platform to supply lowlevel_init().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: tegra: support SKU 7 of Tegra20
Stephen Warren [Fri, 17 May 2013 14:10:15 +0000 (14:10 +0000)]
ARM: tegra: support SKU 7 of Tegra20

Make U-Boot aware of the Tegra20 SKU 7, and treat it identically
to any other Tegra20.

My Whistler board has a SoC with this SKU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: tegra: support SKU 1 of Tegra114
Stephen Warren [Fri, 17 May 2013 14:10:14 +0000 (14:10 +0000)]
ARM: tegra: support SKU 1 of Tegra114

Make U-Boot aware of the Tegra114 SKU 1, and treat it identically
to any other Tegra114.

This value is used on (at least some) Dalmore boards with a production
rather than engineering chip. Such boards are in the hands of some
partners who want to use upstream U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agotegra: always build u-boot-nodtb-tegra.bin
Stephen Warren [Tue, 14 May 2013 08:00:53 +0000 (08:00 +0000)]
tegra: always build u-boot-nodtb-tegra.bin

Even when eventually building u-boot-dtb-tegra.bin, separately building
u-boot-nodtb-tegra.bin can be useful, since building it encapsulates the
SPL padding step. If you want to tweak u-boot.dtb and regenerate
u-boot-dtb-tegra.bin, it is then a simple cat operation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoTegra: clk: always use find_best_divider() for periph clocks
Allen Martin [Fri, 10 May 2013 16:56:55 +0000 (16:56 +0000)]
Tegra: clk: always use find_best_divider() for periph clocks

When adjusting peripheral clocks always use find_best_divider()
instead of clk_get_divider() even when a secondary divider is not
available.  In the case where is requested clock is too slow to be
derived from the parent clock this allows a best effort to get close
to the requested clock.

This comes up for commands like "sf" where the user can pass a clock
speed on the command line or "sspi" where the clock is hardcoded to
1MHz, but the Tegra114 SPI controller can't go that low.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoTegra: Remove unused/non-existent spl linker script reference
Tom Warren [Wed, 17 Apr 2013 15:24:57 +0000 (08:24 -0700)]
Tegra: Remove unused/non-existent spl linker script reference

Tegra builds use the common u-boot-spl.lds now.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhu
Tom Warren [Tue, 16 Apr 2013 22:57:51 +0000 (15:57 -0700)]
Tegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhu

Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both
board and board_name == beaver. Didn't test as I have no T30
Beaver board here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
11 years agopowerpc/mpc85xx: Clear L1 D-cache lock
York Sun [Fri, 5 Apr 2013 13:07:13 +0000 (13:07 +0000)]
powerpc/mpc85xx: Clear L1 D-cache lock

dcbi instruction has been used to clear D-cache lock. However, the cache
lock is persistent for e6500 core. Use dcblc to clear the lock explicitly.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoSECURE BOOT - Removed deletion of TLB entries code
Ruchika Gupta [Mon, 25 Mar 2013 07:40:25 +0000 (07:40 +0000)]
SECURE BOOT - Removed deletion of TLB entries code

Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete TLB entries after CPU initialization
is no longer required.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Acked-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Shaveta Leekha [Mon, 25 Mar 2013 07:40:24 +0000 (07:40 +0000)]
powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/p5040: fix mdio mux for 10G port
Shaohui Xie [Mon, 25 Mar 2013 07:40:21 +0000 (07:40 +0000)]
powerpc/p5040: fix mdio mux for 10G port

Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux.
So we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h
Poonam Aggrwal [Mon, 25 Mar 2013 07:40:20 +0000 (07:40 +0000)]
powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h

B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agosf: spansion: Add support for S25FL128S
Xie Xiaobo [Mon, 25 Mar 2013 07:40:19 +0000 (07:40 +0000)]
sf: spansion: Add support for S25FL128S

SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/p2041: fix serdes reference clock frequency display for PC board
Shaohui Xie [Mon, 25 Mar 2013 07:40:18 +0000 (07:40 +0000)]
powerpc/p2041: fix serdes reference clock frequency display for PC board

PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/b4860: fix for Serdes connectivity to SFP's
Shaveta Leekha [Mon, 25 Mar 2013 07:40:17 +0000 (07:40 +0000)]
powerpc/b4860: fix for Serdes connectivity to SFP's

Crossbar switches were wrongly programmed to
route the CPRI lanes to SFP as the connectivity table
was not correct.
Modified it correctly for SFPs connections.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: fix PHY reset timeout issue
Shengzhou Liu [Mon, 25 Mar 2013 07:40:15 +0000 (07:40 +0000)]
powerpc/t4240qds: fix PHY reset timeout issue

QSGMII card has different PHY address against previous SGMII card.
We check the type of card in slots and set correct PHY address to
avoid complainning "PHY reset timed out" during u-boot booting up.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4qds: Add SW7[4] in the DIP switch display
York Sun [Mon, 25 Mar 2013 07:40:14 +0000 (07:40 +0000)]
powerpc/t4qds: Add SW7[4] in the DIP switch display

SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoEnable XAUI interface for B4860QDS
Suresh Gupta [Mon, 25 Mar 2013 07:40:13 +0000 (07:40 +0000)]
Enable XAUI interface for B4860QDS

- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Stephen George [Mon, 25 Mar 2013 07:40:12 +0000 (07:40 +0000)]
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M

Debug trace buffers are memory mapped in DCSR space beyond 4M.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/p5040: enable PBL tool support
Shaohui Xie [Mon, 25 Mar 2013 07:40:11 +0000 (07:40 +0000)]
powerpc/p5040: enable PBL tool support

Provided a default RCW for P5040, then it can use PBL to build
ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4qds: use clock measurement for sysclk and ddr clock
Ed Swarthout [Mon, 25 Mar 2013 07:40:10 +0000 (07:40 +0000)]
powerpc/t4qds: use clock measurement for sysclk and ddr clock

Use QIXIS measurement registers to obtain sysclk and ddr clock. This
allows using non-standard clock speeds, set by directly writing to
clock chip or store the values in qixis clock data eeprom.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/qixis: add clock measurement registers
Ed Swarthout [Mon, 25 Mar 2013 07:40:09 +0000 (07:40 +0000)]
powerpc/qixis: add clock measurement registers

QIXIS includes frequency measurement functions for each major processor
clock input. After reset (and after clocks are stable), QIXIS measures
the clocks against a reference frequency and stores the results in
CLK_FREQ registers. A base register supplies a multiplier which allows
directly obtaining the measured value, without requiring knowledge of
the target system or QIXIS core frequency.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc8xxx: Allow DDR overclock
York Sun [Mon, 25 Mar 2013 07:40:08 +0000 (07:40 +0000)]
powerpc/mpc8xxx: Allow DDR overclock

Allow DDR clock runs faster than SPD specifes. This may cause memory
failure, but the user should know what is going to happen when using
higher than expected DDR clock.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/chassis2: Change core numbering scheme
York Sun [Mon, 25 Mar 2013 07:40:07 +0000 (07:40 +0000)]
powerpc/chassis2: Change core numbering scheme

To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.

Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.

Cluster clock registers are reorganized to be easily indexed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc8xxx: Add T1040 and variant SoCs
York Sun [Mon, 25 Mar 2013 07:40:06 +0000 (07:40 +0000)]
powerpc/mpc8xxx: Add T1040 and variant SoCs

T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h
York Sun [Mon, 25 Mar 2013 07:40:05 +0000 (07:40 +0000)]
powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h

T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/p5040: enable NAND, SD, SPI boot support
Shaohui Xie [Mon, 25 Mar 2013 07:40:04 +0000 (07:40 +0000)]
powerpc/p5040: enable NAND, SD, SPI boot support

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoAdd e6500 L2 replacement policy selection
James Yang [Mon, 25 Mar 2013 07:40:03 +0000 (07:40 +0000)]
Add e6500 L2 replacement policy selection

This is compile-time config.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4240/ramboot: enable PBL tool for T4240
Shaohui Xie [Mon, 25 Mar 2013 07:40:02 +0000 (07:40 +0000)]
T4240/ramboot: enable PBL tool for T4240

Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use
PBL tool to produce the ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Add VDD override
York Sun [Mon, 25 Mar 2013 07:40:01 +0000 (07:40 +0000)]
powerpc/t4240qds: Add VDD override

Allow VDD voltage overriding with a command. This is an add-on feasture of
VID. To override VDD, use command vdd_override with the value of voltage
in mV, for example

vdd_override <voltage in mV, eg. 1050>

The above example will set the VDD to 1.050 volt. Any wrong value out of
range of 0.8188 to 1.2125 volt or invalid string is ignored.

In addition to the command, if overriding VDD is needed earlier in booting
process, save an variable and reboot:

setenv t4240qds_vdd_mv <voltage in mV>
saveenv

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: check if core is disabled for showing status
York Sun [Mon, 25 Mar 2013 07:40:00 +0000 (07:40 +0000)]
powerpc/mpc85xx: check if core is disabled for showing status

"cpu <num> status" should check if core is disabled before printing
the spin table location.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agonet/phy: fix select line for TN80xx
Shaohui Xie [Mon, 25 Mar 2013 07:39:59 +0000 (07:39 +0000)]
net/phy: fix select line for TN80xx

TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoEnable L2 cache parity/ECC error checking
James Yang [Mon, 25 Mar 2013 07:39:58 +0000 (07:39 +0000)]
Enable L2 cache parity/ECC error checking

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Add board detail for bdinfo command
York Sun [Mon, 25 Mar 2013 07:39:24 +0000 (07:39 +0000)]
powerpc/t4240qds: Add board detail for bdinfo command

Print more detail information including core voltage, RCW source, switch
settings, etc. with bdinfo command.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agocommon: Update cmd_bdinfo for PPC
York Sun [Tue, 14 May 2013 08:06:39 +0000 (08:06 +0000)]
common: Update cmd_bdinfo for PPC

Add board detail function to print more individual board information.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agocmd_mem: fix cp command
Masahiro Yamada [Mon, 20 May 2013 21:08:08 +0000 (21:08 +0000)]
cmd_mem: fix cp command

The "cp" command has not worked since
commit 0628ab8ec59834f98ede267edd21ddb8ba0bb57b,
because of the following lines, which set the destination
and the source to the same address.

buf = map_sysmem(addr, bytes);
src = map_sysmem(addr, bytes);

Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
11 years agoext4: assign get_fs()->dev_desc before using it
Stephen Warren [Thu, 23 May 2013 10:22:10 +0000 (10:22 +0000)]
ext4: assign get_fs()->dev_desc before using it

Commit 50ce4c0 "fs/ext4: Support device block sizes != 512 bytes"
modified ext4fs_set_blk_dev() to calculate total_sect based on
get_fs()->dev_desc->log2blksz rather than SECTOR_SIZE. However, this
value wasn't yet assigned. Move the assignment earlier so the code
doesn't crash or hang.

Cc: Egbert Eich <eich@suse.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
11 years agoarm: Enable -ffunction-sections / -fdata-sections / --gc-sections
Tom Rini [Thu, 25 Apr 2013 07:40:22 +0000 (07:40 +0000)]
arm: Enable -ffunction-sections / -fdata-sections / --gc-sections

While other architectures have enabled these gcc / ld options for some
time on U-Boot itself, ARM has only been doing this on SPL.  Enable this
on full U-Boot as well now.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
11 years agoARM: Add Seagate GoFlex Home support
Suriyan Ramasami [Thu, 11 Apr 2013 07:17:25 +0000 (07:17 +0000)]
ARM: Add Seagate GoFlex Home support

Add Seagate GoFlex Home support

Start with dockstar configuration
define support for RTC, DATE, SATA and EXT4FS

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
11 years agoARM: vexpress: enable bootz and hush parser for all VExpress boards
Andre Przywara [Tue, 9 Apr 2013 02:20:33 +0000 (02:20 +0000)]
ARM: vexpress: enable bootz and hush parser for all VExpress boards

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
11 years agoARM: vexpress: add support for Versatile Express Cortex-A15-TC2
Andre Przywara [Tue, 9 Apr 2013 02:20:32 +0000 (02:20 +0000)]
ARM: vexpress: add support for Versatile Express Cortex-A15-TC2

This adds support for the Cortex-A15-TC2 core tile for the Versatile
Express board by ARM. This is mostly a copy of the A5 support file,
but will be extended later with A15 specific options.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
11 years agoARM: vexpress: create A5 specific board config
Ryan Harkin [Tue, 9 Apr 2013 02:20:31 +0000 (02:20 +0000)]
ARM: vexpress: create A5 specific board config

This patch creates a new config for the A5 dual core tile that includes the
generic config for the Versatile Express platform.

The generic config has been modified to provide support for the Extended
Memory Map, as used on the A5 core tile.  A5 does not support the legacy
memory map.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
11 years agoARM: vexpress: refactoring of Versatile Express CA9x4 support
Ryan Harkin [Tue, 9 Apr 2013 02:20:30 +0000 (02:20 +0000)]
ARM: vexpress: refactoring of Versatile Express CA9x4 support

The current ca9x4_ct_vxp platform contains support for a Versatile
Express motherboard with a quad core A9 core tile.

This patch separates the Versatile Express motherboard code and the
A9 specific code, to ease supporting more core tiles in the next
patches.

Andre: merged the first two of Ryan's original patches and did some
checkpatch fixes.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
11 years agocfi_flash: return NULL for invalid base address input
Masahiro Yamada [Fri, 17 May 2013 05:50:37 +0000 (14:50 +0900)]
cfi_flash: return NULL for invalid base address input

When base address given was out of valid flash address ranges,
flash_get_info() function returned the pointer to the last
element of flash_info[i] array.

This patch changes this function to return NULL pointer
in such a case, which is more correct behaviour.

The function flash_protect_default() calls flash_protect()
immediately after flash_get_info() invocation.
With this correction, flash_protect() function would be
able to return soon, for NULL flash_info.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
11 years agocosmetic: cfi_flash: delete a space after an unary operator
Masahiro Yamada [Fri, 17 May 2013 05:50:36 +0000 (14:50 +0900)]
cosmetic: cfi_flash: delete a space after an unary operator

Linux Kernel Documentation/CodingStyle says:
 Do not add a space after unary operators such as &, *, ...

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
11 years agocfi_flash: Fix unaligned accesses to cfi_qry structure
Andrew Gabbasov [Tue, 14 May 2013 17:27:52 +0000 (12:27 -0500)]
cfi_flash: Fix unaligned accesses to cfi_qry structure

Packed structure cfi_qry contains unaligned 16- and 32-bits members,
accessing which causes problems when cfi_flash driver is compiled with
-munaligned-access option: flash initialization hangs, probably
due to data error.

Since the structure is supposed to replicate the actual data layout
in CFI Flash chips, the alignment issue can't be fixed in the structure.
So, unaligned fields need using of explicit unaligned access macros.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Stefan Roese <sr@denx.de>
11 years agoARM: at91: add NAND partition table and index
Bo Shen [Sun, 12 May 2013 23:28:40 +0000 (23:28 +0000)]
ARM: at91: add NAND partition table and index

Add NAND partition table, EK board support boot up NAND flash using
the same NAND partition table

Add Index in this file

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoARM: at91: add at91sam9x5 and sama5d3x information
Bo Shen [Sun, 12 May 2013 23:28:39 +0000 (23:28 +0000)]
ARM: at91: add at91sam9x5 and sama5d3x information

This patch add following EK information
  - at91sam9n12ek, at91sam9x5ek
  - sama5d3xek

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoARM: at91: fix and update README.at91 document
Bo Shen [Sun, 12 May 2013 23:28:38 +0000 (23:28 +0000)]
ARM: at91: fix and update README.at91 document

This patch implement following things
  - The link no longer accessable
  - Remove the error configuration command
  - Update soldered data flash memory map
  - Update at91sam9m10g45ek memory size to 128MiB

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoARM: atmel: add sama5d3xek support
Bo Shen [Sun, 12 May 2013 22:40:54 +0000 (22:40 +0000)]
ARM: atmel: add sama5d3xek support

Add sama5d3xek support with following feature
  - boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector
  - boot from SPI flash support
  - boot from SD card support
  - LCD support
  - EMAC support
  - USB OHCI support

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoUSB: ohci-at91: support sama5d3x devices
Bo Shen [Sun, 12 May 2013 22:40:53 +0000 (22:40 +0000)]
USB: ohci-at91: support sama5d3x devices

Add OHCI support for sama5d3x devices

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoARM: at91: add Atmel sama5d3 SoC new pmc register
Bo Shen [Sun, 12 May 2013 22:40:52 +0000 (22:40 +0000)]
ARM: at91: add Atmel sama5d3 SoC new pmc register

Add Atmel sama5d3 SoC new pmc register

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoUpdate MAINTAINERS file for sandbox
Simon Glass [Wed, 15 May 2013 06:54:41 +0000 (06:54 +0000)]
Update MAINTAINERS file for sandbox

This currently has no maintainer listed.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agoUpdate MAINTAINERS file for x86
Simon Glass [Wed, 15 May 2013 06:54:40 +0000 (06:54 +0000)]
Update MAINTAINERS file for x86

This still shows the previous maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years ago.gitignore: add GNU GLOBAL files
Masahiro Yamada [Sun, 12 May 2013 18:14:05 +0000 (18:14 +0000)]
.gitignore: add GNU GLOBAL files

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
11 years agofdt_support: Use CONFIG_NR_DRAM_BANKS if defined
Doug Anderson [Tue, 30 Apr 2013 10:22:00 +0000 (10:22 +0000)]
fdt_support: Use CONFIG_NR_DRAM_BANKS if defined

It appears that there are some cases where we have more than 4 banks
of memory.  Use CONFIG_NR_DRAM_BANKS if it's defined to handle this.
This will take up a little extra stack space (64 bytes extra if we go
up to 8 banks), but that seems OK.

Signed-off-by: Doug Anderson <dianders@chromium.org>
11 years agobootm: Avoid 256-byte overflow in fixup_silent_linux()
Doug Anderson [Tue, 17 Jan 2012 09:37:41 +0000 (09:37 +0000)]
bootm: Avoid 256-byte overflow in fixup_silent_linux()

This makes fixup_silent_linux() use malloc() to allocate its
working space, meaning that our maximum kernel command line
should only be limited by malloc().  Previously it was silently
overflowing the stack.

Note that nothing about this change increases the kernel's maximum
command line length.  If you have a command line that is >256
bytes it's up to you to make sure that kernel can handle it.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
11 years agoREADME: Correct reference for CONFIG_SUPPORT_RAW_INITRD
Tom Rini [Thu, 16 May 2013 15:40:11 +0000 (11:40 -0400)]
README: Correct reference for CONFIG_SUPPORT_RAW_INITRD

Signed-off-by: Tom Rini <trini@ti.com>
11 years agopowerpc/esdhc: Correct judgement for DATA PIO mode
Haijun.Zhang [Tue, 7 May 2013 15:50:58 +0000 (15:50 +0000)]
powerpc/esdhc: Correct judgement for DATA PIO mode

The logic for the whether to configure for polling or DMA
was mistakenly reversed in this patch:

Commit 7b43db92110ec2f15c5f7187a165f2928464966b
drivers/mmc/fsl_esdhc.c: fix compiler warnings

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Sun Yusong-R58495 <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agommc: update Faraday FTSDC010 for rw performance
Kuo-Jung Su [Mon, 6 May 2013 20:32:51 +0000 (20:32 +0000)]
mmc: update Faraday FTSDC010 for rw performance

Faraday FTSDC010 is a MMC/SD host controller.
Although there is already a driver in current u-boot release,
which is modified from eSHDC and contributed by Andes Tech.
Its performance is too terrible on Faraday A36x SoC platforms,
so I turn to implement this new version of driver which is
10+ times faster than the old one.

It's carefully designed to be compatible with Andes chips,
so it should be safe to replace it.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Tom Rini [Tue, 14 May 2013 22:47:43 +0000 (18:47 -0400)]
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

11 years agoPower: remove support for Freescale MPC8220
Wolfgang Denk [Sat, 11 May 2013 03:00:50 +0000 (03:00 +0000)]
Power: remove support for Freescale MPC8220

The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.

Remove the code to avoid wasting maitaining efforts on dead stuff.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
11 years agodoc/README.scrapyard: add missing commit IDs
Wolfgang Denk [Sat, 11 May 2013 03:00:49 +0000 (03:00 +0000)]
doc/README.scrapyard: add missing commit IDs

Signed-off-by: Wolfgang Denk <wd@denx.de>
11 years agodrivers/mmc: move spl_mmc.c to common/spl
Ying Zhang [Thu, 9 May 2013 23:00:36 +0000 (23:00 +0000)]
drivers/mmc: move spl_mmc.c to common/spl

The mpc85xx repuires a special layout on the memory device that is
connected to the eSDHC controller interface. But the file spl_mmc.c
didn't handle this specfic case, there needs a special treatmen, in
the powerpc drictory. So, there is no longer to keep spl_mmc.c on
mpc85xx, CONFIG_SPL_FRAMEWORK is not set.

When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not
set, there was an error in drivers/mmc/spl_mmc.c:

drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'.

Now, the solution is to move the file "spl_mmc.c" to directory "common/spl".

Signed-off-by: Ying Zhang <b40530@freescale.com>
11 years agosmc911x: fix the timeout detection
Masahiro Yamada [Wed, 8 May 2013 21:42:44 +0000 (21:42 +0000)]
smc911x: fix the timeout detection

If timeout is occurred at the while loop above,
the value of 'timeout' is -1, not 0.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
11 years agodoc/README.ubi: Add description of accessing ubi filesystems
Paul B. Henson [Wed, 8 May 2013 17:08:10 +0000 (17:08 +0000)]
doc/README.ubi: Add description of accessing ubi filesystems

Signed-off-by: "Paul B. Henson" <henson@acm.org>
11 years agoT4240/eth: fix SGMII card PHY address
Shaohui Xie [Mon, 25 Mar 2013 07:39:38 +0000 (07:39 +0000)]
T4240/eth: fix SGMII card PHY address

QSGMII card assumed to be used by default, but if SGMII card is used,
it will use different PHY address, but we don't know which card is used
until we access PHY on the card. So we check the card type slot by slot,
if we can read a PHY ID by reading a SGMII PHY address on a slot, then
the slot must have a SGMII card pluged, we mark all ports on that slot,
and fix dts to use the SGMII card PHY address when doing dts fixup
for the marked ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4qds: Fix disabling remote I2C connection
Ed Swarthout [Mon, 25 Mar 2013 07:39:37 +0000 (07:39 +0000)]
powerpc/t4qds: Fix disabling remote I2C connection

Only clear IRE bit in qixis brdcfg5 register and keep other bits
unchanged.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/b4860qds: Assign DDR address in board file
York Sun [Mon, 25 Mar 2013 07:39:36 +0000 (07:39 +0000)]
powerpc/b4860qds: Assign DDR address in board file

B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
This is the requirement for DSP cores to run in 32-bit address space.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc8xxx: Allow board file to override DDR address assignment
York Sun [Mon, 25 Mar 2013 07:39:35 +0000 (07:39 +0000)]
powerpc/mpc8xxx: Allow board file to override DDR address assignment

This gives boards flexibility to assign other than default addresses to each
DDR controller. For example, DDR controler 2 can have 0 as the base and DDR
controller 1 has higher memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Update workaround for DDR erratum A-004934
York Sun [Mon, 25 Mar 2013 07:39:34 +0000 (07:39 +0000)]
powerpc/mpc85xx: Update workaround for DDR erratum A-004934

The workaround has been updated to use a slightly different magic number.
Change from 0x00003000 to 0x30003000.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c
Roy Zang [Mon, 25 Mar 2013 07:39:33 +0000 (07:39 +0000)]
T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c

This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without  “usb start” command.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4240/net: use QSGMII card PHY address by default
Shaohui Xie [Mon, 25 Mar 2013 07:39:32 +0000 (07:39 +0000)]
T4240/net: use QSGMII card PHY address by default

Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agonet/phy: add VSC8574 support
Shaohui Xie [Mon, 25 Mar 2013 07:39:31 +0000 (07:39 +0000)]
net/phy: add VSC8574 support

The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/85xx: fix build error introduced by serdes_get_prtcl
Shengzhou Liu [Mon, 25 Mar 2013 07:39:30 +0000 (07:39 +0000)]
powerpc/85xx: fix build error introduced by serdes_get_prtcl

Removed unused declare serdes_get_prtcl() which was no longer needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agonet/fm: fixup ethernet for mEMAC
Shengzhou Liu [Mon, 25 Mar 2013 07:39:29 +0000 (07:39 +0000)]
net/fm: fixup ethernet for mEMAC

- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
  MAC node disabled incorrectly.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agot4240qds/eth: fixup ethernet for t4240qds
Shengzhou Liu [Mon, 25 Mar 2013 07:39:28 +0000 (07:39 +0000)]
t4240qds/eth: fixup ethernet for t4240qds

1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
   slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/85xx: add missing QMAN frequency calculation
Shaohui Xie [Mon, 25 Mar 2013 07:33:25 +0000 (07:33 +0000)]
powerpc/85xx: add missing QMAN frequency calculation

When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc: Add T4160QDS
York Sun [Mon, 25 Mar 2013 07:33:31 +0000 (07:33 +0000)]
powerpc: Add T4160QDS

T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDes protocols.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Move SoC define into boards.cfg
York Sun [Mon, 25 Mar 2013 07:33:30 +0000 (07:33 +0000)]
powerpc/t4240qds: Move SoC define into boards.cfg

Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC
variants supported on the same board.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Add T4160 SoC
York Sun [Mon, 25 Mar 2013 07:33:29 +0000 (07:33 +0000)]
powerpc/mpc85xx: Add T4160 SoC

T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240: Fix SerDes protocol arrays with const prefix
York Sun [Mon, 25 Mar 2013 07:33:28 +0000 (07:33 +0000)]
powerpc/t4240: Fix SerDes protocol arrays with const prefix

Protocols are constants. Fix arrays with const prefix.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Fix PIR parsing for chassis2
York Sun [Mon, 25 Mar 2013 07:33:27 +0000 (07:33 +0000)]
powerpc/mpc85xx: Fix PIR parsing for chassis2

The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/corenet2: Print SerDes protocol in decimal
York Sun [Mon, 25 Mar 2013 07:33:26 +0000 (07:33 +0000)]
powerpc/corenet2: Print SerDes protocol in decimal

Use decimal and hexadecimal for protocol numbers. It helps to match with
SoC user manual.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4/USB: Add USB 2.0 UTMI dual phy support
Roy Zang [Mon, 25 Mar 2013 07:33:23 +0000 (07:33 +0000)]
T4/USB: Add USB 2.0 UTMI dual phy support

T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Add voltage ID support
York Sun [Mon, 25 Mar 2013 07:33:22 +0000 (07:33 +0000)]
powerpc/t4240qds: Add voltage ID support

T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: Fix portal setup
York Sun [Mon, 25 Mar 2013 07:33:21 +0000 (07:33 +0000)]
powerpc/mpc85xx: Fix portal setup

Missing nodes of crypto, pme, etc in device tree is not a fatal error.
Setting up the qman portal should skip the missing node and continue
to finish the rest.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc8xxx: Fix DDR 3-way interleaving
York Sun [Mon, 25 Mar 2013 07:33:20 +0000 (07:33 +0000)]
powerpc/mpc8xxx: Fix DDR 3-way interleaving

Should check if interleaving is enabled before using interleaving mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Update DDR timing table
York Sun [Mon, 25 Mar 2013 07:33:19 +0000 (07:33 +0000)]
powerpc/t4240qds: Update DDR timing table

Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4/SerDes: correct the SATA index
Roy Zang [Mon, 25 Mar 2013 07:33:18 +0000 (07:33 +0000)]
T4/SerDes: correct the SATA index

Lane H on SerDes4 should be SATA2 instead of SATA1

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoFman/t4240: some fix for 10G XAUI
Shaohui Xie [Mon, 25 Mar 2013 07:33:17 +0000 (07:33 +0000)]
Fman/t4240: some fix for 10G XAUI

1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: fix XAUI card PHY address
Shaohui Xie [Mon, 25 Mar 2013 07:33:16 +0000 (07:33 +0000)]
powerpc/t4240qds: fix XAUI card PHY address

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4/serdes: fix the serdes clock frequency
Roy Zang [Mon, 25 Mar 2013 07:33:15 +0000 (07:33 +0000)]
T4/serdes: fix the serdes clock frequency

Reverse the bit sequence to set and display serdes clock frequency
correctly. The correct bit maps in BRDCFG2 are
0 1 2 3 4 5 6 7
S1RATE[1:0] S2RATE[1:0]  S3RATE[1:0]  S4RATE[1:0]

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>