Peng Fan [Mon, 15 Sep 2014 06:59:17 +0000 (14:59 +0800)]
imx:mx6qarm2: change CONFIG_SYS_FSL_ESDHC_ADDR
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR.
USDHC3 and USDHC4 are both initialized in board_mmc_init. There is
no restriction on USDHC3 addr or USDHC4 addr should be assigned to
CONFIG_SYS_FSL_ESDHC_ADDR. So, just choose USDHC4_BASE_ADDR to avoid
errors when fsl_esdhc_mmc_init is invoked.
Stefan Agner [Fri, 12 Sep 2014 11:06:36 +0000 (13:06 +0200)]
arm: vf610: add NAND support for vf610twr
This adds NAND support for the Vybrid tower system (TWR-VF65GS10)
provided by the vf610_nfc driver. Full 16-Bit bus width is
supported. Also an aditional config vf610twr_nand is introduced
which gets the environment from NAND. However, booting U-Boot from
NAND is not yet possible due to missing boot configuration block
(BCB).
Stefan Agner [Fri, 12 Sep 2014 11:06:35 +0000 (13:06 +0200)]
mtd: nand: add Freescale vf610_nfc driver
This adds initial support for Freescale NFC (NAND Flash Controller)
found in ARM Vybrid SoC's, Power Architecture MPC5125 and others.
The driver is called vf610_nfc since this is the first supported
and tested hardware platform supported by the driver.
Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Andrew Ruder [Tue, 12 Aug 2014 14:26:01 +0000 (09:26 -0500)]
arm: mx35: use common timer functions
This patch moves mx35 to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) mx35 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor. Rather than patch the specific mx35 issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Andrew Ruder [Tue, 12 Aug 2014 14:26:00 +0000 (09:26 -0500)]
arm: mx31: use common timer functions
This patch moves mx31 to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) mx31 timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locks the processor. Rather than patch the specific mx31 issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Helmut Raiger <helmut.raiger@hale.at>
The boards using CONFIG_SYS_DV_NOR_BOOT_CFG (i.e. calimain,
da850evm_direct_nor and enbw_cmc) had the _start symbol defined after
the CONFIG_SYS_DV_NOR_BOOT_CFG word rather than before it in
arch/arm/lib/vectors.S. Because of that, if by lack of luck
'gd->mon_len = (ulong)&__bss_end - (ulong)_start' (see setup_mon_len())
was a multiple of 4 kiB (see reserve_uboot()), then the last BSS word
overlapped the first word of the following reserved RAM area (or went
beyond the top of RAM without such an area) after relocation because
__image_copy_start did not match _start (see relocate_code()).
This was broken by commit 41623c9 'arm: move exception handling out of
start.S files', which defined _start twice (before and after the
CONFIG_SYS_DV_NOR_BOOT_CFG word), then by commit 0a26e1d 'arm: fix a
double-definition error of _start symbol', which kept the definition of
the _start symbol after the CONFIG_SYS_DV_NOR_BOOT_CFG word. This new
commit fixes this issue by restoring the original behavior, i.e. by
defining the _start symbol before the CONFIG_SYS_DV_NOR_BOOT_CFG word.
Some boards, like mx31pdk and tx25, require the beginning of the SPL
code to be position-independent. For these two boards, this is because
they use the i.MX external NAND boot, which starts by executing the
first NAND Flash page from the NFC page buffer. The SPL then needs to
copy itself to its actual link address in order to free the NFC page
buffer and use it to load the non-SPL image from Flash before running
it. This means that the SPL runtime address differs from its link
address between the reset and the initial copy performed by
board_init_f(), so this part of the SPL binary must be
position-independent.
This requirement was broken by commit 41623c9 'arm: move exception
handling out of start.S files', which used an absolute address to branch
to the reset routine. This new commit restores the original behavior,
which just performed a relative branch. This fixes the boot of mx31pdk
and tx25.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> Reported-by: Helmut Raiger <helmut.raiger@hale.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Magnus Lilja <lilja.magnus@gmail.com> Cc: John Rigby <jcrigby@gmail.com> Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
Commit 224beb833e544b802f08765271cec07667d39669 add clock
enabling function for FEC, but the masks are not available
for SX processor and the mx6sxsabresd cannot be built clean.
Commit fa9c021632473 ("mx6: add example DTB for mx6qsabreauto") introduced
'imx6q-sabreauto.dts' but it adds no real value as the dts file only contains
the 'model' and 'compatible' strings.
After this commit the final binary is also changed from 'u-boot.imx' to
'u-boot-dtb.imx', which may confuse users.
So revert it until a more complete and useful device tree could be provided.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Guillaume GARDET [Tue, 26 Aug 2014 10:05:31 +0000 (12:05 +0200)]
imx: nitrogen6x: Replace 'fatload' by 'load' command in env settings to be filesystem independent
nitrogen6x.h file defines CONFIG_CMD_FS_GENERIC, so we are able to use generic
'load' command instead of 'fatload'. It allows to use ext filesystem and keep
compatibilty with fat filesystem.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Stefano Babic <sbabic@denx.de> Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
Stefan Agner [Tue, 19 Aug 2014 15:54:28 +0000 (17:54 +0200)]
arm: vf610: lpuart: disable FIFO on initializaton
UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.
This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.
Stefan Agner [Tue, 19 Aug 2014 15:54:27 +0000 (17:54 +0200)]
arm: vf610: lpuart: fix status register handling
The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.
Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.
Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.
Ye.Li [Wed, 20 Aug 2014 08:55:32 +0000 (16:55 +0800)]
imximage: Fix imximage IVT bug for EIM-NOR boot
The load region size of EIM-NOR are defined to 0. For this case,
the parameter "imximage_init_loadsize" must be calculated.
The imximage tool implements the calculation in the "imximage_generate"
function, but the following function "imximage_set_header" resets the value
and not calculate. This bug cause some fields of IVT head are not
correct, for example the boot_data and DCD overlay the application area.
Ye.Li [Wed, 20 Aug 2014 09:18:24 +0000 (17:18 +0800)]
iMX6: Disable the L2 before chaning the PL310 latency
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.
Thierry Reding [Fri, 22 Aug 2014 07:46:35 +0000 (09:46 +0200)]
imx: ventana: Avoid undefined behaviour
The leds array within struct ventana has space for 3 elements, but the
setup_board_gpio() function tries to set up 4 GPIOs for LEDs. Recent
versions of GCC complain about that:
board/gateworks/gw_ventana/gw_ventana.c: In function 'setup_board_gpio':
board/gateworks/gw_ventana/gw_ventana.c:987:27: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations]
if (gpio_cfg[board].leds[i])
^
board/gateworks/gw_ventana/gw_ventana.c:986:2: note: containing loop
for (i = 0; i < 4; i++) {
^
Fix this by making the upper bound of the loop match the array size.
Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
tools: imximage: Fix the maximum DCD size for mx53/mx6
According to mx53 and mx6 reference manuals:
"The maximum size of the DCD limited to 1768 bytes."
As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and
excluding the first entry, which is the header leads to 220 as the maximum
number for DCD size.
Tim Harvey [Fri, 8 Aug 2014 05:49:57 +0000 (22:49 -0700)]
imx: ventana: add pci fixup for PLX PEX860x switch GPIO
Most Gateworks Ventana boards use a PLX PEX860x PCIe switch for PCIe expansion.
These boards use GPIO on the PLX device as PERST# for the downstream ports
thus we assert this when the PLX is enumerated.
Nikita Kiryanov [Wed, 20 Aug 2014 12:08:58 +0000 (15:08 +0300)]
arm: mx6: ddr: fix cs0_end calculation
Current way of calculation CS0_END field for MMDCx_MDASP register
is problematic because in most cases the user is forced to define
cs_density in an unnatural way: as value - 2, instead of value.
This breaks the abstraction provided by struct mx6_ddr_sysinfo
because the user is forced to be aware of the way the calculation
is performed.
Nikita Kiryanov [Wed, 20 Aug 2014 12:08:57 +0000 (15:08 +0300)]
arm: mx6: ddr: configure MMDC for slow_pd
According to MX6 TRM, both MMDC and DRAM should be configured to
the same powerdown precharge. Currently, mx6_dram_cfg()
configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for
'slow exit (DLL off)' (MR0[12] = 0).
Configure MMDC for slow pd.
Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Tim Harvey <tharvey@gateworks.com>
Nikita Kiryanov [Wed, 20 Aug 2014 12:08:54 +0000 (15:08 +0300)]
i2c: imx: add macros to setup pads for multiple SoC types
Add macro which defines i2c_pads_info structs for multiple SoC types,
and a macro which selects the appropriate struct based on CPU type,
thus eliminating the need to manage multiple i2c pad configurations
manually when supporting multiple SoC types.
Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Nikita Kiryanov [Wed, 20 Aug 2014 12:08:52 +0000 (15:08 +0300)]
compulab: eeprom: add support for defining eeprom i2c bus
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM
module what I2C bus the EEPROM is located at. Make cl_eeprom_read()
switch to that bus when reading EEPROM.
Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Dmitry Lifshitz <lifshitz@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Tim Harvey [Fri, 8 Aug 2014 05:35:42 +0000 (22:35 -0700)]
imx: ventana: added cputype env var
There are many similarities between the IMX6QUAD/IMX6DUAL and there are
many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env
variable that tells you which type you have.
Tim Harvey [Thu, 21 Aug 2014 06:35:14 +0000 (23:35 -0700)]
imx: ventana: add GW5520 support
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as:
* 2x MiniPCIe sockets
* 2x USB host sockets
* 2x i210 GigE
* HDMI out
* digital I/O expansion
Tim Harvey [Thu, 21 Aug 2014 06:31:11 +0000 (23:31 -0700)]
imx: ventana: base SPL MMDC calibration on width and size not board
The IMX6 MMDC calibration registers depend on propagation delay and capacitive
loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the
board layout varies little in trace-lengths such that propagation delays are
irrelevant thus we can simply things by using calibration values obtained
from various board layouts based on a common SoC and DDR chip configuration.
This eliminates board-model from being needed allowing more flexibility. These
values were tested on a large sample size of Gateworks Ventana boards ranging
in layout, and memory configuration over the entire temperature range supported.
Fabio Estevam [Mon, 25 Aug 2014 16:34:17 +0000 (13:34 -0300)]
net: fec_mxc: Poll FEC_TBD_READY after polling TDAR
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.
As explained by Ye Li:
"The TDAR bit is cleared when the descriptors are all out from TX ring, but on
mx6solox we noticed that the READY bit is still not cleared right after TDAR.
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared.
In mx6solox, we use a later version of FEC IP. It looks like that this
intrinsic behaviour of TDAR bit has changed in this newer FEC version."
Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.
No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
KBuild abuses the asm statement to write to a file and
clang chokes about these invalid asm statements. Hack it
even more by fooling this is actual valid asm code.
"clang does not support global register variables; this is
unlikely to be implemented soon because it requires additional
LLVM backend support" [1]
Workaround it by obtaining the value of gd/r9 by an inline
asm routine. Note there is no set routine added for ARM at the
moment, since most if not all updates of gd from c are actually
not needed for ARM.
[1] http://clang.llvm.org/docs/UsersManual.html
cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
cc-option: also detect unsupported warnings options
By default clang will echo a warning if a warning option is
unknown. Turning warnings into errors when polling for options
also catches such cases and prevents passing arguments to the
compiler which cause warnings.
For ARM / ARM64 the relocation routines already updated
gd to the new value. Don't set it again. This allows
compilation with clang as it cannot update gd directly.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
exynos video driver.
Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Previously, we used to statically assign values for vl_col, vl_row and
vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
Introducing the function exynos_lcd_early_init() would take care of this
assignment on the fly by parsing FIMD DT properties, thereby allowing us
to remove LCD_XRES and LCD_YRES from the main config file.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Patch is the result of:
sed -i -e 's/FTDFILE/FDTFILE/g' board/sunxi/Kconfig configs/* include/configs/sunxi-common.h
sed -i -e 's/ftdfile/fdtfile/g' board/sunxi/Kconfig
Reported-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com>
[ ijc -- s/Spotted-by/Reported-by/ and resolve conflict vs "remove
redundant "SPL" from CONFIG_SYS_EXTRA_OPTIONS" ]
odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412
This board file supports standard features of Odroid X2 and U3 boards:
- Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
- MAX77686 power regulator,
- USB PHY,
- enable XCL205 - power for board peripherials
- check board type: U3 or X2.
- enable Odroid U3 FAN cooler
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arm:reset: call the reset_misc() before the cpu reset
On an Odroid U3 board, the SOC is unable to reset the eMMC card
in the DWMMC mode by the cpu software reset. Manual reset of the card
by switching proper gpio pin - fixes this issue.
Such solution needs to add a call to pre reset function.
This is done by the reset_misc() function, which is called before reset_cpu().
The function reset_misc() is a weak function.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com>
Changes v4:
- arch/arm/reset: fix weak function attribute to proper style Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
samsung: misc: add function for setting $dfu_alt_info
This change introduces new common function:
- set_dfu_alt_info() - put dfu system and bootloader setting
into $dfu_alt_info.
functions declaration:
- char *get_dfu_alt_system(void)
- char *get_dfu_alt_boot(void)
- void set_dfu_alt_info(void)
and new config:
- CONFIG_SET_DFU_ALT_INFO
This function can be used for auto setting dfu configuration on boot.
Such feature is useful for multi board support by one u-boot binary.
Each board should define two functions:
- get_dfu_alt_system()
- get_dfu_alt_boot()
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
board:samsung: check the boot device and init the right mmc driver.
It is possible to boot device using a micro SD or eMMC slots.
In this situation, boot device should be registered as a block
device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV
is usually set to "0" in the most config cases.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion
S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip
corrected' error messages. Possible cause was discussed in the
mailinglist thread:
http://lists.denx.de/pipermail/u-boot/2014-April/177508.html
Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly
due to a NAND protocol violation in the omap driver since the
Random Data Output command (05h-E0h) expects to see only the
column address that should be addressed within the already loaded
read page into the read buffer. Only 2 address cycles with ALE
active should be provided between the 05h and E0h commands. The
Page read command expects the full address footprint (2bytes for
column address + 3bytes for row address), but once the page is
loaded into the read buffer, Random Data Output should be used
with only 2bytes for column address."
This patch combines the solution proposed in the mailinglist and
the patch provided by the Spansion company (GPLv2 code, source:
http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip)
Since the CS of a device connected to the GPMC was
stored in the global variable, it was not possible to
use multiple devices. In this patch the CS is stored per
device in its 'struct omap_nand_info'. This makes it
possible to use up to 'GPMC_MAX_CS' NAND Flash devices
connected to U-boot.
In case when 4K page keystone RBL layout is used the compilation
error is appeared. That's because the #ifdef has to be placed under
struct name. This patch correct it.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
projects / u-boot / log