We need to wait while drawing engine clears frame
buffer before any further software accesses to frame
buffer will be initiated. Otherwise software drawn
parts could be partially destroyed by the drawing
engine or even GDC chip freeze could occur (as
observed on socrates board).
Michal Simek [Fri, 11 Jul 2008 08:43:13 +0000 (10:43 +0200)]
FIS: repare incorrect return value with ramdisk handling
Microblaze and PowerPC use boot_get_ramdisk for loading
ramdisk to memory with checking return value.
Return 0 means success. Return 1 means failed.
Here is correspond part of code from bootm.c which check
return code.
ret = boot_get_ramdisk (argc, argv, images, IH_ARCH_PPC,
&rd_data_start, &rd_data_end);
if (ret)
goto error;
Stefan Roese [Thu, 10 Jul 2008 11:53:31 +0000 (13:53 +0200)]
ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boards
This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.
Mail to kharris@nexus-tech.net bounces because the user doesn't exist
anymore. You can't be a maintainer without a valid e-mail address, so
move all boards that used to be maintained by Kyle Harris to the
"orphaned" list.
Currently, only PowerPC has a list of orphaned boards, so this patch
creates one for ARM as well.
at91: Fix to enable using Teridian MII phy (78Q21x3) with at91sam9260
On the at91sam9260ep development board there is an EEPROM
connected to the TWI interface (PA23, PA24 Peripheral A
multiplexing), so we cannot use these pins as ETX2, ETX3.
This patch configures PA10, PA11 pins for ETX2, ETX3
instead of PA23, PA24 pins.
Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Manuel Sahm <Manuel.Sahm@feig.de>
The DIU_DIV register is 8 bit not 5 bit. This prevented large DIV values
so it was not possible to set a slow pixel clock and thus prevented
display on small screens.
Signed-off-by: Kenneth Johansson <kenneth@southpole.se> Acked-by: John Rigby <jrigby@freescale.com>
John Rigby [Fri, 11 Jul 2008 20:44:09 +0000 (14:44 -0600)]
ADS5121 cleanup compile warnings
board/ads5121/iopin.c
Replace bit fields in struct iopin_t with a single
field and intialize it via plain old macros.
This fixes the type pun warnings and makes the code
more readable.
board/ads5121/ads5121.c
Add include iopin.h to ads5121.c for the iopin_initialize
prototype.
TsiChung Liew [Thu, 29 May 2008 17:21:54 +0000 (12:21 -0500)]
ColdFire: Fix UART baudrate formula
The formula "counter = (u32) (gd->bus_clk / gd->baudrate) / 32"
can generate the wrong divisor due to integer division truncation.
Round the calculated divisor value by adding 1/2 the baudrate
before dividing by the baudrate.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Stefan Roese [Thu, 10 Jul 2008 09:38:26 +0000 (11:38 +0200)]
ppc4xx: Fix include sequence in 4xx_pcie.c
This patch now moves common.h to the top of the inlcude list. This
is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that
the phys_size_t/phys_addr_t are defined to the correct size in this
driver.
Stefan Roese [Thu, 26 Jun 2008 15:36:39 +0000 (17:36 +0200)]
ppc4xx: Rework 440GX UIC handling
This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.
Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.
Stefan Roese [Thu, 26 Jun 2008 11:40:57 +0000 (13:40 +0200)]
ppc4xx: Consolidate PPC4xx UIC defines
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.
Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.
Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.
Stefan Roese [Wed, 25 Jun 2008 08:59:22 +0000 (10:59 +0200)]
ppc4xx: Consolidate PPC4xx UIC defines
This patch is the first step to consolidate the UIC related defines in the
4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to
asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next
steps.
Stefan Roese [Thu, 10 Jul 2008 11:52:44 +0000 (13:52 +0200)]
ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boards
This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.
Grant Erickson [Tue, 8 Jul 2008 15:35:00 +0000 (08:35 -0700)]
ppc4xx: Add MII mode support to the EMAC RGMII Bridge
This patch adds support for placing the RGMII bridge on the
PPC405EX(r) into MII/GMII mode and allows a board-specific
configuration to specify the bridge mode at compile-time.
Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
Grant Erickson [Wed, 9 Jul 2008 23:46:35 +0000 (16:46 -0700)]
ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM Controller
This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).
With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).
Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:
PPC4xx IBM DDR2 Register Dump:
...
SDRAM_MB0CF[40] = 0x00006701
...
which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.
Tested on:
AMCC Kilauea/Haleakala:
- NFS Linux Boot: PASSED
- NAND Linux Boot: PASSED
Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
Grant Erickson [Wed, 9 Jul 2008 23:31:59 +0000 (16:31 -0700)]
ppc4xx: Add AMCC/IBM DDR2 SDRAM ECC Field Mnemonics
Add additional DDR2 SDRAM memory controller DCR mneomnics, condition
revision ID DCR based on 405EX, and add field mnemonics for bus error
status and ECC error status registers.
Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
Grant Erickson [Wed, 9 Jul 2008 18:55:46 +0000 (11:55 -0700)]
PPC4xx: Correct SDRAM_MCSTAT for PPC405EX(r)
While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM
controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in
the 405EX(r), SDRAM_MCSTAT has a different DCR value.
Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF
which causes SDRAM initialization to periodically fail since it can
prematurely indicate SDRAM ready status.
Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
Feng Kan [Wed, 9 Jul 2008 05:48:42 +0000 (22:48 -0700)]
ppc4xx: Initial framework of the AMCC PPC460SX redwood reference board.
Add AMCC Redwood reference board that uses the latest
PPC 464 CPU processor combined with a rich mix of peripheral
controllers. The board will support PCIe, mutiple Gig ethernet
ports, advanced hardware RAID assistance and IEEE 1588.
Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Sergey Lapin [Thu, 5 Jun 2008 07:06:29 +0000 (11:06 +0400)]
DataFlash AT45DB021 support
Some boards based on AT91SAM926X-EK use smaller DF chips to keep
bootstrap, u-boot and its environment, using NAND or other external
storage for kernel and rootfs. This patch adds support for
small 1024x263 chip.
This patch fixes a potentially serious issue related to USB which was
discouvered by Martin Krause <martin.krause@tqs.de> and fixed for
ARM920T. Martin wrote:
Turn off USB to prevent the host controller from writing to the
SDRAM while Linux is booting. This could happen, because the HCCA
(Host Controller Communication Area) lies within the SDRAM and the
host controller writes continously to this area (as busmaster!), for
example to increase the HccaFrameNumber variable, which happens
every 1 ms.
This is a slightly modified version of the patch in order to shutdown
USB when booting on all architectures.
Harald Welte [Sun, 6 Jul 2008 16:58:05 +0000 (00:58 +0800)]
fix USB devices with multiple configurations
This patch fixes bugs in usbdcore*.c related to the use of devices
with multiple configurations.
The original code made mistakes about the meaning of configuration value and
configuration index, and the resulting off-by-one errors resulted in:
* SET_CONFIGURATION always selected the first configuration, no matter what
wValue is being passed.
* GET_DESCRIPTOR/CONFIGURATION always returned the descriptor for the first
configuration (index 0).
Signed-off-by: Harald Welte <laforge@openmoko.org> Acked-by: Markus Klotzbuecher <mk@denx.de>
Harald Welte [Sun, 6 Jul 2008 16:58:05 +0000 (00:58 +0800)]
fix USB devices with multiple configurations
This patch fixes bugs in usbdcore*.c related to the use of devices
with multiple configurations.
The original code made mistakes about the meaning of configuration value and
configuration index, and the resulting off-by-one errors resulted in:
* SET_CONFIGURATION always selected the first configuration, no matter what
wValue is being passed.
* GET_DESCRIPTOR/CONFIGURATION always returned the descriptor for the first
configuration (index 0).
Signed-off-by: Harald Welte <laforge@openmoko.org> Acked-by: Markus Klotzbuecher <mk@denx.de>
Stefan Roese [Thu, 10 Jul 2008 08:10:54 +0000 (10:10 +0200)]
MTD/NAND: Fix printf format warning in nand code
This patch fixes NAND related printf format warning. Those warnings are
now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd
[Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is
really helpful.
Stefan Roese [Tue, 8 Jul 2008 10:01:47 +0000 (12:01 +0200)]
pci: Move PCI device configuration check into a separate weak function
This patch moves the check, if a device should be skipped in PCI PNP
configuration into the function pci_skip_dev(). This function is defined
as weak so that it can be overwritten by a platform specific one if
needed. The check if the device should get printed in the PCI summary upon
bootup (when CONFIG_PCI_SCAN_SHOW is defined) is moved to the function
pci_print_dev() which is also defined as weak too.
Stefan Roese [Thu, 10 Jul 2008 07:58:06 +0000 (09:58 +0200)]
ppc4xx: Fix printf format warnings now visible with the updated format check
This patch fixes ppc4xx related printf format warning. Those warnings are
now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd
[Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is
really helpful.
Stefan Roese [Wed, 9 Jul 2008 15:33:57 +0000 (17:33 +0200)]
ppc4xx: Enable support for > 2GB SDRAM on AMCC Katmai
Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
To support such configurations, we "only" map the first 2GB via the TLB's. We
need some free virtual address space for the remaining peripherals like, SoC
devices, FLASH etc.
Note that ECC is currently not supported on configurations with more than 2GB
SDRAM. This is because we only map the first 2GB on such systems, and therefore
the ECC parity byte of the remaining area can't be written.
This patch makes SPARC targets build again. It is caused by
phys_addr_t and phys_size_t being defined in the wrong header
file. include/lmb.h need those typedefs to build.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Scott Wood [Wed, 9 Jul 2008 22:47:52 +0000 (17:47 -0500)]
NAND: ifdef-protect most of nand.h when using legacy NAND.
Some macros such as NAND_CTL_SETALE conflict between current and legacy
NAND, being defined by the subsystem in the former case and the board
config file in the latter.
Signed-off-by: Scott Wood <scottwood@freescale.com>
projects / u-boot / log