LS1046AQDS Specification:
-------------------------
Memory subsystem:
* 8GByte DDR4 SDRAM (64bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 64 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two XFI 10G ports
* Two SGMII ports
* Two RGMII ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Mingkai Hu [Wed, 7 Sep 2016 10:47:28 +0000 (18:47 +0800)]
armv8: ls1046ardb: Add LS1046ARDB board support
LS1046ARDB Specification:
-------------------------
Memory subsystem:
* 8GByte DDR4 SDRAM (64bit bus)
* 512 Mbyte NAND flash
* Two 64 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
* On-board 4G eMMC
Ethernet:
* Two XFI 10G ports
* Two SGMII ports
* Two RGMII ports
PCIe:
* PCIe1 (SerDes2 Lane0) to miniPCIe slot
* PCIe2 (SerDes2 Lane1) to x2 PCIe slot
* PCIe3 (SerDes2 Lane2) to x4 PCIe slot
SATA:
* SerDes2 Lane3 to SATA port
USB 3.0: one super speed USB 3.0 type A port
one Micro-AB port
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Wed, 7 Sep 2016 09:56:10 +0000 (17:56 +0800)]
armv8: fsl-layerscape: spl: remove BSS clearing and board_init_r
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly. Clearing BSS and calling board_init_r() will be done in
crt0_64.S.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Mingkai Hu [Wed, 7 Sep 2016 09:56:08 +0000 (17:56 +0800)]
armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency
According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error
that temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Fri, 26 Aug 2016 10:30:39 +0000 (18:30 +0800)]
driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a
This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.
Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Hongbo Zhang [Fri, 19 Aug 2016 09:20:30 +0000 (17:20 +0800)]
armv7: psci: make v7_flush_dcache_all public for all psci code
The v7_flush_dcache_all function will be called by ls102xa platform system
suspend, it is necessary to make it a public call instead of a local one, but
changing the LENTRY to ENTRY isn't enough, because there is another one using
the same name, so this one gets a psci_ prefix.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Tue, 2 Aug 2016 11:03:27 +0000 (19:03 +0800)]
fsl-layerscape: Add workaround for PCIe erratum A010315
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Tue, 2 Aug 2016 11:03:23 +0000 (19:03 +0800)]
arm: fsl-layerscape: move forward the non-secure access permission setup
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Hou Zhiqiang [Tue, 2 Aug 2016 11:03:22 +0000 (19:03 +0800)]
fsl: serdes: ensure accessing the initialized maps of serdes protocol
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
sec_init() which was earlier called in misc_init_r()
is now done in board_init() before PPA init as SEC
block will be used during PPA image validation.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
DDR controller 5.2.1 has this erratum A008511 partially fixed.
The workaround needs to be adjusted to take advantage of Vref
training. This patch enables the training and force output
enable to be off.
Erratum A009803 requires the controller to be idel before enabling
address parity. It was combined with workaround for A008511. With
new A008511 flow, this flow needs to be changed to enabling
data init (D_INIT) after the address parity is enabled.
Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Wed, 3 Aug 2016 03:04:25 +0000 (11:04 +0800)]
net: fm: fix spi flash probe for using driver model
The current code would always use the speed and mode set by
CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
SPI driver model it should get the values from DT.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
Cyrille Pitchen [Wed, 17 Aug 2016 07:19:39 +0000 (15:19 +0800)]
sf: fix sf probe
This patch fixes the "sf probe" command. The very first SPI flash probe
passes, for instance when u-boot tries to read its environment settings
from a (Q)SPI memory but next "sf probe" commands fail because the flash
memory node is unbound from the SPI controller children nodes.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 9 Sep 2016 01:26:39 +0000 (21:26 -0400)]
cmd: Rework disk.c usage
We only need the function found in cmd/disk.c when we have IDE, SCSI or
USB_STORAGE enabled. While the first two are easy to get right, in the
3rd case we assume that the set of cases where we do have USB and do not
enable USB_STORAGE are small enough that we can take the small bloat of
un-discarded strings on gcc prior to 6.x
Joshua Scott [Tue, 6 Sep 2016 04:03:11 +0000 (16:03 +1200)]
net: asix: Fix AX88772B when used with DriverModel
A previous patch (net: asix: fix operation without eeprom) added a
two-byte shift to the packet buffer when receiving a packet on the
AX88772B.
This shift was not included when the driver was updated to work with
DriverModel. Testing on a Marvell DB-88F6820-ACM showed that the adapter
was not functioning correctly (EHCI timeouts).
This patch brings the two-byte shift to the DriverModel implementation
of ops->recv (asix_eth_recv).
Testing on the same board, we were able to TFTP a file over and confirm
that the crc32 was correct.
Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Update the README to add support for K2G EVM. Also
- Add steps on how to use MMC boot
- Fix load address when using CCS
- Update build target to u-boot.bin from u-boot-dtb.bin as all ks2
platforms uses DT.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Provide version of struct efi_mem_desc in efi_get_memory_map().
EFI_BOOT_SERVICES.GetMemoryMap() in UEFI specification v2.6 defines
memory descriptor version to 1. Linux kernel also expects descriptor
version to be 1 and prints following warning during boot if its not:
Wenbin Song [Thu, 1 Sep 2016 08:28:22 +0000 (16:28 +0800)]
pxe: Modify README to add the description about FIT image
Use environment variable "kernel_addr_r" to indicate the location
in RAM where FIT image will be stored.
Use label command "kernel" to indicate which <path> the FIT image at.
York Sun [Thu, 1 Sep 2016 08:28:21 +0000 (16:28 +0800)]
pxe: Fix pxe boot with FIT image
When FIT image is used, a single image provides kernel, device
tree and optionally ramdisk. Argc and argv need to be adjusted
to support this.
Test cases:
1. Booting with legacy images
2. Booting with legacy images without initrd
3. Booting with FIT image
Test commands:
1. pxe get && pxe boot
2. sysboot
Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
omap3_pandora: Only set bootargs if distro_bootcmd failed to load.
As bootargs is hard-coded for the default behavior on the
omap3_pandora, only set the bootargs if distro_bootcmd fails to
load. This leaves distro_bootcmd free to use alternate boot arguments.
Masahiro Yamada [Tue, 30 Aug 2016 09:50:36 +0000 (18:50 +0900)]
Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROL
If both SPL_DM and SPL_OF_CONTROL are enabled, SPL needs to bind
several devices, but CONFIG_SYS_MALLOC_F_LEN=0x400 is apparently
not enough. Increase the default to 0x2000 for the case. This
will be helpful for shorter defconfigs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Tue, 30 Aug 2016 07:22:22 +0000 (16:22 +0900)]
ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig
Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms
can select. Then, move CONFIG_ARMV7_PSCI, which is automatically
enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
omap3_pandora: Fix mmc loading of autoboot script to use correct syntax.
fatload/ext2load both require that the device and partition be
specified after specifying the device type. Specify the first
partition on mmc device 0, which is the only mmc device currently
configured on the pandora.
Tom Rini [Fri, 26 Aug 2016 17:30:43 +0000 (13:30 -0400)]
TI: Rework SRAM definitions and maximums
On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area. As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow. As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.
Tested on OMAP4 Pandaboard, OMAP3 Beagle xM
Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Paul Kocialkowski <contact@paulk.fr> Cc: Enric Balletbo i Serra <eballetbo@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Weber <weber@corscience.de> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Heiko Schocher <hs@denx.de> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: "B, Ravi" <ravibabu@ti.com> Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: "Kipisz, Steven" <s-kipisz2@ti.com> Cc: Daniel Allred <d-allred@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
Adam Ford [Fri, 26 Aug 2016 12:53:53 +0000 (07:53 -0500)]
omap3logic: Fix PBIAS Bug
The PBIAS fixing is done in the MMC driver, and doing it in the
the board file conflicts with the driver causing intermittent
hangs on reboot. Remove this from the board file and let
the driver do it.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
An issue in the TI secure image generation tool causes the ROM to
load the SPL at a different load address than what is specified by
CONFIG_ISW_ENTRY_ADDR while doing a peripheral boot on HS devices.
This causes the SPL to fail on secure devices during peripheral
boot.
The TI secure image generation tool has been fixed so that the SPL
will always be loaded at 0x403018E0 by the ROM code for both
peripheral and memory boot modes.
ARM: AM57xx: Enable post-processing of FIT artifacts loaded by U-Boot
Enable the platform-specific post-processing of FIT-extracted blobs such
as Kernel, DTB, and initramfs on TI AM57xx high-security (HS) devices
which will ultimately invoke a ROM-based API call that performs secure
processing such as blob authentication.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
ARM: DRA7xx: Enable post-processing of FIT artifacts loaded by U-Boot
Enable the platform-specific post-processing of FIT-extracted blobs such
as Kernel, DTB, and initramfs on TI DRA7xx high-security (HS) devices
which will ultimately invoke a ROM-based API call that performs secure
processing such as blob authentication.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
ARM: AM43xx: Enable post-processing of FIT artifacts loaded by U-Boot
Enable the platform-specific post-processing of FIT-extracted blobs such
as Kernel, DTB, and initramfs on TI AM43xx high-security (HS) devices
which will ultimately invoke a ROM-based API call that performs secure
processing such as blob authentication.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
spl: Rework image header parse to allow abort on raw image and os boot
This reworks spl_set_header_raw_uboot to allow having both os boot
(which comes with a valid header) and aborting when no valid header is
found (thus excluding raw u-boot.bin images).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
Masahiro Yamada [Mon, 22 Aug 2016 13:18:22 +0000 (22:18 +0900)]
tools: moveconfig: add --spl option to move options for SPL build
Prior to this commit, the tool could not move options guarded by
CONFIG_SPL_BUILD ifdef conditionals because they do not show up in
include/autoconf.mk. This new option, if given, makes the tool
parse spl/include/autoconf.mk instead of include/autoconf.mk,
which is probably preferred behavior when moving options for SPL.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Masahiro Yamada [Mon, 22 Aug 2016 13:18:21 +0000 (22:18 +0900)]
tools: moveconfig: warn loudly if moved option has no entry in Kconfig
Currently, the tool gives up moving an option quietly if its entry
was not found in Kconfig.
If the option is not defined in the config header in the first
place, it is no problem (as the Kconfig entry may have been hidden
by reasonable "depends on").
However, if the option is defined in the config header, the missing
Kconfig entry is a sign of possible behavior change. It is highly
recommended to manually check if the option has been moved as
expected. In this case, let's add "suspicious" in the log and
change the log color (if --color option is given) to make it stand
out.
pinctrl: generic: scan for "pins" and "groups" properties in sub-nodes
In cases where the pins and groups definitions are in a sub-node, as:
uart_a {
mux {
groups = "uart_tx_a", "uart_rx_a";
function = "uart_a";
};
};
pinctrl_generic_set_state_subnode() returns an error for the top-level
node and pinctrl_generic_set_state() fails. Instead, return success so
that the child nodes are tried.
Alexander Graf [Mon, 15 Aug 2016 15:48:51 +0000 (17:48 +0200)]
serial: bcm283x_mu: Detect disabled serial device
On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.
However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted on to whoever calls
getc() today.
This patch adds detection logic for that case by checking whether the RX pin is
mapped to GPIO15 and disables the mini uart if it is not mapped properly.
That way we can leave the driver enabled in the tree and can determine during
runtime whether serial is usable or not, having a single binary that allows for
uart and non-uart operation.
Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Fabio Estevam [Fri, 26 Aug 2016 00:07:19 +0000 (21:07 -0300)]
warp7: Use PARTUUID to specify the rootfs location
warp7 can run different kernel versions, such as NXP 4.1 or mainline.
Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the eMMC
changes depending on the kernel version.
In order to avoid such issue, use UUID method to specify the rootfs
location.
Succesfully tested booting a NXP 4.1 and also a mainline kernel.
Fabio Estevam [Mon, 29 Aug 2016 23:37:16 +0000 (20:37 -0300)]
mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
we observe a hang when going into the lowest operational point of cpufreq.
This hang issue does not happen on the NXP U-Boot version.
After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting:
Fabio Estevam [Mon, 29 Aug 2016 23:37:15 +0000 (20:37 -0300)]
mx6: ddr: Allow changing REFSEL and REFR fields
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.
Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:
ft_board_setup may return early in the case that the board revision
cannot be obtained. In that case it is assumed that no revision
specific correction in the fdt is neccessary. But the mtd partitions
will not be fixed up either altough they are not revision specific.
Move the call to fdt_fixup_mtdparts in front of the revision specific
part to ensure that the partitions are fixed up even if the board
revision cannot be obtained.
While on it, fix a spelling mistake in a comment introduced by the
same commit.
Fixes: 62d6bac66038 ("ARM: board: cm_fx6: fixup mtd partitions in the fdt") Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Nikita Kiryanov <nikita@compulab.co.il>
Eric Nelson [Fri, 5 Aug 2016 23:51:17 +0000 (16:51 -0700)]
mx6ul_14x14_evk: don't use array for SD2 card detect pad
Only a single pad is changed to change sdhc2_dat3 from an
SDIO pin to and from GPIO4:5, so remove the array and use
the imx_iomux_v3_setup_pad() routine.
Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Mon, 15 Aug 2016 13:07:12 +0000 (10:07 -0300)]
warp: Fix RAM size runtime detection
Since commit a13d3757f7df ("warp: Use imx_ddr_size() for calculating the
DDR size") warp board no longer boots.
The reason for the breakage is that the warp board is using the DDR
configuration from mx6slevk. A fundamental difference between warp and
mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two.
The imx_ddr() function calculates the RAM size in runtime by reading the
values of registers MDCTL and MDMISC.
So in order to fix this warp boot issue, create a imximage DDR file specific
to warp, where the MDCTL register is configured to only activates a single
chip select.
Reported-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Breno Lima <breno.lima@nxp.com>
arm: imx: Add support for Advantech DMS-BA16 board
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Stefan Agner [Tue, 2 Aug 2016 06:55:18 +0000 (23:55 -0700)]
mtd: nand: mxs: fix cache alignment for cache lines >32
Currently the command buffer gets allocated with a size of 32 bytes.
This causes warning messages on systems with cache lines bigger than
32 bytes:
CACHE: Misaligned operation at range [9df17a00, 9df17a20]
Define command buffer to be at least 32 bytes, but more if cache
line is bigger.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
projects / u-boot / log