Heiko Schocher [Thu, 12 Mar 2009 06:37:18 +0000 (07:37 +0100)]
powerpc: common updates for keymile boards
- added to keymile-common.h:
- bootcount support
- COMMAND HISTORY
- CONFIG_AUTO_COMPLETE
- CONFIG_SYS_FLASH_PROTECTION
- JFFS2 support
- CONFIG_VERSION_VARIABLE
- extracted common I2C settings for all boards
- common default environment settings summarized
TsiChung Liew [Mon, 2 Mar 2009 19:16:45 +0000 (19:16 +0000)]
ColdFire: Fix M5329EVB and M5373EVB nand issue
The Nand flash was unable to read and write properly
due to Nand Chip Select (nCE) setup was in reverse
order. Also, increase the Nand time out value to 60.
TsiChung Liew [Wed, 18 Feb 2009 11:49:31 +0000 (11:49 +0000)]
ColdFire: Fix M54451 serial boot dram setup
The serial boot dram extended/standard mode register was not
setup and was using default DRAM setup causing the U-boot was
unstable to boot up in serial mode.
Ladislav Michl [Fri, 13 Mar 2009 13:38:19 +0000 (14:38 +0100)]
NAND: Make nboot skip bad blocks
nboot command currently does not skip bad blocks and gives read error when
loading image stored over bad block. With patch applied, nboot works as
expected:
Stefan Roese [Thu, 12 Mar 2009 06:27:25 +0000 (07:27 +0100)]
ppc4xx: lwmon5: Only use one CS (rank) in DDR2 configuration
This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with
the DDR2 configuration to only use one CS (rank). As this code is most
likely copied from the original Sequoia version, this error was copied
as well.
Stefan Roese [Thu, 12 Mar 2009 06:24:40 +0000 (07:24 +0100)]
ppc4xx: PMC440: Only use one CS (rank) in DDR2 configuration
This patch fixes a problem spotted by Mikhail Zolotaryov on Sequoia with
the DDR2 configuration to only use one CS (rank). As this code is most
likely copied from the original Sequoia version, this error was copied
as well.
Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D)
specifies that BankSel#1 is not connected, while bootloader memory
configuration is (board/amcc/sequoia/sdram.c):
mtsdram(DDR0_10, 0x00000300);
i.e. both Chip Selects used - not correct.
If we change to correct value here:
mtsdram(DDR0_10, 0x00000100);
memory is accessible OK also.
Signed-off-by: Mikhail Zolotaryov <lebon@lebon.org.ua> Signed-off-by: Stefan Roese <sr@denx.de>
Jerry Van Baren [Fri, 13 Mar 2009 15:40:10 +0000 (11:40 -0400)]
mpc83xx: Add bank configuration to FSL spd_sdram.c
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
mpc83xx: correctly set encryption and I2C bus 0 clock
This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.
Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Paul Gortmaker [Mon, 9 Mar 2009 23:07:53 +0000 (18:07 -0500)]
tsec: report when there is no vendor specific PHY support
Commit af1c2b84 added a generic phy support, with an ID of zero
and a 32 bit mask; meaning that it will match on any PHY ID.
The problem is that there is a test that checked if a matching
PHY was found, and if not, it printed the non-matching ID.
But since there will always be a match (on the generic PHY,
worst case), this test will never trip.
In the case of a misconfigured PHY address, or of a PHY that
isn't explicitly supported outside of the generic support,
you will never see the ID of 0xffffffff, or the ID of the
real (but unsupported) chip. It will silently fall through
onto the generic support.
This change makes that test useful again, and ensures that
the selection of generic PHY support doesn't happen without
some sort of notice. It also makes it explicitly clear that
the generic PHY must be last in the PHY table.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Andy Fleming <afleming@freescale.com>
Heiko Schocher [Tue, 24 Feb 2009 10:30:51 +0000 (11:30 +0100)]
8360, kmeter1: added bootcount feature.
add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU.
The bootcounter uses 8 bytes from the muram,
because no other memory was found on this
CPU for the bootcount feature. So we must
correct the muram size in DTS before booting
Linux.
This feature is actual only implemented for
MPC8360, because not all 83xx CPU have qe,
and therefore no muram, which this feature
uses.
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Heiko Schocher [Tue, 24 Feb 2009 10:30:48 +0000 (11:30 +0100)]
83xx, kmeter: QE_ENET10 errata for Silicon Revision 2.1
old code implemented the QE_ENET10 errata only for Silicon
Revision 2.0. New code reads now the Silicon Revision
register and sets dependend on the Silicon Revision the
values as advised in the QE_ENET10 errata.
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Heiko Schocher [Tue, 24 Feb 2009 10:30:37 +0000 (11:30 +0100)]
83xx, i2c: add mux support for fsl_i2c
This patch adds I2C mux support for the fsl_i2c driver. This
allows you to add "new" i2c busses, which are reached over
i2c muxes. For more infos, please look in the README and
search for CONFIG_I2C_MUX.
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Heiko Schocher [Tue, 24 Feb 2009 10:30:34 +0000 (11:30 +0100)]
83xx, kmeter1: add I2C, dtt, eeprom support
This patch adds I2C support for the Keymile kmeter1 board.
It uses the First I2C Controller from the CPU, for
accessing 4 temperature sensors, an eeprom with IVM data
and the booteeprom over a pca9547 mux.
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Dave Liu [Wed, 25 Feb 2009 04:31:32 +0000 (12:31 +0800)]
83xx: Fix some bugs in spd sdram code
1. RD_TO_PRE missed to add the AL, and need min 2 clocks for
tRTP according to DDR2 JEDEC spec.
2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec.
3. add the support of DDR2-533,667,800 DIMMs
4. cpo
5. make the AL to min to gain better performance.
The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.
items 1, 2 and 5: Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Thu, 19 Feb 2009 15:20:39 +0000 (18:20 +0300)]
mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signal
The SerDes initialization should be finished before negating the reset
signal according to the reference manual. This isn't an issue on real
hardware, but we'd better stick to the specifications anyway.
Suggested-by: Liu Dave <DaveLiu@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Mike Frysinger [Mon, 23 Feb 2009 15:29:47 +0000 (10:29 -0500)]
smc911x: split out useful defines/functions into local header
The smc911x driver has a lot of useful defines/functions which can be used
by pieces of code (such as example eeprom programmers). Rather than
forcing each place to duplicate these defines/functions, split them out
of the smdc911x driver into a local header.
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Ben Warren <biggerbadderben@gmail.com> CC: Sascha Hauer <s.hauer@pengutronix.de> CC: Guennadi Liakhovetski <lg@denx.de> CC: Magnus Lilja <lilja.magnus@gmail.com> CC: Ben Warren <biggerbadderben@gmail.com>
ARM: add an "eet" variant of the imx31_phycore board
The "eet" variant of the imx31_phycore board has an OLED display, using a
s6e63d6 display controller on the first SPI interface, using GPIO57 as a
chip-select for it. With this configuration you can display 256 colour BMP
images in 16-bit RGB (RGB565) LCD mode.
Add a driver for the Synchronous Display Controller and the Display
Interface on i.MX31, using IPU for DMA channel setup. So far only
displaying of bitmaps is supported, no text output.
This patch also simplifies some ifdefs in lcd.c, introduces a generic
vidinfo_t, which new drivers are encouraged to use and old drivers to switch
over to.
A driver for the S6E63D6 SPI display controller from Samsung
This is a driver for the S6E63D6 SPI OLED display controller from Samsung.
It only provides access to controller's registers so the client can freely
configure it.
i.MX31: support GPIO as a chip-select in the mxc_spi driver
Some SPI devices have special requirements on chip-select handling.
With this patch we can use a GPIO as a chip-select and strictly follow
the SPI_XFER_BEGIN and SPI_XFER_END flags.
This patch fixes an issue in config space read accessors: we should
fill-in the value even if we fail (e.g. skipping devices), otherwise
CONFIG_PCI_SCAN_SHOW reports bogus values during boot up.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Thu, 19 Feb 2009 15:20:42 +0000 (18:20 +0300)]
mpc83xx: PCIe: Don't start bus enumeration at 0
Currently we assign first_busno = 0 for the first PCIe hose, but this
scheme won't work if we have ordinary PCI hose already registered (its
first_busno value is 0 too).
The old code worked fine only because we have PCI disabled on
MPC837XEMDS boards in stand-alone mode (see commit 00f7bbae92e3b13f2b3
"mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards").
But on MPC837XERDB boards we have PCI and PCIe, so the bug actually
triggers.
So, to fix the issue, we should use pci_last_busno() + 1 for the
first_busno (i.e. last available busno).
Reported-by: Huang Changming <Chang-Ming.Huang@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Mike Frysinger [Mon, 22 Dec 2008 07:56:07 +0000 (02:56 -0500)]
smc911x_eeprom: new example app for managing newer SMC parts
A forward port of the last version to work with the newer smc911x driver.
I only have a board with a LAN9218 part on it, so that is the only one
I've tested. But there isn't anything in this that would make it terribly
chip specific afaik.
Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Sascha Hauer <s.hauer@pengutronix.de> CC: Guennadi Liakhovetski <lg@denx.de> CC: Magnus Lilja <lilja.magnus@gmail.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
MIPS: Fix GCC-4.2 'discards qualifiers from pointer target type' warnings
Compiling dbau1x00 and gth2 boards with GCC-4.2, you would see new warnings
like this:
skuribay@ubuntu:u-boot.git$ ./MAKEALL dbau1000
Configuring for dbau1x00 board...
au1x00_eth.c: In function 'au1x00_send':
au1x00_eth.c:158: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type
au1x00_eth.c: In function 'au1x00_recv':
au1x00_eth.c:211: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type
au1x00_eth.c: In function 'au1x00_init':
au1x00_eth.c:252: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type
au1x00_eth.c: In function 'au1x00_recv':
au1x00_eth.c:211: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type
au1x00_eth.c: In function 'au1x00_init':
au1x00_eth.c:252: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type
au1x00_eth.c: In function 'au1x00_send':
au1x00_eth.c:158: warning: passing argument 1 of 'virt_to_phys' discards qualifiers from pointer target type
We're passing a volatile pointer to a function which is expecting a non-
volatile pointer. That's potentially dangerous, so gcc warns about it.
Confirmed with ELDK 4.2 (GCC 4.2.2) and Sourcey G++ 4.2 (GCC 4.2.3).
To fix this, we add a volatile attribute to the argument in question.
The virt_to_phys function in Linux kernel also does the same thing.
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Dirk Behme [Thu, 12 Feb 2009 17:55:41 +0000 (18:55 +0100)]
OMAP3: Beagle: Add board revision detection
With BeagleBoard revision C some HW changes are introduced (e.g. PinMUX)
which might need different software handling. For this, GPIO pin 171 (GPIO
module 6, offset 11) can be used to check for board revision. If this pin
is low, we have a rev C board. Else it must be a revision Ax or Bx board.
To handle board differences you can call function beagle_get_revision().
E.g.:
Dirk Behme [Thu, 12 Feb 2009 17:55:40 +0000 (18:55 +0100)]
OMAP3: Overo: Clean up pin mux and GPIO configuration
* Make Overo GPIO114 an input for touchscreen PENDOWN
* Make Overo GPIO144-147 readable
* Make Overo EHCI pinmux match beagle rev c setup
* Adjust pinmux for SMSC911X network chip support
* Remove unnecessary GPIO setup
* Fix merge error in Makefile
Signed-off-by: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Hugo Villeneuve [Fri, 21 Nov 2008 19:35:56 +0000 (14:35 -0500)]
ARM DaVinci: Add common peripherals and modules enable functions.
Taken all the duplicated code for enabling common modules and apply
software workarounds from the board specific code into common
functions. Also added comments explaining the workarounds
(from TI errata documents) and replaced some numerical bit numbers
with more meaningful defines.
Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
projects / u-boot / log