Xiubo Li [Fri, 21 Nov 2014 09:40:59 +0000 (17:40 +0800)]
ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:58 +0000 (17:40 +0800)]
ARM: ls102xa: allow all the peripheral access permission as R/W.
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:57 +0000 (17:40 +0800)]
ls102xa: changing a few targets' configurations.
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:56 +0000 (17:40 +0800)]
ls1021a: adding a secondary core boot address and kick functions
Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.
Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:55 +0000 (17:40 +0800)]
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.
This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Fri, 21 Nov 2014 03:17:15 +0000 (11:17 +0800)]
fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
drivers: usb: fsl: Add USB device-tree errata framework
Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 9 Dec 2014 09:38:14 +0000 (17:38 +0800)]
arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 9 Dec 2014 09:38:02 +0000 (17:38 +0800)]
arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:48 +0000 (15:00 +0800)]
arm: ls102xa: Add SD boot support for LS1021ATWR board
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:47 +0000 (15:00 +0800)]
arm: ls102xa: Add SD boot support for LS1021AQDS board
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:46 +0000 (15:00 +0800)]
ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macro
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:43 +0000 (15:00 +0800)]
arm: spl: Add I2C linker list in generic .lds
On LS1, DDR is initialized by reading SPD through I2C interface
in SPL code. For I2C, ll_entry_count() is called, and it returns
the number of elements of a linker-generated array placed into
subsection of .u_boot_list section specified by _list argument.
So add I2C linker list in the generic .lds to fix the issue about
using I2C in SPL.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:42 +0000 (15:00 +0800)]
spl: Use u-boot.img instead of u-boot.bin
In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when producing u-boot-with-spl-pbl.bin.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:41 +0000 (15:00 +0800)]
ls102xa: pblimage: Add pblimage tool support for LS102xA
For LS102xA, the size of spl/u-boot-spl.bin is variable.
This patch adds the support to deal with the variable
u-boot size in pblimage tool. It will be padded to 64
byte boundary.
Use pblimage_check_params() to add the specific operations
for ARM, such as PBI CRC and END command and the calculation
of pbl_cmd_initaddr.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Masahiro Yamada [Fri, 5 Dec 2014 15:03:26 +0000 (00:03 +0900)]
ARM: UniPhier: detect the number of flash banks at run-time
Some UniPhier boards are equipped with an expansion slot that
some optional SRAM/NOR-flash cards can be attached to. So, run-time
detection of the number of flash banks would be more user-friendly.
Until this commit, UniPhier boards have achieved this by (ab)using
board_flash_wp_on() because the boot failed if flash_size got zero.
Fortunately, this problem was solved by commit 70879a92561a (flash:
do not fail even if flash_size is zero).
Now it is possible to throw away such a tricky workaround. This
commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further
refactoring.
Peter Kümmel [Sat, 29 Nov 2014 08:26:04 +0000 (17:26 +0900)]
kconfig: Fix warning "‘jump’ may be used uninitialized"
Warning:
In file included from scripts/kconfig/zconf.tab.c:2537:0:
scripts/kconfig/menu.c: In function ‘get_symbol_str’:
scripts/kconfig/menu.c:590:18: warning: ‘jump’ may be used uninitialized in this function [-Wmaybe-uninitialized]
jump->offset = strlen(r->s);
Simplifies the test logic because (head && local) means (jump != 0)
and makes GCC happy when checking if the jump pointer was initialized.
Signed-off-by: Peter Kümmel <syntheticpp@gmx.net> Signed-off-by: Michal Marek <mmarek@suse.cz>
[ imported from Linux Kernel, commit 2d5603060967 ] Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suriyan Ramasami [Thu, 27 Nov 2014 21:24:16 +0000 (13:24 -0800)]
fdt: Allow non-FDT kernels to boot when CONFIG_OF_LIBFDT is defined
The boot commands - bootz/bootm mandate a third argument which is the
address to the FDT blob. In cases where this argument is not specified,
boot fails with a message indicating a missing FDT.
This causes non-FDT kernels to fail to boot. This patch allows both FDT
and non-FDT kernels to boot by making the third parameter to the bootm/bootz
optional.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
[trini: Update again for covering appended DTB case after last revert in
this area] Signed-off-by: Tom Rini <trini@ti.com>
Introduce a Makefile under arch/$ARCH/ and include it in the
top Makefile (similar to Linux kernel). This allows further
refactoringi like moving architecture-specific code out of global
makefiles, deprecating config variables (CPU, CPUDIR, SOC) or
deprecating arch/$ARCH/config.mk.
In contrary to Linux kernel, U-Boot defines the ARCH variable by
Kconfig, thus the arch Makefile can only included conditionally
after the top config.mk.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Vikas Manocha [Fri, 21 Nov 2014 18:34:21 +0000 (10:34 -0800)]
serial: pl01x: move all line control at same place
Receive line control uses same setting as transmit line control, also one lcrh
write is effective for both baud rate & receive line control internal update.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
Vikas Manocha [Fri, 21 Nov 2014 18:34:20 +0000 (10:34 -0800)]
serial: pl01x: fix pl011 baud rate configuration
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
The CPU directory of this board is arch/powerpc/cpu/mpc5xxx.
Without the CONFIG_SPL_START_S_PATH and CONFIG_SPL_LDSCRIPT defines,
the same start.o and u-boot-spl.lds are selected by default.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
The CPU directory of this board is arch/powerpc/cpu/ppc4xx.
Without the CONFIG_SPL_START_S_PATH and CONFIG_SPL_LDSCRIPT defines,
the same start.o and u-boot-spl.lds are selected by default.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
Masahiro Yamada [Fri, 21 Nov 2014 02:26:11 +0000 (11:26 +0900)]
powerpc: mpc8xx: remove hermes board support
This board sprinkles #ifdef(CONFIG_HERMES) over various global files
such as include/common.h, common/board_r.c, common/cmd_bdinfo.c.
Let's zap such an ill-behaved board.
It has not been converted to generic board yet and mpc8xx is old
enough.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
Hector Palacios [Thu, 20 Nov 2014 08:27:42 +0000 (09:27 +0100)]
cmd_fuse: return CMD_RET_FAILURE on error
Fuse drivers, like the mxs_ocotp.c, may return negative error codes but
the commands are only allowed to return CMD_RET_* enum values to the
shell, otherwise the following error appears:
Stephen Warren [Thu, 20 Nov 2014 03:41:04 +0000 (20:41 -0700)]
ARM: rpi: support an environment
Enable ENV_IS_IN_FAT so that the environment can be stored persistently.
It's stored in the FAT partition that the RPi firmware requires. On most
RPis, this is on the SD card (which must be present in order for the
system to boot). On the CM this is on the built-in eMMC device.
Since we now have a persistent environment, there's no need to load
uEnv.txt at boot; we only did that to work around the lack of persistent
environment.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Wed, 19 Nov 2014 04:40:21 +0000 (21:40 -0700)]
ARM: rpi_b: detect board revision
Detect the board revision early during boot, and print the decoded
model name.
Eventually, this information can be used for tasks such as:
- Allowing/preventing USB device mode; some models have a USB device on-
board so only host mode makes sense. Others connect the SoC directly
to the USB connector, so device-mode might make sense.
- The on-board USB hub/Ethernet requires different GPIOs to enable it,
although luckily the default appears to be fine so far.
- The compute module contains an on-board eMMC device, so we could store
the environment there. Other models use an SD card and so don't support
saving the environment (unless we store it in a file on the FAT boot
partition...)
Set $fdtfile based on this information. At present, the mainline Linux
kernel doesn't contain a separate DTB for most models, but I hope that
will change soon.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Wu, Josh [Tue, 18 Nov 2014 05:07:08 +0000 (13:07 +0800)]
net: bootp: as CONFIG_BOOTP_SERVERIP is defined, keep bootfile not changed
Currenly when CONFIG_BOOTP_SERVERIP is defined, the SERVERIP is not changed
when receive the BOOTP packet. But BOOTFILE is changed via BOOTP packet.
As we will load the BOOTFILE from SERVERIP, if the BOOTFILE is modified
by bootp packet but SERVERIP is not, that is not make sense.
This patch make SERVERIP and BOOTFILE be consistent. If we define the
CONFIG_BOOTP_SERVERIP, then SERVERIP and BOOTFILE will not changed by
BOOTP packet. Only IP address is changed.
get_maintainer.pl always fails with following message:
./scripts/get_maintainer.pl: The current directory does not appear to be a linux kernel source tree.
We use MAINTAINERS for the maintainership of the supported boards.
For dead boards, we have some clues in doc/README.scrapyard and
also imperishable history in git-log.
Remove CREDITS from source tree detection to fix this.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 14 Nov 2014 03:51:12 +0000 (20:51 -0700)]
Fix console functions for U-Boot API
Commit 709ea54 made a subtle change to the way the U-Boot API jump table
is set up. So at present putc(), getc(), tstc() and puts() do not work
correctly from functions that use the U-Boot API.
Previously these were set to the stdio functions, but these now take a
parameter specifying which stdio device to use. Instead, we should change
them to use the global functions which do not have a parameter.
This is a slight change in behaviour. The functions will now output to
all selected stdio devices - for example putc() will output a character to
all devices selected by stdout. However in most cases there is only one,
and it isn't necessarily incorrect behaviour anyway.
The API version is not changed since it is compatible with what was there
before.
Reported-by: Martin Dorwig <dorwig@tektronik.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Raw images of U-Boot can be stored inside MMC partitions, so it makes sense to
read the partition table, looking for a partition number instead of using
a fixed sector address.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com>
[trini: Only add mmc_load_image_raw_partition() when
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to avoid warning, add missing
conversion in spl_mmc_load_image()] Signed-off-by: Tom Rini <trini@ti.com>
Mark Tomlinson [Mon, 1 Dec 2014 19:49:18 +0000 (08:49 +1300)]
i2c: Fix deselection of muxes
Due to an uninitialised variable, when muxes were deselected, any value
could be written to the mux control register. On the PCA9548, this could
result in multiple channels being selected, thus enabling multiple
pull-up resistors, and much bus capacitance.
The fix is simply to initialise the written value to zero.
Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Masahiro Yamada [Fri, 5 Dec 2014 15:03:22 +0000 (00:03 +0900)]
ARM: UniPhier: merge UniPhier config headers into a single file
Some configurations have been moved to Kconfig and the difference
among the config headers of UniPhier SoC variants is getting smaller
and smaller. Now is a good time to merge them into a single file.
Masahiro Yamada [Fri, 5 Dec 2014 15:03:21 +0000 (00:03 +0900)]
ARM: UniPhier: move support card select to Kconfig
There are two kinds of expansion boards which are often used for
the UniPhier platform and they are only exclusively selectable.
It can be better described by the "choice" menu of Kconfig.
Masahiro Yamada [Fri, 5 Dec 2014 03:20:58 +0000 (12:20 +0900)]
flash: do not fail even if flash_size is zero
CONFIG_SYS_MAX_FLASH_BANKS_DETECT allows to determine the number of
flash banks at run-time, that is, there is a possibility that no flash
bank is found. Even in such cases, it makes sense to continue the
boot process without any flash device.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de>
Minghuan Lian [Mon, 24 Nov 2014 10:20:46 +0000 (18:20 +0800)]
powerpc/hydra: fix judging condition of RGMII selection
BRDCFG1_EMI1_SEL_MASK has been changed to 0x78, which contains
selection bits and connected status bit. So the Corresponding mux
value of RGMII is changed to BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Chunhe Lan [Tue, 18 Nov 2014 03:11:54 +0000 (11:11 +0800)]
powerpc/hydra: Update MDIO mux fixups
The new device trees use a more generic interface for
supporting muxing mdio buses. The mux property is thus
specified in "reg", rather than "fsl,hydra-mdio-muxval".
In order to support using old device trees, we keep the
old fixup in there. Linux will therefore see the both
properties, but will ignore fsl,hydra-mdio-muxval.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Tudor Laurentiu [Thu, 20 Nov 2014 10:09:31 +0000 (12:09 +0200)]
powerpc/mpc85xx: use correct dma compatible for several SoCs
Newer qoriq socs have an updated dma ip block with a
different compatible. Let's make sure we use the proper
string so that the dmas get their liodn.
In order to have the means to specify the compatible
string, the liodn setting macros were updated to receive
a new parameter for it.
The following SoCs were changed to use the new compatible:
T1023/4, T1040, T2080/1, T4240, B4860.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Mon, 24 Nov 2014 09:11:58 +0000 (17:11 +0800)]
board/t1024qds: update pin multiplexing
Add multiplexing support among SPI flash, TDM riser card and SDXC.
it routes SPI pins to SPI flash by default.
Route SPI pins to SD slot if "adaptor=sdxc" is set in hwconfig.
Route SPI pins to TDM riser card and do fixup for dts if "pin_mux=tdm"
is set in hwconfig.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Mon, 24 Nov 2014 09:11:57 +0000 (17:11 +0800)]
net/fman: update 10GEC to fit new SoC
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
10GEC1->MAC1, 10GEC2->MAC2
so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Mon, 24 Nov 2014 09:11:56 +0000 (17:11 +0800)]
powerpc/t1024rdb: Add T1024 RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.
T1024RDB board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- one 10Gbps XFI interface
- PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors.
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD
- eSPI: 64MB N25Q512 SPI flash.
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- USB: Two Type-A USB2.0 ports with internal PHY
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC
- I2C: Four I2C controllers
- UART: Two UART serial ports
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Mon, 24 Nov 2014 09:11:55 +0000 (17:11 +0800)]
powerpc/t1024qds: Add T1024 QDS board support
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.
T1024QDS board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Three 1G/2.5Gbps SGMII ports
- Four 1Gbps QSGMII ports
- one 10Gbps XFI or 10Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Mon, 24 Nov 2014 09:11:54 +0000 (17:11 +0800)]
powerpc/mpc85xx: Add T1024/T1023 SoC support
Add support for Freescale T1024/T1023 SoC.
The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T1024 and T1023:
Feature T1024 T1023
QUICC Engine: yes no
DIU: yes no
Deep Sleep: yes no
I2C controller: 4 3
DDR: 64-bit 32-bit
IFC: 32-bit 28-bit
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 14 Nov 2014 02:31:22 +0000 (10:31 +0800)]
powerpc/t2080: updating rcw for silicon v1.1
T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0,
and also update core frequency to 1.8GHz for v1.1.
We reserve the support for T2080 v1.0 and enable v1.1 by default.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Suresh Gupta [Thu, 13 Nov 2014 03:28:09 +0000 (11:28 +0800)]
B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Thu, 13 Nov 2014 03:27:49 +0000 (11:27 +0800)]
powerpc/b4860qds: add workaround for XFI
XFI does not work stable on current board, it's due to heat sink issue,
to make it work stable the board needs additional heat sink, enable two
XFI lanes only. Right now we do not have such an erratum for the issue,
so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it.
The workaround will only be used in XFI protocols and only if the
hwconfig indicates that XFI is prefered.
A new VSC3308 config function is used instead of re-use the original
function, to avoid making the function complex and ugly.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Thu, 13 Nov 2014 03:26:19 +0000 (11:26 +0800)]
powerpc/b4860qds: add xfi support
We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
projects / u-boot / log