Karl Palsson [Fri, 21 Nov 2014 22:14:57 +0000 (22:14 +0000)]
stm32l: split l0/l1 support no jtag, different HSI settings
L0 is cortex m0+, so different id codes, SWD only, different addresses
for the clock speedup. It has no endian options, no boundary scan.
Removed all L0 specific portions from L1 files, and renamed files to clarify
their purpose. The deprecated stm32lx_stlink.cfg is kept as is, as it is only
around for backwards compatibility with prior releases.
Tested on STM32L053 Discovery and STM32L151 Discovery.
Has _not_ been tested with jtag on L1.
Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2405 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
Grigori Goronzy [Thu, 30 Oct 2014 00:14:58 +0000 (01:14 +0100)]
lpc2000: ignore status of part ID IAP command
The IAP firmware won't return a proper status with some versions. This
happens on my CCC r0ket board and others have seen it as well [1]. So
just ignore the status code and do a (weak) consistency check instead.
Antony Pavlov [Fri, 10 Oct 2014 04:13:46 +0000 (08:13 +0400)]
checkpatch.pl: check for openocd tree, not for kernel tree
checkpatch.pl looks for linux kernel specific paths and files
to check source tree. As openocd misses kernel files it ends
with this error message:
Must be run from the top-level dir. of a kernel tree
This patch also renames 'kernel' -> 'openocd'
in source tree-related messages.
Due to checkpatch checking modifications on itself, lift the
restriction on having no spaces at the start of a line for Perl
scripts. This can be readded back later.
In ChibiOS/RT 3.0 the ready list pointer "rlist" is now part of the system
data structure. Since the ready list is the first element in that
structure it can be accessed via the structure's symbol "ch".
Change-Id: Idc7eaa87cb7bbad0afa0ff1dafd54283bf429766 Signed-off-by: Christian Gudrian <christian.gudrian@gmx.de>
Reviewed-on: http://openocd.zylin.com/2352 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Andrey Yurovsky [Thu, 30 Oct 2014 18:56:08 +0000 (11:56 -0700)]
flash: at91samd: fix use of is_erased in check
is_erased can be one of -1, 0, or 1 so it must not be checked like a
boolean value. In this case we want to erase a page unless we know it's
already erased so we just check for is_erased != 1.
Thanks to Jim Paris for pointing this out on another driver.
Paul Fertser [Fri, 31 Oct 2014 11:30:57 +0000 (14:30 +0300)]
jtag/drivers/jlink: implement register command to fix SWD
Some J-Link fw versions require registration to be performed before
SWD operation is possible. It doesn't harm anyway, vendor's utilities
do it unconditionally.
Thanks go to Segger for providing the necessary information.
Change-Id: Iabd76c743eca86e2c817a97cb93c969fec3f7ac6 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2331 Tested-by: jenkins
Anders [Mon, 27 Oct 2014 19:55:50 +0000 (12:55 -0700)]
flash/nor/lpcspifi.c: fix bug that prevented clean reset after flash write
After SPI flash was written by the assembly language stub,
the last SPI command was not terminated by raising CS.
This left the SPI device in a hung state that prevented the
flash from being read by the M4 SPIFI controller, even after
the M4 was fully reset. To access the flash via SPIFI, it was
necessary to completely power cycle the board.
This fix adds the missing instructions to raise CS and
terminate the SPI command after the last byte. This allows
the M4 to be resumed or reset cleanly after flashing. The
SPIFI memory is now immediately accessable at address
0x1400 0000 after flashing is complete.
Change-Id: I4d5e03bded0fa00c430c2991f182dc18611d5f48 Signed-off-by: Anders <anders@openpuma.org>
Reviewed-on: http://openocd.zylin.com/2359 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Jim Paris [Wed, 29 Oct 2014 23:09:49 +0000 (19:09 -0400)]
nrf51: fix checks for is_erased
is_erased can take the value 0 (no), 1 (yes), or -1 (unknown).
Checks like (!is_erased) don't do the right thing if it's -1.
Change-Id: I10ba32c99494ca803e0a7a1ba56fdd78184b96bb Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/2366 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Jim Paris [Wed, 29 Oct 2014 23:00:52 +0000 (19:00 -0400)]
nrf51: verify that UICR needs erasing before triggering an error about it
If the UICR is already empty, there's no reason to return an error
just because it can't be erased again. This happens, for example,
when flashing UICR from GDB after a "monitor nrf51 mass_erase".
Change-Id: Ia6d28c43189205fb5a7120b1c7312e45eb32edb7 Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/2363 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Jim Paris [Wed, 29 Oct 2014 03:15:31 +0000 (23:15 -0400)]
nrf51: fix UICR erase
nrf51_erase_page() checks for (sector->offset == NRF51_UICR_BASE) to
determine if the UICR should be erased. However, sector->offset for
the UICR bank is set to 0 in nrf51_probe, so this code is never hit.
Attempting to erase UICR ends up erasing the first flash sector.
Use bank->base instead to determine if UICR is being erased.
Change-Id: Ie5df0f9732f23662085ae2b713d64968cd801472 Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/2362 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Jim Paris [Tue, 28 Oct 2014 20:20:16 +0000 (16:20 -0400)]
nrf51: fix UICR region size
The UICR region is actually 0x100 bytes in size. Besides making the
full region accessible, having the right value is important because
GDB rounds flash addresses to the nearest multiple of the block size
when determing which flash blocks to erase.
Change-Id: I416c391cbfc7be41a03a9b9c6e42326c87391f38 Signed-off-by: Jim Paris <jim@jtan.com>
Reviewed-on: http://openocd.zylin.com/2361 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
Peter Lawrence [Sun, 2 Nov 2014 00:31:49 +0000 (17:31 -0700)]
arm_adi_v5: added two CoreSight peripheral IDs
added "Single Wire Output" and "Trace Memory Controller" peripheral
IDs to dap_rom_display(), which is invoked by the "dap info" command
Change-Id: Iea3201007bb98e6376fbb50be40a4a2e031b0a03 Signed-off-by: Peter Lawrence <majbthrd@gmail.com>
Reviewed-on: http://openocd.zylin.com/2369 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Rémi PRUD'HOMME [Wed, 1 Oct 2014 21:43:03 +0000 (22:43 +0100)]
stm32: add mass erase support for STM32L
The mass erase for STM32L was lack because the procedure is more complex
than the procedure for the STM32F4xx.
The reference manual RM0038 (L100 subfamily) page 79 is more accurate
than the reference manual for the STM32L0xx. On the L0, the mass-erase
erase also the EEPROM. This is a limit to mass erase on L0.
The mass erase procedure is a command of telnet interface.
Paul Fertser [Wed, 1 Oct 2014 06:36:02 +0000 (10:36 +0400)]
libusb: introduce jtag_libusb_choose_interface() and use it for JLink
This introduces a new common function that allows auto-discovery of a
suitable USB interface based on class, subclass and protocol
matching. It claims the interface and returns the corresponding
endpoints number to the caller.
The need for this arised due to nRF51822 USB dongle which comes with
an "on-board Segger J-link debugger" having 3 interfaces, so the
current code can't work at all with it (in this particular case the
last interface needs to be choosen). This also removes special
handling of JLink-OB endpoint numbers as it's now possible to
autodetect them as well as the standard JLink endpoints.
Change-Id: I4d990a7a3b373efdd2949a394b32d855a168e138 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2327 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Tue, 19 Aug 2014 17:16:20 +0000 (21:16 +0400)]
hla: add a way to pass arbitrary commands from user to layout and use for ICDI
TI's ICDI adapter supports some additional commands which a user might
want to run for debugging or other purposes, the most useful of them
being "debug unlock" that fully mass-erases the device and unprotects
the flash.
Change-Id: I26990e736094367f92106fa891e9bb8fb0382efb Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2263 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Wed, 10 Sep 2014 08:29:23 +0000 (12:29 +0400)]
interface/ftdi/olimex-arm-usb-ocd-h: fix nTRST control definition
According to my inspection of an Olimex ARM-USB-OCD-H adapter ACBUS0
is connected directly to an SN74LVC2T45 buffer input B2, and the
corresponding output A2 is connected directly to the JTAG
connector. It seems the information in the Olimex flyer is incorrect
for the -H version and TRST can't be tri-stated, ACBUS2 is unused.
The older ARM-USB-OCD device has SN74AC244 for an output buffer and
ACBUS2 controls its !2OE, ACBUS0 connected to 2A1 (2Y1 is nTRST), in
accordance with the information flyer.
Change-Id: I22828b7b959b6f62c3f51367feb8fab9705641e5 Reported-by: Tim Sander <tim@krieglstein.org> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2286 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Tim Sander <tim@krieglstein.org>
Anders [Fri, 12 Sep 2014 15:44:33 +0000 (08:44 -0700)]
jtag/drivers/jlink.c: fix for LPC Link-2 running JLink firmware on Linux
Change 2288 fixed the extraneous reset caused by set_configuration that
crashed the LPC Link-2 running JLink firmware and works on windows platforms.
On Linux however, conditional code was still calling USB reset and caused
the adapter to crash on any non-windows platforms.
Anders [Thu, 2 Oct 2014 02:42:33 +0000 (19:42 -0700)]
jtag/drivers/libusb1_common: avoid device reset when reselecting configuration
According to [1], we shouldn't reselect an already active configuration to avoid needless device reset. This is known to cause issues with e.g. LPC Link2 with JLink firmware.
at91samd: fix protect, add EEPROM and boot commands
There were two problems with the _protect() feature:
1. The address written was off by a factor of two because the address
register takes 16-bit rather than 8-bit addresses. As a result the
wrong sectors were (un)protected with the protect command. This has
been fixed.
2. The protection settings issued via the lock or unlock region commands
don't persist after reset. Making them persist requires modifying the
LOCK bits in the User Row using the infrastructure described below.
The Atmel SAMD2x MCUs provide a User Row (the size of which is one
page). This contains a few settings that users may wish to modify from
the debugger, especially during production. This change adds commands
to inspect and set:
- EEPROM size, the size in bytes of the emulated EEPROM region of the
Flash.
- Bootloader size, the size in bytes of the protected "boot" section of
the Flash.
This is done by a careful read-modify-write of the special User Row
page, avoiding erasing when possible and disallowing the changing of
documented reserved bits. The Atmel SAMD20 datasheet was used for bit
positions and descriptions, size tables, etc. and testing was done on a
SAMD20 Xplained Pro board.
It's technically possible to store arbitrary user data (ex: serial
numbers, MAC addresses, etc) in the remaining portion of the User Row
page (that is, beyond the first 64 bits of it). The infrastructure used
by the eeprom and bootloader commands can be used to access this as
well, and this seems safer than exposing the User Row as a normal Flash
sector that openocd understands due to the delicate nature of some of
the data stored there.
Andrey Yurovsky [Wed, 6 Aug 2014 21:28:37 +0000 (14:28 -0700)]
at91samd: add erase/secure commands, minor fix
Reference code for the SAMD2x disables caching in the NVM controller when
issuing NVM commands. Let's do this as well to be consistent and safer.
Add a "chip-erase" for the Atmel SAMD targets that issues a complete Chip Erase
via the Device Service Unit (DSU). This can be used to "unlock" or otherwise
unbrick a chip that can't be halted or inspected, allowing the user to reflash
with new firmware.
Add a "set-security" command which issues an SSB. Once that's done and the
device is power-cycled, the flash cannot be written to until a "chip-erase" is
issued. The chip-erase cannot be issued by openocd at this time because
the device will not respond to a request for the DAP IDCODE.
Jon Burgess [Sun, 21 Sep 2014 19:40:01 +0000 (20:40 +0100)]
cortex_m.c: Use two byte breakpoint for 32bit Thumb-2 request
When GDB requests a breakpoint on a 32bit Thumb-2 instruction it
sends a length of 3 which the current code rejects. Using the
existing two byte breakpoint for this case appears to work fine.
The use of length==3 for this case is mentioned in a few places:
https://sourceware.org/gdb/onlinedocs/gdb/ARM-Breakpoint-Kinds.html
http://sourceforge.net/p/openocd/mailman/message/30012280/
Change-Id: I59cd69ba4d1bc9a37b86569738c6bb2a67c3eb7a Signed-off-by: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/2312 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is because any command line that starts with a valid command group is
classified as a group, triggering ocd_bouncer to print the confusing
message.
Fix by requiring that to be a command group, the command line must not
contain any unknown tokens after the last valid (sub-)command group. That
is OK because command groups don't have handlers defined and thus can't
take any parameters.
Also fix the error message for "unknown" type to be similar to the error
message that is printed (by Jim) for non-existent primary commands.
Change-Id: I26950349f0909fd3961c4f9ab9b198c221cea9fc Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2285 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Remove this underutilized feature. Despite the fact that a lot of configs
specifies a arbitrary "variant", only the xscale target actually defines
any.
In the case of xscale, the use of -variant is dubious since
1) it's used as a redundant irlen specifier,
2) it carries a comment that it doesn't really need it and
3) only two xscale configs even specify it.
If there's a future target that needs a variant set, a target specific
option could be added when needed.
Change-Id: I1ba25a946f0d80872cbd96ddcc48f92695c4ae20 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2283 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Previous to this version the code of handle_flash_probe_command would
probe a bank twice: first time by auto-probe through a call to
flash_command_get_bank and second time by calling the probe function
directly. This change adds a flash_command_get_bank_maybe_probe wich
is a more generic version of the flash_command_get_bank, that would
allow commands to decide whether auto-probing should be performed or
not.
Paul Fertser [Sun, 31 Aug 2014 07:04:39 +0000 (11:04 +0400)]
target/arm_dpm: prevent endless loop in arm_dpm_full_context()
The code treats registers that are shadowed in FIQ mode in a special
way: to read them out the target is first switches to USR mode. But
since USR != ANY the current implementation later skips register read,
and the loop becomes endless in case any !valid ARM_MODE_ANY is
present at the moment arm_dpm_full_context() is called. This was
reported in https://sourceforge.net/p/openocd/tickets/76/. The issue
surfaced because 2efb1f14f611f2ff8a380b703f3e8bcb8a95d1ad added two
ARM_MODE_ANY registers ("sp" and "lr") which were not normally read,
so at the time a user was calling "arm reg" they were not valid.
Fix this by changing the mode appropriately while keeping the "mode"
variable state intact so it would later match register's mode.
Compile-tested only.
Change-Id: I01840e8fa20ec392220138a3f1497ac25deb080a Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2278 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch adds support for QSPI flash controller driver for
Marvell's Wireless Microcontroller platform.
For more information please refer,
https://origin-www.marvell.com/microcontrollers/wi-fi-microcontroller-platform/
Following things have been tested on 88MC200 (Winbond W25Q80BV flash chip):
1. Flash sector level erase
2. Flash chip erase
3. Flash write in normal SPI mode
4. Flash fill (write and verify) in normal SPI mode
The hla_serial command allows for a programming device serial number to be
specified in addition to USB VID/PID. This allows for multiple ST-LINK/V2
programmers to be attached to a single machine and operated using openocd.
Change-Id: I350654bf676eb26ba3a90450acfa55d2a5d2d791 Signed-off-by: Austin Phillips <austin_phillips@hotmail.com>
Reviewed-on: http://openocd.zylin.com/2198 Tested-by: jenkins Reviewed-by: Martin Glunz <mg@wunderkis.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Anders [Mon, 8 Sep 2014 04:18:55 +0000 (21:18 -0700)]
flash: added new Spansion S25FL116K, S25FL132K, and S25FL164K devices
The new FL1-K family is replacing the FL-K family. The data from all
three was based on the datasheet. In addition the 8MB S25FL164K was
tested successfully with OpenOCD on a custom board.
Change-Id: Idafeed86da12a481c0db92cc0de7ba28f50c2252 Signed-off-by: Anders <anders@openpuma.org>
Reviewed-on: http://openocd.zylin.com/2281 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Andrey Yurovsky [Thu, 28 Aug 2014 18:54:29 +0000 (11:54 -0700)]
stm32lx: don't allow part_info to be uninitialized
It's possible for us to fail to read the part ID code so make sure that
part_info is initialized to NULL before attempting to do so, otherwise
we could proceed and use it uninitialized and then segfault.
Change-Id: I0a3f3d3947690b66f0981b5046340449521e0b33 Signed-off-by: Jack Peel <jack.peel@synapse.com> Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/2276 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Бурага Александр [Mon, 25 Aug 2014 17:42:59 +0000 (21:42 +0400)]
tcl/target: add config for К1879ХБ1Я, a hybrid ARM11/DSP SoC by RC Module
This adds config to allow JTAG debugging of an ARM core of a modern
hybrid SoC by Research Centre "Module"
(http://www.module.ru/en/company/). К1879ХБ1Я is targetted at set-top
boxes and other multimedia equipment, the official SDK is Linux-based.
Change-Id: Ib2ae5784d25699f952682e66b025a3f677a76d5d Signed-off-by: Бурага Александр <dtp-avb@yandex.ru> Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2272 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Paul Fertser [Thu, 14 Aug 2014 15:57:47 +0000 (19:57 +0400)]
tcl/interface/ftdi: fix TRST for Olimex TINY adapters
According to the research by Eldar, TINY-H adapter has nTRST connected
to ACBUS0 directly via a 100 Ohms series resistor. I think it's safe
to assume the older TINY adapter does the same.
See high-res photos at [1].
This patch should fix issues with JTAG for the case when nTRST is
actually connected but is missing from the config.
Paul Fertser [Tue, 19 Aug 2014 14:49:53 +0000 (18:49 +0400)]
flash/nor/stellaris: add all Tiva C parts IDs
Luckily, TI's website has predictable URLs for the datasheets, so it
was trivial to download all the pdfs corresponding to the currently
available 71 TivaC devices. Then they were processed with pdftotext
and parsed by this script:
BEGIN { capture = -1 }
/^Device Identification 0 \(DID0\)$/ { state = "waitingclass0" }
/^Device Identification 1 \(DID1\)$/ { state = "waitingpartno0" }
/^CLASS$/ { if (state == "waitingclass0") state = "waitingclass"
else if (state == "waitingclass") capture = 4 }
/^PARTNO$/ { if (state == "waitingpartno0") state = "waitingpartno"
else if (state == "waitingpartno") capture = 4 }
(FNR == 3) { family = $2 }
{
if (capture >= 0) {
if (capture == 0) {
if (state == "waitingclass")
class = $0
else if (state == "waitingpartno")
partno = $0
}
capture--
}
}
END { print "{" class ", " partno ", \"" family "\"}," }
Change-Id: I6820c409fe535f08394c203276b5af4406fe8b92 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2262 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This struct and libusb_get_device_descriptor() method are not present
in libusb-0.1 API, so when libusb-1.0 is unavailable, this code breaks
the build. Fix by using the appropriate struct (which is apparently
filled automatically on device initialisation).
While at it, change return values for consistency with the callers.
Change-Id: I7d85ab9a70401a155a65122397008ae4d81382fe Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2252 Tested-by: jenkins Reviewed-by: Austin Phillips <austin_phillips@hotmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Paul Fertser [Tue, 19 Aug 2014 07:44:42 +0000 (11:44 +0400)]
jtag: always configure enabled tap parameter appropriately
Commit f701c0cb seems to have introduced a regression for non-JTAG
transports as the newly created "tap" (DAP actually) ended up being
disabled, thus resulting in total lack of functionality.
This was exposed by a debug log demonstrating ftdi SWD transport
connection to mdr32f9q2i, the target wasn't examined on init and
couldn't be reset.
This adds initial support for the STM32L0 family, specifically the ID
code 417 variant. The 'L0 has 128B rather than 256B pages as well as a
different number of pages per sector. It also has several key registers
and register sets in different locations from the STM32L1xx parts.
This change therefore takes the opportunity to reorganize part information into
a const table (it was previously determined by a set of control statements) and
abstracts away some of the low-level details to make them generic for L1 and
L0 parts.
We also include the first bank's size (for dual bank parts) in the new
device information table (and correct that size for the 0x437 variant
which is 256 rather than 192KB).
The 'L0 parts will not use the built-in loader/helper for Flash writing.
Tested on STM32L053 (dicovery board and Nucleo board) and STM32L152
(discovery board).
Robert Jarzmik [Sun, 27 Jul 2014 10:30:13 +0000 (12:30 +0200)]
jtag: usb_blaster: fix initialization regression
As Daniel pointed out, since the rewrite of the USB Blaster driver, the
initialization behaviour has change. The initial flush of the FIFOs is
not longer done with a specific USB setup packet, but with a write
filling up the blaster queues.
The problem is, quoting Daniel :
When the CPLD is in bit banging mode (as is usually the case), the
first 0x00 byte sets all pins to low and disables the output
driver. Disabling the output drivers is a few nanoseconds slower
than changing a pin from high to low, so I see a spike towards GND
on my reset line when that byte is sent over USB. The spike is too
short to have an effect on the board.
When the 4096 0x00 bytes are processed and the TMS=1 is to be
generated, all I see is several microseconds of low level on all
pins, resetting my board.
This patch changes the way the initialization is done :
- at driver init, nothing is sent towards the usb-blaster
This gives time for init script to setup PIN6 and PIN8 (resets)
- at the very first driver command, the initialization is done :
- the output is in bit bigbang mode
- the PIN6 and PIN8 are computed according to init script
- the 4096 computed output is sent
Change-Id: If7ceee957f6b59bcb27c8f912f1cfdd0f94f75ed Reported-by: Daniel Glöckner <daniel-gl@gmx.net> Cc: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-on: http://openocd.zylin.com/2229 Tested-by: jenkins Reviewed-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-by: Daniel Glöckner <daniel-gl@gmx.net> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Oleksij Rempel [Wed, 5 Feb 2014 22:11:15 +0000 (23:11 +0100)]
mips32.c: cache debug caps and support EJTAG 2.0 specific changes
EJTAG v2.0 indicated some debug caps in IMP register.
V2.6 moved them to DCR register. To make it more universal,
convert this values and store them for later use.
projects / openocd / log