]> git.sur5r.net Git - openocd/commitdiff
at91sam4: Adding support for the AT91SAM4S4A.
authorThomas Schmid <thomas@rfranging.com>
Fri, 15 Aug 2014 21:08:23 +0000 (15:08 -0600)
committerSpencer Oliver <spen@spen-soft.co.uk>
Mon, 24 Nov 2014 22:15:36 +0000 (22:15 +0000)
Added the chip definition for the Atmel AT91SAM4S4A. This chip is a 48-pin
package with 256k flash and 64k ram.

Change-Id: I8ada7d5735e31e0ce086f96f5906c7358464245c
Signed-off-by: Thomas Schmid <thomas@rfranging.com>
Reviewed-on: http://openocd.zylin.com/2254
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
src/flash/nor/at91sam4.c

index 8e873a6c7e76254796f0928c1e6533ae24688dea..6e53b4e94da78987d9db66fdbdc0d7f3731cad6c 100644 (file)
@@ -496,6 +496,40 @@ static const struct sam4_chip_details all_sam4_details[] = {
                },
        },
 
+       /*atsam4s4a - LQFP48/BGA48*/
+       {
+               .chipid_cidr    = 0x288b09e0,
+               .name           = "at91sam4s4a",
+               .total_flash_size     = 256 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = {*/
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK_BASE_S,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  256 * 1024,
+                       .nsectors   =  32,
+                       .sector_size = 8192,
+                       .page_size   = 512,
+                 },
+/*             .bank[1] = {*/
+                 {
+                       .present = 0,
+                       .probed = 0,
+                       .bank_number = 1,
+
+                 },
+               },
+       },
+
        /*at91sam4sd32c*/
        {
                .chipid_cidr    = 0x29a70ee0,