Andre Przywara [Thu, 19 Sep 2013 16:06:42 +0000 (18:06 +0200)]
ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.
We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.
Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0xFFFFFFFF)
The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Andre Przywara [Thu, 19 Sep 2013 16:06:41 +0000 (18:06 +0200)]
ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.
Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)
Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.
The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.
After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Andre Przywara [Thu, 19 Sep 2013 16:06:40 +0000 (18:06 +0200)]
ARM: add secure monitor handler to switch to non-secure state
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
r9 is a platform-specific register in ARM EABI and not per
definition a general purpose register. Do not use it while
relocating so it can be used for gd.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Michal Simek [Wed, 28 Aug 2013 05:36:31 +0000 (07:36 +0200)]
arm: zynq: Fix timer loadaddress
Reload address was written to the counter register
instead of load register.
The problem happens when timer expires but never
reload to ~0UL (it is downcount timer).
Reported-by: Stephen MacMahon <stephenm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jeroen Hofstee [Sat, 24 Aug 2013 11:55:38 +0000 (13:55 +0200)]
arm: prevent using movt/movw address loads
The movt/movw instruction can be used to hardcode an
memory location in the instruction itself. The linker
starts complaining about this if the compiler decides
to do so: "relocation R_ARM_MOVW_ABS_NC against `a local
symbol' can not be used" and it is not support by U-boot
as well. Prevent their use by requiring word relocations.
This allows u-boot to be build at other optimalization
levels then -Os.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: TigerLiu@viatech.com.cn Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Simon Glass <sjg@chromium.org>
am335x_evm.h: If mmcdev and bootpart switch to mmcdev 1, so should mmcroot.
If, in CONFIG_BOOTCOMMAND, the environment switches both the mmcdev
and bootpart variables to refer to MMC device 1, it would make sense
that the mmcroot env variable should switch to that device as well.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
if phy_connect() did not find a phy, phydev is NULL and
following code in cpsw_phy_init() crashes. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Lokesh Vutla [Fri, 23 Aug 2013 12:04:17 +0000 (17:34 +0530)]
ARM: OMAP5: Avoid writing into LDO SRAM bits
Writing magic bits into LDO SRAM was suggested only for OMAP5432
ES1.0. Now these are no longer applicable. Moreover these bits should
not be overwritten as they are loaded from EFUSE. So avoid
writing into these registers.
Steve Kipisz [Wed, 14 Aug 2013 14:51:31 +0000 (10:51 -0400)]
am335x:Handle worst case scenario for Errata 1.0.24
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Adapt to current framework] Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Fri, 30 Aug 2013 20:28:46 +0000 (16:28 -0400)]
am335x_evm: am33xx_spl_board_init function and scale core frequency
Add a am33xx_spl_board_init (and enable the PMICs) that we may see,
depending on the board we are running on. In all cases, we see if we
can rely on the efuse_sma register to tell us the maximum speed. In the
case of Beaglebone White, we need to make sure we are on AC power, and
are on later than rev A1, and then we can ramp up to the PG1.0 maximum
of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that
supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we
cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we
need to rely on the efuse_sma if we are on PG2.1, and the defaults for
PG1.0/2.0.
doc: README.mxs: Add instruction to install 'libssl-dev'
Since commit bce883707 (ARM: mxs: tools: Add mkimage support for MXS bootstream)
the following build error is seen when doing a MAKEALL build:
$ ./MAKEALL mx28evk
Configuring for mx28evk - Board: mx28evk, Options: ENV_IS_IN_MMC
mxsimage.c:18:25: fatal error: openssl/evp.h: No such file or directory
Add an entry about the need of installing the 'libssl-dev' package.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
mx6sabresd: Avoid hang when HDMI cable is not connected
Since commit d9b894603 (mx6sabresd: Add LVDS splash screen support) the
following hang happens if the HDMI cable is not connected or the 'panel'
variable is not set:
wandboard: Use imx6dl-wandboard.dtb for the solo version
The wandboard solo version should boot the 'imx6dl-wandboard.dtb' file, since
dual-lite and solo variants are the same SoC with only the number of cores being
different.
Tom Rini [Fri, 30 Aug 2013 20:28:45 +0000 (16:28 -0400)]
am33xx: Add the efuse_sma CONTROL_MODULE register
Starting with PG2.1 we have a register in the CONTROL_MODULE that is set
with the package type and maximum supported frequency. Add this, and
the relevant mask/values.
Tom Rini [Fri, 30 Aug 2013 20:28:44 +0000 (16:28 -0400)]
am33xx: Add am33xx_spl_board_init function, call
We need to allow for a further call-out in spl_board_init. Call this
am33xx_spl_board_init and add a __weak version. This function may be
used to scale the MPU frequency up, depending on board needs.
Philip, Avinash [Fri, 30 Aug 2013 20:28:43 +0000 (16:28 -0400)]
drivers/power/pmic: Add tps65910 driver
Add a driver for the TPS65910 PMIC that is found in the AM335x GP EVM,
AM335x EVM SK and others.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
[trini: Split and rework Avinash's changes into new drivers/power
framework] Signed-off-by: Tom Rini <trini@ti.com>
Greg Guyotte [Fri, 30 Aug 2013 20:28:42 +0000 (16:28 -0400)]
drivers/power/pmic: Add tps65217 driver
Add a driver for the TPS65217 PMIC that is found in the Beaglebone
family of boards.
Signed-off-by: Greg Guyotte <gguyotte@ti.com>
[trini: Split and rework Greg's changes into new drivers/power
framework] Signed-off-by: Tom Rini <trini@ti.com>
arm: atmel: cpux9k2: increase malloc space to fix crash on start u-boot
Since UBIFS is enabled for cpux9k2, more malloc space is needed.
For the current uboot 2013.10-rcX the size is to small, this will fix the
startup problems by increasing the malloc space to 4MiB.
Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Kuo-Jung Su [Mon, 29 Jul 2013 05:51:43 +0000 (13:51 +0800)]
arm: dma_alloc_coherent: malloc() -> memalign()
Even though the MMU/D-cache is off, some DMA engines still
expect strict address alignment.
For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet
controllers expect the tx/rx descriptors should always be aligned
to 16-bytes boundary.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tom Rini [Tue, 10 Sep 2013 13:51:44 +0000 (09:51 -0400)]
Revert "standalone-examples: support custom GCC lib"
After further testing, this patch has two problems. First,
examples/standalone/Makefile was already inherting PLATFORM_LIBS from
the top-level Makefile so this lead to duplicating the private libgcc.
Second, currently the private libgcc has a reference to 'hang' that is
not being fulfilled.
Albert ARIBAUD [Wed, 11 Sep 2013 13:52:51 +0000 (15:52 +0200)]
Merge and reformat boards.cfg and MAINTAINERS
Put all informations about targets, including state (active or
orphan) and maintainers, in boards.cfg; remove MAINTAINERS;
adjust the build system accordingly.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org> Signed-off-by: Nicolas Colombain <nicolas.colombain@armadeus.com>
root@(none):/sys/devices/virtual/mtd/mtd0# for i in ecc_strength oobsize subpagesize; do echo $i = `cat $i`; done
ecc_strength = 16
oobsize = 224
subpagesize = 4096
The ECC strength was not properly discovered by U-Boot causing the data
written by Linux to return an -74 (EBADMSG) when read from U-Boot. This
patch fixes mxs_nand_get_ecc_strength() to function in case of a NAND
flash with page_data_size = 4096 and page_oob_size= 224.
Signed-off-by: Elie De Brauwer <eliedebrauwer@gmail.com> Acked-by: Scott Wood <scottwood@freescale.com>
arm:goni:mmc: Add sd card detection and initialization.
This change allow to use sd card on Goni the same like mmc 0.
SD card is mmc dev 1, so it can be used like this: "fatls mmc 1:2".
SD card is inited even if eMMC initialization fails.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
As per new convention ARCH_CPU_DTS is not defined in "dtc/Makefile".
Hence Arndale comilation is failing. Fix this by adding proper include
file in "board/samsung/dts/exynos5250-arndale.dts".
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Marek Vasut [Sat, 31 Aug 2013 13:53:46 +0000 (15:53 +0200)]
ARM: mxs: Add SanDisk Sansa Fuze+ board
Add STMP3780-based Sansa Fuze+ board. This board is a small PMP
device sporting a CPU which was later rebranded to i.MX233 .
Currently supported is USB gadget mode and MMC .
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Sat, 31 Aug 2013 13:53:45 +0000 (15:53 +0200)]
ARM: mxs: Add Creative ZEN XFi3 board
Add STMP3780-based XFi3 board. This board is a small PMP device
sporting a CPU which was later rebranded to i.MX233 . Currently
supported is USB gadget mode and both external SD and internal
Phison SD-NAND bridge .
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Sat, 31 Aug 2013 13:53:44 +0000 (15:53 +0200)]
ARM: mxs: Receive r0 and r1 passed from BootROM
Make sure value in register r0 and r1 is preserved and passed to
the board_init_ll() and mxs_common_spl_init() where it can be
processed further. The value in r0 can be configured during the
BootStream generation to arbitary value, r1 contains pointer to
return value from CALL'd function.
This patch also clears the value in r0 before returning to BootROM
to make sure the BootROM is not confused by this value.
Finally, this patch cleans up some comments in the start.S file.
Andrew Gabbasov [Thu, 4 Jul 2013 11:27:32 +0000 (06:27 -0500)]
mx6: Fix calculation of emi_slow clock rate
This is porting of Freescale's patch from version imx_v2009.08_3.0.35_4.0.0,
that fixes the obvious mistype of bits offset macro name (ACLK_EMI_PODF_OFFSET
was used instead of ACLK_EMI_SLOW_PODF_OFFSET).
Using the occasion, change the variable name 'emi_slow_pof' to more consistent
'emi_slow_podf'.
Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
powerpc/mpc85xx: Fix the I2C bus speed error on p1022
The source clock frequency of I2C bus on p1022 is the platform(CCB)
clock, not CCB/2. The wrong source clock frequency leads to wrong
I2C bus speed setting. so, fixed it.
Stefan Roese [Mon, 26 Aug 2013 10:08:48 +0000 (12:08 +0200)]
ppc4xx: Fix GPIO handling in lwmon5 and lcd4_lwmon5 BSP
LCD4 needs a slightly different GPIO configuration than the
original LWMON5 variant. GPIO49 needs to be configured to a
default output value of 0 (permanent voltage supply).
Additionally lcd4 also needs to enable the LSB transmitter.
Rob Herring [Sat, 24 Aug 2013 15:10:54 +0000 (10:10 -0500)]
ahci: convert to use libata functions and definitions
libata already has similar functions as implemented in the ahci code.
Refactor the code to use the libata variants and remove the dependency on
ata.h. Convert some defines to use the version from libata.h. Also, remove
some unnecessary memset's of bss data.
This is a step toward hopefully merging ahci.c and dw_ahsata.c which are
essentially the same driver.
Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
Rob Herring [Sat, 24 Aug 2013 15:10:51 +0000 (10:10 -0500)]
ahci: move link bring-up handling to separate function
Move the link bring-up handling to a separate weak function in order to
allow platforms to override it. This is needed on highbank platform which
needs special phy handling.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Richard Gibbs [Sat, 24 Aug 2013 15:10:47 +0000 (10:10 -0500)]
ahci: use ports implemented map instead of num_ports
The AHCI driver was incorrectly using the Capabilities register NP (number
of ports) field to determine which ports to activate. This commit changes
it to correctly use the PORTS_IMPL register as a port map.
Signed-off-by: Richard Gibbs <richard.gibbs@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com>
fs: fat: don't call disk_write with zero sector num
In the set_cluster() function, it will convert the buffer size to sector
numbers. Then call disk_write() to write by sector.
For remaining buffer, the size is less than a sector, call disk_write()
again to write them in one sector.
But if the total buffer size is less then one sector, the original code
will call disk_write() with zero sector number. It is unnecessary.
So this patch fix this. Now it will not call disk_write() if total buffer size
is less than one sector.
Jeroen Hofstee [Sat, 10 Aug 2013 15:16:50 +0000 (17:16 +0200)]
compiler_gcc: do not redefine __gnu_attributes
gcc allows extensions to be non compiler specific by defining
__* macros for the attributes supported by gcc. Having a
different definition causes many warnings during the build
(cdefs.h on FreeBSD uses __attribute((__pure__)) where u-boot
uses __attribute__((pure)) for example). Do not redefine
these macros to suppress these warnings.
This patch ignores the checkpatch warning:
WARNING: __packed is preferred over __attribute__((packed))
Chin Liang See [Wed, 7 Aug 2013 15:08:03 +0000 (10:08 -0500)]
socfpga: Creating driver for Reset Manager
Consolidating reset code into reset_manager.c. Also
separating reset configuration for virtual target and
real hardware Cyclone V development kit
Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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