Add a header for SAMA5D2 SMC since it's not compatible with
SAMA5D3 one.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[wenyou: fix the wrong base address of the SMC register] Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
mmc: atmel_sdhci: not on capabilities to set gck rate
The capabilities have default values which doesn't reflect the reality
when it concerns the base clock and the mul value. Use a fixe rate
for the gck. 240 MHz is an arbitrary choice, it is a multiple of the
maximum SD clock frequency handle by the controller and it allows to
get a 400 kHz clock for the card initialisation.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Wenyou Yang [Fri, 17 Nov 2017 06:50:22 +0000 (14:50 +0800)]
clk: at91: clk-generated: fix incorrect index of clk source
Differentiate the generic clock source selection value from the parent
clock index to fix the incorrect assignment of the generic clock
source selection.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Patrice Chotard [Wed, 15 Nov 2017 12:14:52 +0000 (13:14 +0100)]
clk: clk_stm32fx: add clock configuration for mmc usage
MMC block needs 48Mhz source clock, for that we choose
to select the SAI PLL.
Update also stm32_clock_get_rate() to retrieve the MMC
clock source needed in MMC driver.
STM32F4 uses a different RCC variant than STM32F7. For STM32F4
sdmmc clocks bit are located into dckcfgr register whereas there
are located into dckcfgr2 registers on STM32F7.
In both registers, bits CK48MSEL and SDMMC1SEL are located at
the same position.
Patrice Chotard [Wed, 15 Nov 2017 12:14:51 +0000 (13:14 +0100)]
dm: misc: bind STM32F4/F7 clock from rcc MFD driver
Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.
Patrice Chotard [Wed, 15 Nov 2017 12:14:47 +0000 (13:14 +0100)]
clk: stm32f7: add STM32F4 support
STM32F4 and STM32F7 RCC clock IP are very similar.
Same driver can be used to managed RCC clock for
these 2 SoCs.
Differences between STM32F4 and F7 will be managed using
different compatible string :
_ overdrive clock is only supported by STM32F7
_ different sys_pll_psc parameters can be used between STM32F4
and STM32F7.
Patrice Chotard [Wed, 15 Nov 2017 12:14:46 +0000 (13:14 +0100)]
ARM: DTS: stm32: update rcc compatible for STM32F746
Align the RCC compatible string with the one used by kernel.
It will allow to use the same clock driver for STM32F4
and STM32F7 and to manage the differences between the 2 SoCs
Add a dedicated stm32f7 compatible string to use clk_stm32f7
driver with both STM32F4 and STM32F7 SoCs.
It will be needed to manage differences between these 2 SoCs.
tools: env: Add support for direct read/write UBI volumes
Up to now we were able to read/write environment data from/to UBI
volumes only indirectly by gluebi driver. This driver creates NAND MTD
on top of UBI volumes, which is quite a workaroung for this use case.
Add support for direct read/write UBI volumes in order to not use
obsolete gluebi driver.
Forward-ported from this patch:
http://patchwork.ozlabs.org/patch/619305/
Original patch: Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Forward port: Signed-off-by: S. Lockwood-Childs <sjl@vctlabs.com>
Rick Chen [Thu, 23 Nov 2017 06:19:36 +0000 (14:19 +0800)]
spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi
atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.
Rick Chen [Thu, 23 Nov 2017 04:48:46 +0000 (12:48 +0800)]
atcpit100: timer: Remove arch dependency.
ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.
Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Rick Chen [Thu, 23 Nov 2017 03:04:34 +0000 (11:04 +0800)]
ae3xx: timer: Fix ae3xx timer work abnormal in 64 bit.
It will be work fine with unsigned long declaretion in timer
register struct when system is 32 bit. But it will not work
well when system is 64 bit. Replace it by u32 and verify both
ok in 32/64 bit.
Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 29 Nov 2017 13:26:07 +0000 (08:26 -0500)]
Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.1
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling
ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board
Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
net: xilinx_axi_emac: Use readl and writel for io ops
This patch uses readl and writel instead of in_be32 and
out_be32 for io ops as these internally uses readl,
writel for microblaze and for Zynq, ZynqMP there is
no need of endianness conversion and readl, writel
should work straightaway. This patch starts supporting
the driver for Zynq and ZynqMP platforms.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: Dont enable SGMII and PCS selection
Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 23 Nov 2017 07:25:41 +0000 (08:25 +0100)]
arm: zynq: Change Zynq/ZynqMP Kconfig description
Use more accurate description for Xilinx Zynq and ZynqMP based platforms.
With using driver model there shouldn't be a need to create separate
Kconfig config options.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
tools: zynqmpimage: adjust ug1085 reference to v1.4 of the document
The chapter in which the table explaining the image format changed
chapter as the document evolved. This should help people track the
info down faster.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Joe Hershberger [Tue, 7 Nov 2017 02:16:10 +0000 (18:16 -0800)]
mtd: nand: zynq: Add support for the NAND lock/unlock operation
Zynq NAND driver is not support for NAND lock or unlock operation.
Hence, accidentally write into the critical NAND region might cause
data corruption to occur.
This commit is to add NAND lock/unlock command into NAND SMC register
set for NAND lock/unlock operaion.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Wilson Lee [Wed, 15 Nov 2017 09:14:35 +0000 (01:14 -0800)]
mtd: zynq: nand: Move board_nand_init() function to board.c
Putting board_nand_init() function inside NAND driver was not appropriate
due to it doesn't allow board vendor to customise their NAND
initialization code such as adding NAND lock/unlock code.
This commit was to move the board_nand_init() function from NAND driver
to board.c file. This allow customization of board_nand_init() function.
Signed-off-by: Wilson Lee <wilson.lee@ni.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Cc: Scott Wood <oss@buserror.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 12:28:07 +0000 (13:28 +0100)]
arm: zynq: Use unsigned type with comparison with ARRAY_SIZE
Sparse is return warning about this:
arch/arm/mach-zynq/slcr.c: In function 'zynq_slcr_get_mio_pin_status':
arch/arm/mach-zynq/slcr.c:185:16: warning: comparison between signed and
unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
^
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 08:47:28 +0000 (09:47 +0100)]
arm: zynq: Move common ps7_init* initialization to arch code
This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.
The patch is also marking ps7_config as weak function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: xilinx_axi_emac: Add support for non processor mode
Add support for non processor mode, this mode doesn't have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.
Paul Burton [Tue, 21 Nov 2017 22:31:07 +0000 (14:31 -0800)]
boston: Add u-boot.mcs make target
U-Boot is generally flashed to a MIPS Boston development board by means
of a .mcs file which Xilinx Vivado software can write to the flash
present on the board. As such we'd generally want to produce an mcs file
when building U-Boot to target the Boston board. Introduce a make target
for u-boot.mcs which generates it using the srec_cat tool available from
the SRecord project, and build it by default when srec_cat is present.
Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
Paul Burton [Tue, 21 Nov 2017 20:35:31 +0000 (12:35 -0800)]
boston: Set CONFIG_SYS_LOAD_ADDR to 0x88000000
Generally we load Linux kernels on Boston boards in the form of FIT
images containing a compressed kernel binary. Linux is linked at
0x80100000 and so we need to decompress the kernel binary to that
address, however this is our default load address which means that
unless explicitly avoided we hit a decompression error as the
uncompressed kernel binary overwrites its compressed version from the
FIT image.
Avoid this by adjusting CONFIG_SYS_LOAD_ADDR to 0x88000000 (or
0xffffffff88000000 for MIPS64 builds) which avoids the address overlap
between compressed & uncompressed kernel binaries.
Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
Paul Burton [Tue, 21 Nov 2017 19:18:39 +0000 (11:18 -0800)]
MIPS: Break out of cache loops for unimplemented caches
If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.
Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
Paul Burton [Tue, 21 Nov 2017 19:18:38 +0000 (11:18 -0800)]
MIPS: Clear instruction hazards in flush_cache()
When writing code, for example during relocation, we ensure that the
icache has a coherent view of the new instructions with a call to
flush_cache(). This handles the bulk of the work to ensure the new
instructions will execute as expected, however it does not ensure that
the CPU pipeline doesn't already contain instructions taken from a stale
view of the affected memory. This could theoretically be a problem for
relocation, but in practice typically isn't because we sync caches for
enough code after the entry point of the newly written code that by the
time the CPU pipeline might possibly fetch any of it we'll have long ago
written it back & invalidated any stale icache entries. This is however
a problem for shorter regions of code.
In preparation for later patches which write shorter segments of code,
ensure any instruction hazards are cleared by flush_cache() by
introducing & using a new instruction_hazard_barrier() function which
makes use of the jr.hb instruction to clear the hazard.
Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
Paul Burton [Tue, 21 Nov 2017 19:18:37 +0000 (11:18 -0800)]
MIPS: Ensure cache ops complete in cache maintenance functions
A typical use of cache maintenance functions is to force writeback of
data which a device is about to read using DMA - for example a
descriptor or command structure. Such users of cache maintenance
functions require that operations on the cache have completed before
they proceed to instruct a device to read memory. This requires that we
place a completion barrier (ie. sync instruction) between the cache ops
and whatever write informs the device to perform DMA.
Whilst strictly speaking this isn't all users of the cache maintenance
functions & we could instead place the barriers in the drivers that
require them, it would be much more invasive to do so than to just have
the barrier be the default by placing it in the cache functions
themselves. The cost is low enough that it shouldn't matter to us in any
rare cases that we use the cache functions when not performing DMA.
Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
Paul Burton [Mon, 30 Oct 2017 23:58:21 +0000 (16:58 -0700)]
Update Paul Burton's email address
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.
Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
Paul Burton [Fri, 15 Sep 2017 18:35:54 +0000 (11:35 -0700)]
MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.lds
The u-boot.lds linker script for MIPS defines a PTR_COUNT_SHIFT macro to
2 or 3 for 32 bit or 64 bit builds respectively. This macro is never
actually used though, so remove the dead code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Paul Burton [Fri, 15 Sep 2017 18:33:53 +0000 (11:33 -0700)]
boston: Drop unused return value
The boston lowlevel_init() function zeroes the return register v0,
despite the function not being expected to return a value & that value
never being used.
Remove the redundant assignment to v0.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Masahiro Yamada [Fri, 24 Nov 2017 15:25:32 +0000 (00:25 +0900)]
ARM: uniphier: remove IRQ settings
This work-around has been here in U-Boot because the AIDET and GPIO
drivers were missing in the upstream Linux. Both are now available
in Linus' tree:
- drivers/irqchip/irq-uniphier-aidet.c
- drivers/gpio/gpio-uniphier.c
Masahiro Yamada [Tue, 21 Nov 2017 17:38:32 +0000 (02:38 +0900)]
mtd: nand: denali: sync with Linux 4.15-rc1
I largely reworked the Denali NAND controller driver in Linux.
This commit imports the improvements from Linux. The code is
almost synced with Linux 4.15-rc1.
Masahiro Yamada [Tue, 21 Nov 2017 17:38:31 +0000 (02:38 +0900)]
mtd: nand: introduce NAND_ROW_ADDR_3 flag
Several drivers check ->chipsize to see if the third row address cycle
is needed. Instead of embedding magic sizes such as 32MB, 128MB in
drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since
nand_scan_ident() knows well about the device, it can handle this
properly. The flag is set if the row address bit width is greater
than 16.
Delete comments such as "One more address cycle for ..." because
intention is now clear enough from the code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Wenyou Yang <wenyou.yang@microchip.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 14157f861437ebe2d624b0a845b91bbdf8ca9a2d]
Masahiro Yamada [Tue, 21 Nov 2017 17:38:30 +0000 (02:38 +0900)]
mtd: nand: add a shorthand to generate nand_ecc_caps structure
struct nand_ecc_caps was designed as flexible as possible to support
multiple stepsizes (like sunxi_nand.c).
So, we need to write multiple arrays even for the simplest case.
I guess many controllers support a single stepsize, so here is a
shorthand macro for the case.
Driver are responsible for setting up ECC parameters correctly.
Those include:
- Check if ECC parameters specified (usually by DT) are valid
- Meet the chip's ECC requirement
- Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set
The logic can be generalized by factoring out common code.
This commit adds 3 helpers to the NAND framework:
nand_check_ecc_caps - Check if preset step_size and strength are valid
nand_match_ecc_req - Match the chip's requirement
nand_maximize_ecc - Maximize the ECC strength
To use the helpers above, a driver needs to provide:
- Data array of supported ECC step size and strength
- A hook that calculates ECC bytes from the combination of
step_size and strength.
By using those helpers, code duplication among drivers will be
reduced.
Boris Brezillon [Tue, 21 Nov 2017 17:38:28 +0000 (02:38 +0900)]
mtd: nand: Pass the CS line to ->setup_data_interface()
Some NAND controllers can assign different NAND timings to different
CS lines. Pass the CS line information to ->setup_data_interface() so
that the NAND controller driver knows which CS line is concerned by
the setup_data_interface() request.
Masahiro Yamada [Tue, 21 Nov 2017 17:38:27 +0000 (02:38 +0900)]
mtd: nand: allow drivers to request minimum alignment for passed buffer
In some cases, nand_do_{read,write}_ops is passed with unaligned
ops->datbuf. Drivers using DMA will be unhappy about unaligned
buffer.
The new struct member, buf_align, represents the minimum alignment
the driver require for the buffer. If the buffer passed from the
upper MTD layer does not have enough alignment, nand_do_*_ops will
use bufpoi.
Boris Brezillon [Tue, 21 Nov 2017 17:38:26 +0000 (02:38 +0900)]
mtd: nand: Wait for PAGEPROG to finish in drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS
Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the
full read/write page sequence, and waiting for a page to actually be
programmed is part of this write-page sequence.
This is also what is done in ->write_oob_xxx() hooks, so let's do that in
->write_page_xxx() as well to make it consistent.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 41145649f4acb30249b636b945053db50c9331c5]
[masahiro:
There is no driver setting NAND_ECC_CUSTOM_PAGE_ACCESS in U-Boot.
No driver is affected by this change.] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Marc Gonzalez [Tue, 21 Nov 2017 17:38:22 +0000 (02:38 +0900)]
mtd: nand: Support controllers with custom page
If your controller already sends the required NAND commands when
reading or writing a page, then the framework is not supposed to
send READ0 and SEQIN/PAGEPROG respectively.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit: 3371d663bb4579f1b2003a92162edd6d90edd089] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Boris Brezillon [Tue, 21 Nov 2017 17:38:21 +0000 (02:38 +0900)]
mtd: nand: Add a few more timings to nand_sdr_timings
Add the tR_max, tBERS_max, tPROG_max and tCCS_min timings to the
nand_sdr_timings struct.
Assign default/safe values for the statically defined timings, and
extract them from the ONFI parameter table if the NAND is ONFI
compliant.
Boris Brezillon [Tue, 21 Nov 2017 17:38:20 +0000 (02:38 +0900)]
mtd: nand: Fix data interface configuration logic
When changing from one data interface setting to another, one has to
ensure a specific sequence which is described in the ONFI spec.
One of these constraints is that the CE line has go high after a reset
before a command can be sent with the new data interface setting, which
is not guaranteed by the current implementation.
Rework the nand_reset() function and all the call sites to make sure the
CE line is asserted and released when required.
Also make sure to actually apply the new data interface setting on the
first die.
Boris Brezillon [Tue, 21 Nov 2017 17:38:19 +0000 (02:38 +0900)]
mtd: nand: automate NAND timings selection
The NAND framework provides several helpers to query timing modes supported
by a NAND chip, but this implies that all NAND controller drivers have
to implement the same timings selection dance. Also currently NAND
devices can be resetted at arbitrary places which also resets the timing
for ONFI chips to timing mode 0.
Provide a common logic to select the best timings based on ONFI or
->onfi_timing_mode_default information. Hook this into nand_reset()
to make sure the new timing is applied each time during a reset.
NAND controller willing to support timings adjustment should just
implement the ->setup_data_interface() method.
Sascha Hauer [Tue, 21 Nov 2017 17:38:17 +0000 (02:38 +0900)]
mtd: nand: convert ONFI mode into data interface
struct nand_data_interface is the designated type to pass to
the NAND drivers to configure the timing. To simplify further
patches convert the onfi_sdr_timings array from type struct
nand_sdr_timings nand_data_interface.
Sascha Hauer [Tue, 21 Nov 2017 17:38:16 +0000 (02:38 +0900)]
mtd: nand: Introduce nand_data_interface
Currently we have no data structure to fully describe a NAND timing.
We only have struct nand_sdr_timings for NAND timings in SDR mode,
but nothing for DDR mode and also no container to store both types
of timing.
This patch adds struct nand_data_interface which stores the timing
type and a union of different timings. This can be used to pass to
drivers in order to configure the timing.
Add kerneldoc for struct nand_sdr_timings while touching it anyway.
Sascha Hauer [Tue, 21 Nov 2017 17:38:15 +0000 (02:38 +0900)]
mtd: nand: Create a NAND reset function
When NAND devices are resetted some initialization may have to be done,
like for example they have to be configured for the timing mode that
shall be used. To get a common place where this initialization can be
implemented create a nand_reset() function. This currently only issues
a NAND_CMD_RESET to the NAND device. The places issuing this command
manually are replaced with a call to nand_reset().
Boris Brezillon [Tue, 21 Nov 2017 17:38:13 +0000 (02:38 +0900)]
mtd: nand: Add an option to maximize the ECC strength
The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.
In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).
Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
[Linux commit: ba78ee00e1ff84de9b3ad33edbd3ec599099ee82]
[masahiro: of_property_read_bool -> fdt_getprop for U-Boot] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
projects / u-boot / log