Hans de Goede [Sat, 27 Dec 2014 16:56:59 +0000 (17:56 +0100)]
sunxi: Fix PLL1 running at half speed on sun8i
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
sunxi: Fix buggy sun6i/sun8i DRAM size detection logic
After reboot, reset or even short power off, DRAM typically retains
the old stale data for some period of time (for this type of memory,
the bits of data are stored in slowly discharging capacitors).
The current sun6i/sun8i DRAM size detection logic, which is
inherited from the Allwinner code, relies on using a large magic
signature with the hope that it is unique enough and unlikely to
ever accidentally match this leftover garbage data in RAM. But
this approach is inherently unsafe, as can be demonstrated using
the following test program:
/***** A testcase for reproducing the problem ******/
void main(int argc, char *argv[])
{
size_t size, i;
uint32_t *buf;
/* Allocate the buffer */
if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) ||
!(buf = malloc(size))) {
printf("Need buffer size in MiB as a cmdline argument\n");
exit(1);
}
/* Fill it with the Allwinner DRAM "magic" values */
for (i = 0; i < size / 4; i++)
buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64;
/* Try to reboot */
system("reboot");
/* And wait */
for (;;) {}
}
/***************************************************/
If this test program is run on the device (giving it a large
chunk of memory), then the DRAM size detection logic in u-boot
gets confused after reboot and fails to initialize DRAM properly.
A better approach is not to rely on luck and abstain from making
any assumptions about the properties of the leftover garbage
data in RAM. Instead just use a more reliable code for testing
whether two different addresses refer to the same memory location.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch uses the same DRAM settings as in the pre-installed
Android firmware. The LCD display is supported too.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch uses the same ZQ and DRAM clock settings as in the
pre-installed Android firmware.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: Fix CONFIG_UART0_PORT_F build and add it to menuconfig
The CONFIG_UART0_PORT_F option has been supported since
http://git.denx.de/?p=u-boot.git;a=commit;h=ff2b47f6a9cc1025
This option is primarily useful only for low level u-boot debugging
on tablets, where normal UART0 is difficult to access and requires
device disassembly and/or soldering.
This patch now allows it to be selected from menuconfig. A dependency on
SPL_FEL is added because u-boot does not support booting from NAND yet
and also booting from SD card is impossible when a MicroSD breakout board
is plugged into the SD slot.
Additionally a compilation problem is fixed:
common/spl/built-in.o: In function `spl_mmc_load_image':
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:94: undefined reference to `mmc_initialize'
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:96: undefined reference to `find_mmc_device'
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:104: undefined reference to `mmc_init'
scripts/Makefile.spl:206: recipe for target 'spl/u-boot-spl' failed
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Sat, 20 Dec 2014 11:25:14 +0000 (12:25 +0100)]
sun8i: Ippo_q8h_v5_defconfig: Enable SPL support
Now that we've sun8i dram-init support we can enable the SPL for sun8i boards.
While at it also replace CONFIG_DEFAULT_DEVICE_TREE with CONFIG_FDTFILE,
the former is for u-boot's own fdt usage, which we do not use (yet), the later
specifies the fdt to pass to the kernel, which is the one we want.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 8 Dec 2014 12:58:53 +0000 (13:58 +0100)]
sunxi: Fill memory before comparing it when doing dram init on sun6i
The sun8i boot0 code fills the DRAM with a "random" pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not do it, instead relying on the memory contents being random enough
to begin with for the memcmp to properly detect the wrap-around address, iow
it is working purely by chance. Since our sun6i dram code was modelled after
the boot0 code it contained the same issue.
This commit fixes this by filling the memory with a unique, distinct pattern.
The new mctl_mem_fill function this introduces is added as an inline helper
in dram.h, so that it can be shared with the sun8i dram code.
While at it move mctl_mem_matches to dram.h for re-use in sun8i too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 8 Dec 2014 12:38:21 +0000 (13:38 +0100)]
sunxi: Move await_completion dram helper to dram.h
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h, rather then adding yet another copy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 7 Dec 2014 20:09:31 +0000 (21:09 +0100)]
sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them
Our old hardcoded k and m values are based on PLL5 being configured in steps
of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the
DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i)
the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps.
This commit adjusts clock_set_pll5 to automatically select the best k and m
depending on the requested clk rate.
Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 13 Dec 2014 13:02:38 +0000 (14:02 +0100)]
sunxi: axp221: Explicitly turn off unused voltages
Explicitly turn off unused voltages, rather then leaving them as is. Likewise
explictly enabled the dcdc convertors, rather then assuming they are already
enabled at boot.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 13 Dec 2014 13:12:06 +0000 (14:12 +0100)]
sunxi: axp221: Make dcdc1 voltage configurable
The dcdc1 voltage is typically used as generic 3.3V IO voltage for things like
GPIO-s, sdcard interfaces, etc. On most boards this is undervolted to 3.0V to
safe battery, but not on all, make it configurable so that we can use the
same settings as the original firmware on all boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 13 Dec 2014 11:40:45 +0000 (12:40 +0100)]
sunxi: axp221: Add Kconfig help and sane defaults for typical ldo usage
Some of the ldo-s of the axp221 are used in the same way on most boards, add
comments to the Kconfig help text to reflect this, and give them defaults
matching their typical usage.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 29 Nov 2014 22:54:25 +0000 (23:54 +0100)]
sunxi: axp221: Add axp223 support
The axp223 appears to be the same as the axp221, except that it uses the
rsb to communicate rather then the p2wi. At least all the registers we use
are 100% the same.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 29 Nov 2014 12:38:35 +0000 (13:38 +0100)]
sunxi: Add support for the rsb (Reduced Serial Bus)
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.
This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Axel Lin [Sat, 20 Dec 2014 03:41:25 +0000 (11:41 +0800)]
mmc: sunxi: Fix misuse of gpio_direction_input()
It does not make sense to make gpio_direction_input() return the gpio input
status. The return value of gpio_direction_input() is inconsistent if
CONFIG_DM_GPIO is defined.
And we don't need to call gpio_direction_input() int sunxi_mmc_getcd().
Just init the gpio once in mmc_resource_init() is enough.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Chen-Yu Tsai [Tue, 9 Dec 2014 08:56:53 +0000 (16:56 +0800)]
sun6i: Add new board Merrii Hummingbird A31
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Sun, 7 Dec 2014 19:55:10 +0000 (20:55 +0100)]
sunxi: mmc: Properly setup mod-clk and clock sampling phases
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.
The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).
For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.
This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Tue, 2 Dec 2014 09:29:42 +0000 (10:29 +0100)]
sun6i: Update Colombus defconfig settings
The Colombus defconfig settings are missing a number of settings for recently
added features, because we did not know exactly how things were hooked up.
Maxime Ripard has run various tests to get us the necessary details, this
commit updates the defconfig with this info.
This commit also updates the dram clk and zq values with values verified
by Maxime to be the ones used by the original firmware for this board.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 16 Nov 2014 10:33:56 +0000 (11:33 +0100)]
sun6i: Add new CSQ_CS908 board
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
Hans de Goede [Sat, 15 Nov 2014 18:46:39 +0000 (19:46 +0100)]
sun6i: Make dram clk and zq value Kconfig options
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.
Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Bin Meng [Tue, 6 Jan 2015 14:14:21 +0000 (22:14 +0800)]
x86: Make chromebook_link the default board for coreboot
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:19 +0000 (22:14 +0800)]
x86: Move CONFIG_SYS_CAR_xxx to Kconfig
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:18 +0000 (22:14 +0800)]
x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:17 +0000 (22:14 +0800)]
x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want to make these two options configurable
so that we can easily change them during 'make menuconfig' so that
the generated U-Boot image for coreboot is board configuration aware.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:14 +0000 (22:14 +0800)]
x86: Allow a hardcoded TSC frequency provided by Kconfig
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
Normally the bypass should be turned on in a simulation environment
like qemu.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:13 +0000 (22:14 +0800)]
x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:14 +0000 (16:18 -0700)]
x86: ivybridge: Update microcode early in boot
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.
For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.
Simon Glass [Thu, 1 Jan 2015 23:18:11 +0000 (16:18 -0700)]
x86: Commit the current MTRRs before relocation
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.
Simon Glass [Thu, 1 Jan 2015 23:18:09 +0000 (16:18 -0700)]
x86: board_f: Adjust x86 boot order for performance
For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.
Simon Glass [Thu, 1 Jan 2015 23:18:07 +0000 (16:18 -0700)]
x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded
code.
These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).
Simon Glass [Thu, 1 Jan 2015 23:18:06 +0000 (16:18 -0700)]
x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Simon Glass [Thu, 1 Jan 2015 23:18:02 +0000 (16:18 -0700)]
x86: ivybridge: Only run the Video BIOS when video is enabled
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.
We could add a command to run the video BIOS later when needed, but this is
not considered at present.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Wed, 31 Dec 2014 08:05:14 +0000 (16:05 +0800)]
x86: crownbay: Add pci devices in the dts file
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:13 +0000 (16:05 +0800)]
x86: Use ePAPR defined properties for x86-uart
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:12 +0000 (16:05 +0800)]
serial: ns16550: Support ns16550 compatible pci uart devices
There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.
Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:11 +0000 (16:05 +0800)]
fdt: Add several apis to decode pci device node
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
Bin Meng [Tue, 30 Dec 2014 08:02:05 +0000 (16:02 +0800)]
x86: Simplify the fsp hob access functions
Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 30 Dec 2014 14:53:21 +0000 (22:53 +0800)]
pci: Make pci apis usable before relocation
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.
Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 30 Dec 2014 14:53:20 +0000 (22:53 +0800)]
x86: Support pci bus scan in the early phase
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log