Simon Glass [Mon, 13 Jun 2016 05:30:22 +0000 (23:30 -0600)]
dm: mmc: Add a way to use driver model for MMC operations
The driver model conversion for MMC has moved in small steps. The first step
was to have an MMC device (CONFIG_DM_MMC). The second was to use a child
block device (CONFIG_BLK). The final one is to use driver model for MMC
operations (CONFIG_DM_MMC_OP). Add support for this.
The immediate priority is to make all boards that use DM_MMC also use those
other two options. This will allow them to be removed.
Simon Glass [Mon, 13 Jun 2016 05:30:14 +0000 (23:30 -0600)]
rockchip: Use 'select' instead of defaults in Kconfig
Rockchip uses driver model for all subsystems. Specify this in the arm
Kconfig rather than as defaults in the Rockchip Kconfig. This means that
boards cannot turn these options off, which seems correct.
Andre Przywara [Fri, 8 Jul 2016 14:25:23 +0000 (15:25 +0100)]
doc: ARMv8: add README.pine64
Since we lack information about the DRAM initialization for the
Allwinner A64 SoC, booting any A64 based board like the Pine64 is a bit
involved at the moment.
Add a README file to explain the process.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Move to board/sunxi/ from doc/] Signed-off-by: Tom Rini <trini@konsulko.com>
Mingkai Hu [Thu, 7 Jul 2016 04:22:12 +0000 (12:22 +0800)]
armv8: Enable CPUECTLR.SMPEN for coherency
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
test/py: support 'memstart =' in u_boot_utils.find_ram_base()
Some archs like MIPS or PPC have a different 'bdinfo' output
than ARM regarding the memory configuration. Also support
'memstart = 0x*' in u_boot_utils.find_ram_base() to make
all tests requiring the RAM base working on those archs.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Wed, 6 Jul 2016 16:34:30 +0000 (10:34 -0600)]
test/py: strip VT100 codes from match buffer
Prior to this patch, any VT100 codes emitted by U-Boot are considered part
of a command's output, which often causes tests to fail. For example,
test_env_echo_exists executes printenv, and then considers any text on a
line before an = sign as a valid U-Boot environment variable name. This
includes any VT100 codes emitted. When the test later attempts to use that
variable, the name would be invalid since it includes the VT100 codes.
Solve this by stripping VT100 codes from the match buffer, so they are
never seen by higher level test code.
The codes are still logged unmodified, so that users can expect U-Boot's
exact output without interference. This does clutter the log file a bit.
However, it allows users to see exactly what U-Boot emitted rather than a
modified version, which hopefully is better for debugging. It's also much
simpler to implement, since logging happens as soon as text is received,
and so stripping the VT100 codes from the log would require handling
reception and stripping of partial VT100 codes.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Alexander Graf [Tue, 5 Jul 2016 18:37:17 +0000 (20:37 +0200)]
arm: Fix setjmp (again)
Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp
code path with thumv1. Unfortunately it missed a constraint that the adr
instruction can only refer to 4 byte aligned offsets.
So this patch adds the required alignment hooks to make compilation
work again even when setjmp doesn't happen to be 4 byte aligned.
Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Tom Rini <trini@konsulko.com>
Andre Przywara [Fri, 8 Jul 2016 14:18:35 +0000 (15:18 +0100)]
SPL: tiny-printf: avoid any BSS usage
As printf calls may be executed quite early, we should avoid using any
BSS stored variables, since some boards put BSS in DRAM, which may not
have been initialised yet.
Explicitly mark those "static global" variables as belonging to the
.data section, to keep tiny-printf clear of any BSS usage.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Stephen Warren [Wed, 6 Jul 2016 15:04:08 +0000 (09:04 -0600)]
test/py: fix CONFIG_ tests
Some CONFIG_ variables were recently renamed, but test/py wasn't updated
to match. This causes some tests to be skipped. Fix test/py so the tests
are run.
Fixes: 11636258981a ("Rename reset to sysreset") Fixes: f1f9d4fac527 ("hush: complete renaming CONFIG_SYS_HUSH_PARSER to CONFIG_HUSH_PARSER") Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
York Sun [Wed, 6 Jul 2016 23:39:51 +0000 (16:39 -0700)]
powerpc: mpc85xx: kmp204x: Fix compiling error for usb errata
Commit 9262367 moves USB errata workaround into a C file. This
causes compiling error for kmcoge4 and kmlion1. To enable the
errata workaround, define CONFIG_USB_EHCI_FSL in common header.
Signed-off-by: York Sun <york.sun@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Ed Swarthout <Ed.Swarthout@nxp.com> Cc: Sriram Dash <sriram.dash@nxp.com> Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
net: rtl8169: Fix return value for rtl_send_common
Return value of rtl_send_common propogates unmodified all the way
up to eth_send and further to API consumer if CONFIG_API is enabled.
Previously rtl_send_common returned number of bytes sent on success
which was erroneouly detected as error condition by API consumers
that checked for operation success by comparing return value with 0.
Switch rtl_send_common to use common convention: return 0 on success
and negative value for failure.
Cc: Stephen Warren <swarren@nvidia.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alexey Brodkin [Mon, 27 Jun 2016 10:17:51 +0000 (13:17 +0300)]
net: designware: Make driver independent from DM_GPIO again
Commit 90b7fc924adf "net: designware: support phy reset device-tree
bindings" made DW GMAC driver dependent on DM_GPIO by unconditional
usage of purely DM_GPIO stuff like:
* dm_gpio_XXX()
* gpio_request_by_name()
But since that driver as of today might be easily used without
DM_GPIO (that's the case for Synopsys AXS10x boards) we're
shielding all DM_GPIO things by ifdefs.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Sun, 8 May 2016 22:55:22 +0000 (16:55 -0600)]
fdt: Drop some unused compatible strings
We have driver-model drivers for some of these now, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sun, 8 May 2016 22:55:20 +0000 (16:55 -0600)]
video: tegra: Move to using simple-panel and pwm-backlight
We have standard drivers for panels and backlights which can do most of the
work for us. Move the tegra20 LCD driver over to use those instead of custom
code.
This patch includes device tree changes for the nvidia boards. I have only
been able to test seaboard. If this patch is applied, these boards will
also need to be synced with the kernel, and updated to use display-timings:
- colibri
- medcom-wide
- paz00
- tec
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sun, 8 May 2016 22:55:19 +0000 (16:55 -0600)]
tegra: dts: Sync tegra20 device tree files with Linux
Sync everything except the display panel, which will come in a future patch.
One USB port is left disabled since we don't want to support it in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sun, 8 May 2016 22:55:18 +0000 (16:55 -0600)]
errno: Allow errno_str() to be used without CONFIG_ERRNO_STR
The pmic framework uses errno_str() and this requires board that use it to
enable CONFIG_ERRNO_STR to avoid a build error. Update the header to provide
a NULL error message when CONFIG_ERRNO_STR is not defined, and fix the build
error.
This will show as "(null)" when U-Boot prints it.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sun, 8 May 2016 22:55:17 +0000 (16:55 -0600)]
errno: Add copyright header and header guard
Bring in a copyright for this file from cmd/pmic.c since this file was
submitted by the same author at around the same time. Also fix the missing
header guard.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Fri, 24 Jun 2016 14:36:04 +0000 (08:36 -0600)]
pci: tegra: actually program REFCLK_CFG* on recent SoCs
On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.
For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Tue, 21 Jun 2016 18:47:51 +0000 (12:47 -0600)]
pci: tegra: correctly program PADS_REFCLK registers
The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.
For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Marek Vasut [Tue, 5 Jul 2016 15:40:27 +0000 (17:40 +0200)]
powerpc: mpc85xx: Do not build errata command in SPL
The errata command is useless in SPL, so don't build it. This fixes
multiple build failures on PowerPC.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
Hans de Goede [Sun, 3 Jul 2016 18:22:05 +0000 (20:22 +0200)]
usb: dm: Make "usb info" use usb_for_each_root_dev()
The old dm "usb info" implementation has several issues:
1) NULL pointer deref when a bus has no children
2) Not showing usb devices on busses without an emulated root-hub (otg host)
3) Attempting to show devices on inactive busses
4) "usb info" Would cause some hosts to get re-probed something which only
"usb reset" should do
TL;DR: proper iterating over usb bus root devs is hard, use the helper
for it.
Reported-by: Bernhard Nortmann <bernhard.nortmann@web.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Sun, 3 Jul 2016 18:22:04 +0000 (20:22 +0200)]
usb: dm: Add a usb_for_each_root_dev() helper function
Iterating over usb-root devs and doing something for all of them is
a bit tricky with dm, factor out the proven usb_show_tree() for this
into a helper function.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Currently on attempt to use global_data.h in an assembly file following
will happen:
-------------------->8-----------------
./arch/arc/include/asm/global_data.h: Assembler messages:
./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{'
./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}'
scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed
-------------------->8-----------------
In this change we disable struct arch_global_data in ASM which fixes
the issue above.
Alexey Brodkin [Thu, 16 Jun 2016 08:55:00 +0000 (10:55 +0200)]
arc: Use "-mcpu=archs" instead of deprecated "-marchs" for ARC HS
Newer ARC toolchains don't support "-marchs" option any longer.
Instead "-mcpu=archs" should be used. What's also important older
toiolchains that support ARC HS cores will also happily accept
"-mcpu=archs" so that's a very safe move.
Quentin Schulz [Fri, 24 Jun 2016 12:33:35 +0000 (14:33 +0200)]
sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)
The Parrot Board is an evaluation board with an Allwinner R16 (assumed
to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host
and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2
controllable buttons, an LVDS port with separated backlight and
capacitive touch panel ports, an audio/microphone jack, a camera CSI
port, 2 sets of 22 GPIOs and an accelerometer.
The DTS file is identical to the one submitted to the upstream kernel.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Olliver Schinagl [Mon, 13 Jun 2016 16:13:07 +0000 (18:13 +0200)]
sunxi: Add missing boot_media fields in the SPL header
Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid
code corruption") Added defines for MMC0 and SPI as boot identification.
After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected
values have been confirmed and added to spl.h
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Masahiro Yamada [Mon, 27 Jun 2016 07:23:02 +0000 (16:23 +0900)]
autoboot: rename abortboot_{keyed, normal} to __abortboot
Because abortboot_keyed() and abortboot_normal() are not compiled
at the same time, we can rename both of them to __abortboot().
This allows to drop #ifdef from the caller.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
Masahiro Yamada [Mon, 27 Jun 2016 07:23:01 +0000 (16:23 +0900)]
autoboot: remove CONFIG_ZERO_BOOTDELAY_CHECK
As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2
means the autoboot with no delay, with no abort check even if
CONFIG_ZERO_BOOTDELAY_CHECK is defined.
To sum up, the autoboot behaves as follows:
[1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y
autoboot with no delay, but you can abort it by key input
[2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
autoboot with no delay, with no check for abort
[3] CONFIG_BOOTDELAY=-1
disable autoboot
[4] CONFIG_BOOTDELAY=-2
autoboot with no delay, with no check for abort
As you notice, [2] and [4] come to the same result, which means we
do not need CONFIG_ZERO_BOOTDELAY_CHECK. We can control all the
cases only by CONFIG_BOOTDELAY, like this:
[1] CONFIG_BOOTDELAY=0
autoboot with no delay, but you can abort it by key input
[2] CONFIG_BOOTDELAY=-1
disable autoboot
[3] CONFIG_BOOTDELAY=-2
autoboot with no delay, with no check for abort
This commit converts the logic as follow:
CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
--> CONFIG_BOOTDELAY=-2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Christian Riesch <christian.riesch@omicronenergy.com> Acked-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Align the name of the defconfig file for high-security (HS) device variants
from the AM43xx family of SoCs with the corresponding name used for the
general purpose devices. This allows for easier cross-association of those
files and also provides room to grow from an HS device part number
perspective.
Furthermore, update and cleanup associated MAINTAINERS file.
Masahiro Yamada [Wed, 29 Jun 2016 10:39:03 +0000 (19:39 +0900)]
ARM: uniphier: add external IRQ setup code
I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.
Masahiro Yamada [Wed, 29 Jun 2016 10:38:59 +0000 (19:38 +0900)]
pinctrl: uniphier: support pin configuration for dedicated pins
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.
Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function. The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.
Masahiro Yamada [Wed, 29 Jun 2016 10:38:58 +0000 (19:38 +0900)]
pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20
PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.
However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development. Split it into two dedicated drivers.
Masahiro Yamada [Wed, 29 Jun 2016 10:38:57 +0000 (19:38 +0900)]
pinctrl: uniphier: allow to have pinctrl node under syscon node
Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node. This commit allows to migrate to
the new DT structure.
Bin Meng [Wed, 22 Jun 2016 09:30:03 +0000 (02:30 -0700)]
x86: coreboot: Remove the dummy pch driver
There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Abhimanyu Saini [Tue, 14 Jun 2016 07:48:31 +0000 (13:18 +0530)]
armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs
Currently layescape SoCs are not using cpu nodes. So removing
them in favour of compatibly with similar SoCs that
have different cores like LS2080A and LS2088A.
This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Fan [Wed, 15 Jun 2016 02:53:02 +0000 (10:53 +0800)]
mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Ye Li [Wed, 15 Jun 2016 02:53:01 +0000 (10:53 +0800)]
fsl_esdhc: Update clock enable bits for USDHC
The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
external card and reinitialize it.
So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Fan [Wed, 15 Jun 2016 02:53:00 +0000 (10:53 +0800)]
mmc: fsl: reset to normal boot mode when eMMC fast boot
When booting in eMMC fast boot, MMC host does not exit from
boot mode after bootrom loading image. So the first command
'CMD0' sent in uboot will pull down the CMD line to low and
cause errors.
This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.
Also clear DLL_CTRL delay line settings at USDHC initialization
to eliminate the pre-settings from boot rom.
Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
SoCs supports loading U-Boot from different medias to DRAM, such as
i.MX6/7 supports loading U-Boot to DRAM from sd/emmc/nand/qspi/spi/sata
and etc. For i.MX, imximage will generate different IVT headers according
to boot medias.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Francois Retief <fgretief@spaceteq.co.za> Cc: Tom Rini <trini@konsulko.com>
Steve Rae [Tue, 7 Jun 2016 18:19:38 +0000 (11:19 -0700)]
fastboot: sparse: implement reserve()
In order to process the CHUNK_TYPE_DONT_CARE properly, there is
a requirement to be able to 'reserve' a specified number of blocks
in the storage media. Because of the special handling of "bad blocks"
in NAND devices, this is implemented in a storage abstraction function.
Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
While retaining the storage abstraction feature, this is the second
set of the changes required to resync with the
cmd_flash_mmc_sparse_img()
in the file
aboot.c
from
https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1
While retaining the storage abstraction feature, this is the first
set of the changes required to resync with the
cmd_flash_mmc_sparse_img()
in the file
aboot.c
from
https://us.codeaurora.org/cgit/quic/la/kernel/lk/plain/app/aboot/aboot.c?h=LE.BR.1.2.1
Jaehoon Chung [Fri, 13 May 2016 14:37:44 +0000 (23:37 +0900)]
mmc: dw_mmc: fix the wrong AND operation
These condition checking are wrong.
Original Author's intention might be "&" instead of "&&".
It can know whether receive or transmit data request with
BIT[4]/BIT[5] of RINTSTS register.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
projects / u-boot / log