Jagan Teki [Mon, 5 Dec 2016 23:00:53 +0000 (00:00 +0100)]
icorem6: Use CONFIG_DM_ETH support
Use CONFIG_DM_ETH and remove board_eth_init code
from board files.
Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 5 Dec 2016 23:00:50 +0000 (00:00 +0100)]
net: fec_mxc: Driver cleanups
- Remove exctra space
- Add space
- Add tab space
- Fix single line comments quotes
- Fix 'CHECK: Avoid CamelCase'
- Fix 'CHECK: Alignment should match open parenthesis'
- Fix 'WARNING: line over 80 characters'
- Re-arrage header include files
Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 5 Dec 2016 23:00:49 +0000 (00:00 +0100)]
net: fec_mxc: Convert into driver model
This patch add driver model support for fec_mxc driver.
Cc: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Jagan Teki [Mon, 5 Dec 2016 23:00:48 +0000 (00:00 +0100)]
net: fec_mxc: Remove unneeded eth_device arg from fec_get_hwaddr
fec_get_hwaddr never used eth_device argument, hence removed.
Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Patrick Bruenn [Fri, 4 Nov 2016 10:57:02 +0000 (11:57 +0100)]
arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC
Add CX9020 board based on mx53loco.
Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse
serial_mxc with DTE and prepare for device tree migration of other
functions and imx53 devices.
The CX9020 differs from i.MX53 Quick Start Board by:
- use uart2 instead of uart1
- DVI-D connector instead of VGA
- no audio
- CCAT FPGA connected to emi
- enable rtc
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
CPU: Freescale i.MX6SLL rev1.0 at 792MHz
CPU: Commercial temperature grade (0C to 95C)Reset cause: POR
Model: Freescale i.MX6SLL EVK Board
Board: MX6SLL EVK
DRAM: 2 GiB
i2c bus 0 at 35258368, no gpio pinctrl state.
PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
u-boot allows modifying a device tree after it is loaded into
memory. Add fdt_fixup hook in u-boot environment which can
facilitate such modifications.
Here we treat SOM similar to SOC, so we place it inside arch/arm/mach-*
directory and make it possible to reuse initialization code (i.e. DDR,
eMMC init) for all boards that use it.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Max Krummenacher [Wed, 30 Nov 2016 18:43:09 +0000 (19:43 +0100)]
arm: imx: initial support for colibri imx6
This adds board support for the Toradex module family Colibri iMX6.
The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both
with a version for commercial and industrial temperature range.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Max Krummenacher [Wed, 30 Nov 2016 18:43:08 +0000 (19:43 +0100)]
arm: imx: initial support for apalis imx6
This adds board support for the Toradex module family Apalis iMX6.
The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with
commercial and industrial temperature range.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Stefan Agner [Wed, 30 Nov 2016 21:41:57 +0000 (13:41 -0800)]
ARM: dts: vf: Fix warning about missing reg property
Add proper reg values for the two AIPS bus nodes. This avoids this
two warnings:
Node /soc/aips-bus@40000000 has a unit name, but no reg property
Node /soc/aips-bus@40080000 has a unit name, but no reg property
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Wed, 30 Nov 2016 21:41:56 +0000 (13:41 -0800)]
colibri_vf: use same NAND clock as Linux uses
Currently a divider of 6 has been used, leading to following NAND
Flash Controller (NFC) clocks:
VF61: 27.7 MHz (166.7MHz bus clock)
VF50: 22 MHz (132MHz bus clock)
The NAND Flash Memory used on VF50 allows to use clock speed of
up to 33MHz, while the Flash Memory of VF61 allows 50MHz. We can
use the same divider of 4 on both modules to configure the maximal
possible clock speeds:
VF61: 41.7 MHz
VF50: 33 MHz
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Wed, 30 Nov 2016 21:41:55 +0000 (13:41 -0800)]
colibri_vf: cleanup USB clock initialization
Use the same preprocessor define to enable clocks as we use to
enable the driver. Make sure that the necessary PLL's are on
(they get enabled by boot ROM by default, so this is more for
completness).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Wed, 30 Nov 2016 21:41:54 +0000 (13:41 -0800)]
colibri_vf: use device-tree for MTD partitions
Use device-tree fixup to communicate the MTD partitions to the
kernel. U-Boot's mtdparts environment variable will be used as
partition source for the device-tree based partition table too.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Wed, 30 Nov 2016 21:41:53 +0000 (13:41 -0800)]
toradex: allow custom fdt board setup in board file
The config block support currently uses the ft_board_setup function
to patch the device tree with config block information. However, this
does not allow to patch the device tree with board specific information.
Rename the common setup function to ft_common_board_setup and use the
call it from the board files directly.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
arm64: mvebu: Add L3 cache flush functionality to A8K family
Add missing L3 cache flush functionality which absence prevents
Linux kernel from normal boot in case the L3 cache is enabled
by ATF.
The L3 cache is named the "last level" cache in order to keep
the terminology similar to the ATF code.
This cache should not be disabled by u-boot since the Linux
kernel cannot activate it, so it is activates at ATF stage.
However the cache flush is required for preventing data corruption
after disabling the MMU and the data cache before passing control
to the loaded Linux image.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
arm64: mvebu: pinctrl: Add pin control driver for A8K family
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
arm64: mvebu: Modify the A8K SPI and I2C config in DTS
Align the Armada-8040-db and Armada-7040-db SPI and I2C
DTS settings with latest DB settings:
- 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO)
- 8040-db: disable cps_i2c0 on CP1
- 8040-db: enable spi1 on CP1 (the new location of the boot flash)
The spi1 on CP1 is aliased as spi0 since this is the way
the driver enumerates it.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Jyri Sarha [Fri, 9 Dec 2016 10:29:13 +0000 (12:29 +0200)]
arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evm
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2,
and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With
the default values LCDC suffers from DMA FIFO underflows and frame
synchronization lost errors. The initialization values are the highest
that work flawlessly when heavy memory load is generated by CPU. 32bpp
colors were used in the test. On BBB the video mode used 110MHz pixel
clock. The mode supported by the panel of am335x-evm uses 30MHz pixel
clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 7 Dec 2016 16:20:40 +0000 (11:20 -0500)]
travis-ci: Switch to building QEMU
First, there are a number of features in newer QEMU that will allow us
to test a wider range of platforms, so we want to use at least v2.8.0.
Second, making use of a PPA for QEMU fails from time to time. So we
change to checking out and building a copy of QEMU when we know that we
are going to use test.py and need QEMU to be installed. This adds
around 4 minutes per test.py job that we run.
Michal Simek [Tue, 6 Dec 2016 16:17:01 +0000 (17:17 +0100)]
tools: mkimage: Use fstat instead of stat to avoid malicious hacks
The patch is fixing:
"tools: mkimage: Check if file is regular file"
(sha1: 56c7e8015509312240b1ee15f2ff74510939a45d)
which contains two issues reported by Coverity
Unchecked return value from stat and incorrect calling sequence where
attack can happen between calling stat and fopen.
Using pair in opposite order (fopen and fstat) is fixing this issue
because fstat is using the same file descriptor (FILE *).
Also fixing issue with:
"tools: mkimage: Add support for initialization table for Zynq and
ZynqMP" (sha1: 3b6460809c2a28360029c1c48247648fac4455c9)
where file wasn't checked that it is regular file.
Reported-by: Coverity (CID: 154711, 154712) Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Currently we let U-Boot find a spot at the end of DRAM at runtime, this
forces us to build an OPTEE image based on the size of DRAM for an EVM.
Add a default address that works across all current AM57xx EVMs.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Currently we let U-Boot find a spot at the end of DRAM at runtime, this
forces us to build an OPTEE image based on the size of DRAM for an EVM.
Add a default address that works across all current DRA7xx EVMs.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Mon, 5 Dec 2016 18:15:21 +0000 (19:15 +0100)]
davinci: omapl138_lcdk: fix bad NAND ECC config
The configuration used to error correction was not in line with what
linux and the ROM code is using. Fix it by using the correct
configuration. Now u-boot and the SPL are able to read correctly
anything written by them.
Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Yehuda Yitschak [Thu, 1 Dec 2016 15:14:18 +0000 (17:14 +0200)]
cmd: pci: add option to parse and display BAR information
Currently the PCI command only allows to see the BAR register
values but not the size and actual base address.
This little extension parses the BAR registers and displays
the base, size and type of each BAR.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 30 Nov 2016 22:30:50 +0000 (15:30 -0700)]
spl: Add a name to the SPL load-image methods
It is useful to name each method so that we can print out this name when
using the method. Currently this happens using a separate function. In
preparation for unifying this, add a name to each method.
The name is only available if we have libcommon support (i.e can use
printf()).
Keerthy [Wed, 30 Nov 2016 09:32:53 +0000 (15:02 +0530)]
am57xx: Set tps659038 PMIC GPIO7 pad mux value to POWERHOLD
The GPIO7 pad mux should be programmed to POWERHOLD value
as per board design. In cases where the PMIC is shut off the
mux is set to GPIO7 mode. So during initialization to be on the
safer side set the mode to POWERHOLD.
Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Patrick Delaunay [Tue, 22 Nov 2016 16:31:33 +0000 (17:31 +0100)]
arm: armv7: add us timer for bootstage
solve issue when bootstage is used with armV7 generic timer
first call of timer_get_boot_us() use the function get_timer()
before timer initialization (arch.timer_rate_hz = 0)
=> div by 0
Commit-notes
When I activate bootstage on ARMV7 architecture with platform
using the generic armv7 timer defined in file
./arch/arm/cpu/armv7m/timer.c
I have a issue because gd->arch.timer_rate_hz = 0
For me the get_timer() function should not used before timer_init
(which initialize gd->arch.timer_rate_hz) at least for the ARMV7
timer.
But in the init sequence, the first bootstage fucntion is called
before timer_init and this function use the timer function.
For me it is a error in the generic init sequence :
mark_bootstage is called before timer_init.
To solve the issue for all the paltform, we can move timer_init()
call just before mark_bootstage() in this array...
It should be ok for ARMV7 but I don't sure for other platform
impacted
- the other ARM platform or ARMV7 wich don't use generic timer
- MIPS BLACKFIN NDS32 or SPARC
and I don't sure of impact for other function called
(board_early_init_f for example....)
=> This patch solve issue only in timer armv7
get_boot_us() can be called everytime without div by 0 issue
(gd->arch.timer_rate_hz is not used)
END
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
Alex [Tue, 22 Nov 2016 18:55:13 +0000 (10:55 -0800)]
net/phy/vitesse: Rework RGMII skew configuration for VSC8601
The VSC8601 config tried to add an RGMII skew based on #defines that
no config defines. That's quite an ugly way to do it. Since the skew
is only needed on RGMII interfaces, check the interface mode at
runtime, and apply the settings accordingly.
Tested on custom board with AM3352 SOC and VSC801 PHY.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch now uses the ALLOC_CACHE_ALIGN_BUFFER() macro to allocate the
buffers on a cache aligned boundary. This fixes all warnings seen on the
Armada XP platform.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ted Chen <tedchen@realtek.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
shaohui xie [Tue, 15 Nov 2016 06:36:47 +0000 (14:36 +0800)]
net: fman: fix 2.5G SGMII settings
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: phy: realtek: Only force master mode on rtl8211b/c
Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY")
added the define to force the PHY into master mode. Unfortunatly this is
an all or nothing switch. So it applies to either all PHY's or no PHY's.
The bug that define tried to solve was a buggy PLL in the RTL8211C only.
The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was
replaced with an RTL8211E. With this define however, both lime2 boards
are either forced to master mode or not. We could of course have a
binary for each board, but the following patch fixes this by adding a
'quirk' to the flags to the rtl8211b and rtl8211c only. It is now
possible to force master mode, but only have it apply to the rtl8211b
and rtl8211c.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Mon, 14 Nov 2016 14:08:42 +0000 (15:08 +0100)]
net: phy: micrel: Fix error handling
Fix the following error, the $ret variable handling must
be part of the loop, while due to the missing parenthesis
it was not.
drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’:
drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’:
drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation]
for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
^~~
drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’
if (ret)
^~
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michal Simek [Thu, 8 Dec 2016 09:25:44 +0000 (10:25 +0100)]
net: xilinx: Use mdio_register_seq() to support multiple instances
axi_emac, emaclite and gem have the same issue with registering
multiple instances with mdio busses. mdio bus name has to be uniq but
drivers are setting up only one name for all.
Use mdio_register_seq() and pass dev->seq number to allow multiple
mdio instances registration.
Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: u-boot
Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
projects / u-boot / log