net: fix wrong initialization in davinci-emac driver
emac module of the davinci platform supports only 8 tx and 8
rx channels (total 16). emac driver for davinci platform,
however, while doing initialization of the dma descriptor
head pointers, wrongly initializes the 16 head pointers
(instead of 8) for tx dma and 16 head pointers (insted of 8)
for rx dma, which is wrong. The result is, that this register
initilization spills over the other registers which was not
intended and is undesirable. This patch fixes this problem.
Signed-off-by: Vishwas Srivastava <vishu.kernel@gmail.com> CC: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
Simon Glass [Sat, 30 Jan 2016 22:45:19 +0000 (15:45 -0700)]
rockchip: Drop old CONFIG_VIDEO_ROTATION option
The option was renamed to CONFIG_CONSOLE_ROTATION and Rockchip boards
were not updated. However this option is is not needed by default for
Rockchip since we don't need a rotated console for current boards. So just
remove the old option.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sat, 30 Jan 2016 22:45:14 +0000 (15:45 -0700)]
microblaze: Correct build error in eth-uclass.c
This fixes the following error when building microblaze-generic:
net/eth-uclass.c: In function 'eth_post_probe':
net/eth-uclass.c:466:18: error: 'gd' undeclared (first use in this function)
ops->start += gd->reloc_off;
Fixes: db9391e1 ("net: Move driver-model code into its own file") Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Bin Meng [Tue, 2 Feb 2016 13:58:09 +0000 (05:58 -0800)]
x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c
which is only built for legacy PCI. Also per checkpatch.pl warning,
DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 2 Feb 2016 13:58:02 +0000 (05:58 -0800)]
x86: quark: Use Quark's own PCI config APIs
There are still two places in Quark's MRC codes that use the generic
legacy PCI APIs, but as we are phasing out these legacy APIs, switch
to use Quark's own PCI config routines.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:55 +0000 (01:40 -0800)]
x86: tnc: Remove IGD and SDVO devices from driver model
With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disable bit, IGD and SDVO devices will disappear in the
PCI configuration space. This however creates an inconsistent state
from a driver model PCI controller point of view, as these two PCI
devices are still attached to its parent's child device list as
maintained by the driver model. Some driver model PCI APIs like
dm_pci_find_class() used in the vesa_fb driver, are referring to
the list to speed up the finding process instead of re-enumerating
the whole PCI bus, so it gets the stale cached data which is wrong.
To fix this, manually remove these two devices.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:51 +0000 (01:40 -0800)]
x86: irq: Move irq_router to a per driver priv
At present irq_router is declared as a static struct irq_router in
arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
to move it to a per driver priv. Adjust existing APIs to accept an
additional parameter of irq_router's udevice.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:47 +0000 (01:40 -0800)]
x86: ich6_gpio: Convert to use proper DM API
At present this GPIO driver still uses the legacy PCI API. Now that
we have proper PCH drivers we can use those to obtain the information
we need. While the device tree has nodes for the GPIO peripheral it is
not in the right place. It should be on the PCI bus as a sub-peripheral
of the PCH device.
Update the device tree files to show the GPIO controller within the PCH,
so that PCI access works as expected. This also adds '#address-cells'
and '#size-cells' to the PCH node.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:45 +0000 (01:40 -0800)]
dm: pch: Add get_io_base op
On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:43 +0000 (01:40 -0800)]
dm: pch: Add get_gpio_base op
x86 GPIO registers are accessed via I/O port whose base address is
configured in a PCI configuration register on the PCH device. Add
an op get_gpio_base to get the GPIO base address from PCH.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:41 +0000 (01:40 -0800)]
dm: pch: Remove pch_get_version op
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:38 +0000 (01:40 -0800)]
spi: ich: Change PCHV_ to ICHV_
The ICH SPI controller supports two variants, one of which is ICH7
compatible and the other is ICH9 compatible. Change 'pch_version'
to 'ich_version' to better match its original name.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:37 +0000 (01:40 -0800)]
spi: ich: Use compatible strings to distinguish controller version
At present ich spi driver gets the controller version information via
pch, but this can be simply retrieved via spi node's compatible string.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 1 Feb 2016 09:40:36 +0000 (01:40 -0800)]
spi: ich: Some clean up
This cleans up the ich spi driver a little bit:
- Remove struct ich_spi_slave that is not referenced anywhere
- Remove ending period in some comments
- Move struct ich_spi_platdata and struct ich_spi_priv to ich.h
- Add #ifndef _ICH_H_ .. in ich.h
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
Stefan Roese [Mon, 18 Jan 2016 13:49:56 +0000 (14:49 +0100)]
x86: x86-common.h: Add CONFIG_BOOTDELAY
Without this CONFIG_BOOTDELAY, autobooting does not work at all. As
autoboot_command() from common/* will not get called. So lets define
CONFIG_BOOTDELAY, so that auto-booting works on x86.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Miao Yan <yanmiaobest@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Miao Yan <yanmiaobest@gmail.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
Stefan Roese [Thu, 28 Jan 2016 16:34:40 +0000 (17:34 +0100)]
autoboot.c: Fill env vars in process_fdt_options() only if TEXT_BASE is set
The x86 build target "efi-x86" has no TEXT_BASE configured. And with the
introduction of CONFIG_BOOTDELAY for x86, this function is now called
for this board as well. Resulting in compile errors for this target.
Without TEXT_BASE it makes no sense to fill these values. So lets only
configure the env variable if TEXT_BASE is defined.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Dinh Nguyen [Tue, 19 Jan 2016 15:16:21 +0000 (09:16 -0600)]
Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"
Apparently, the logic for the FPGA global bit is not universal between Gen5
and Gen10 devices is not the same. Disabling this bit, while applicable to
Gen10 devices, will break FPGA programming on Gen5 devices.
Frank Wang [Wed, 27 Jan 2016 20:39:40 +0000 (12:39 -0800)]
usb: gadget: dwc2_udc_otg: modified the check condition for max packet size of ep_in in high speed
In current high speed fastboot, fs_ep_in.wMaxPacketSize is configured 64 bytes
as default, as a result, it failed to match the size at initialization stage in
usb controller.
Actually, hardware can support less than or equal to 512 bytes in high speed mode,
so I changed the condition from '!=' to '>' to fix this issue.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Tested-by: Steve Rae <srae@broadcom.com>
Peng Fan [Thu, 28 Jan 2016 08:51:26 +0000 (16:51 +0800)]
imx: mx6: implement mmc_get_env_dev
Implement mmc_get_env_dev, devno can be got from smbr1 of SRC.
Introduce a weak function board_mmc_get_env_dev, different
boards can implement it according to different sdhc controllers
that used by the board.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Thu, 28 Jan 2016 08:51:25 +0000 (16:51 +0800)]
imx: mx7dsabresd: move mmc_get_env_devno to soc code
Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to
match the one in common/env_mmc.c.
Introduce a weak function board_mmc_get_env_dev. Different
boards can implement this according to sdhc controller which
is used by the board.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:51 +0000 (10:31 +0530)]
arm: vybrid: Drop enabling GPIO, SPI and UART in legacy mode
Remove the legacy way of enabling GPIO, SPI and UART on Vybrid
based boards since these driver's now only supports DT mode.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:50 +0000 (10:31 +0530)]
arm: vybrid: Update defconfig's
Let's go with pure DT solution for board's
based on NXP/Freescale Vybrid platform.
- Merge the DT defconfig with non-DT defconfig for Toradex
Colibri VF50/VF61 and drop the non-DT defconfig.
- Update the legacy defconfigs for NXP/Freescale VF610 Tower
Board with DT.
- Update the legacy defconfigs for Phytec phyCORE-vybrid
Board with DT.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:46 +0000 (10:31 +0530)]
arm: vybrid: Update the license string
Since SPDX license is already there, drop the full one.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bhuvanchandra DV [Wed, 27 Jan 2016 05:01:45 +0000 (10:31 +0530)]
arm: vybrid: Enable lpuart support
Add device tree node's for lpuart on Vybrid platform
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Ye Li [Tue, 26 Jan 2016 14:09:40 +0000 (22:09 +0800)]
imx: mx6sxsabresd: Add MCIMX28LCD display support
The i.MX6SX SABRESD board supports MCIMX28LCD (800x480x24) at LCDIF1
port, enable this display feature by adding relevant BSP codes
and configurations.
Ye Li [Tue, 26 Jan 2016 14:01:58 +0000 (22:01 +0800)]
imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation
The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
Bin Meng [Mon, 25 Jan 2016 03:38:32 +0000 (19:38 -0800)]
tools: mxsboot: Use more portable cpu_to_le32()
Currently when building mxsboot on certain machines it reports:
HOSTCC tools/mxsboot
tools/mxsboot.c: In function 'mx28_create_sd_image':
tools/mxsboot.c:560: warning: implicit declaration of function 'htole32'
/tmp/cchLIV6q.o: In function 'main':
mxsboot.c:(.text+0x6d8): undefined reference to 'htole32'
mxsboot.c:(.text+0x6e7): undefined reference to 'htole32'
mxsboot.c:(.text+0x6f6): undefined reference to 'htole32'
mxsboot.c:(.text+0x705): undefined reference to 'htole32'
mxsboot.c:(.text+0x711): undefined reference to 'htole32'
/tmp/cchLIV6q.o:mxsboot.c:(.text+0x71d): more undefined references to
'htole32' follow
collect2: ld returned 1 exit status
make[1]: *** [tools/mxsboot] Error 1
make: *** [tools] Error 2
The solution is to use cpu_to_le32() instead which is more portable,
just like other U-Boot tools [1] do.
Peter Robinson [Wed, 20 Jan 2016 10:00:16 +0000 (10:00 +0000)]
wandboard: fix variable name so PXE boot works
All boards that support PXE booting use the pxefile_addr_r variable. Standardise
wandboard with this variable as pxe_addr_r isn't used anywhere else so it's a
typo.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
Marek Vasut [Wed, 16 Dec 2015 14:40:07 +0000 (15:40 +0100)]
arm: imx6: Enable DDR calibration on Novena
Enable the DDR calibration functionality on Novena to deal with the
memory SoDIMM on this board. Moreover, tweak the initial DDR DRAM
parameters so the calibration works properly.
Marek Vasut [Wed, 16 Dec 2015 14:40:06 +0000 (15:40 +0100)]
arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.
Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Josh Wu [Tue, 24 Nov 2015 08:34:01 +0000 (16:34 +0800)]
atmel_nand: Add 32 bit ecc support for sama5d2 chip
Also if minimum ecc requirment is bigger then what we support, then just
use our maxium pmecc support.
But it is not safe, so we'll output a warning about this.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Josh Wu [Tue, 24 Nov 2015 08:34:00 +0000 (16:34 +0800)]
atmel_nand_ecc: update pmecc registers according to sama5d2 chip
1. add the pmecc register mapping for sama5d2.
2. add the pmecc error location register mapping for sama5d2.
3. add some new field that is different from old ip.
4. add sama5d2 pmecc ip version number.
Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Simon Glass [Mon, 1 Feb 2016 01:10:52 +0000 (18:10 -0700)]
tegra: Always build a boot image with the same filename
Adjust the Makefile to build u-boot-tegra.bin which contains a device tree
if OF_SEPARATE is enabled, and does not if not. This mirrors U-Boot's new
approach of using u-boot.bin to handle both cases.
Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 1 Feb 2016 01:10:51 +0000 (18:10 -0700)]
fdt: Build an SPL binary without device tree
At present u-boot-spl.bin holds the plain SPL binary without the device
tree. This is somewhat annoying since you need either u-boot-spl.bin or
u-boot-spl-dtb.bin depending on whether device tree is used.
Adjust the build such that u-boot-spl.bin includes a device tree
(if enabled), and the plain binary is in u-boot-spl-nodtb.bin. For now
u-boot-spl-dtb.bin remains the same.
Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 1 Feb 2016 01:10:50 +0000 (18:10 -0700)]
fdt: Build a U-Boot binary without device tree
At present u-boot.bin holds the plain U-Boot binary without the device tree.
This is somewhat annoying since you need either u-boot.bin or u-boot-dtb.bin
depending on whether device tree is used.
Adjust the build such that u-boot.bin includes a device tree (if enabled),
and the plain binary is in u-boot-nodtb.bin. For now u-boot-dtb.bin remains
the same.
This should be acceptable since:
- without OF_CONTROL, u-boot.bin still does not include a device tree
- with OF_CONTROL, u-boot-dtb.bin does not change
The main impact is build systems which are set up to use u-boot.bin as
the output file and then add a device tree. These will have to change to use
u-boot-nodtb.bin instead.
Adjust tegra rules so it continues to produce the correct files.
Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Fri, 29 Jan 2016 02:42:53 +0000 (11:42 +0900)]
mailmap: fix Ricardo's entry
Commit df48b23428e9 (".mailmap: Add all the mail alias for Ricardo
Ribalda") assigned two different proper names for the email address
"ricardo.ribalda@uam.es". This is a completely wrong usage as the
mailmap feature exists for coalescing together commits by the same
person whose name is sometimes spelled differently.
projects / u-boot / log