Peter Tyser [Mon, 5 Apr 2010 03:40:50 +0000 (22:40 -0500)]
cmd_ubi: Fix uninitialized variable warning
gcc 3.4.6 previously reported the following error on many MIPS boards
which utilize UBI:
cmd_ubi.c:193: warning: 'vol' might be used uninitialized in this function
The current code is structured such that 'vol' will never be used when
it is NULL anyway, but gcc isn't smart enough to figure this out.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Thomas Chou [Thu, 1 Apr 2010 03:15:05 +0000 (11:15 +0800)]
cfi_flash: reset timer in flash status check
This patch adds reset_timer() before the flash status check
waiting loop.
Since the timer is basically running asynchronous to the cfi
code, it is possible to call get_timer(0), then only a few
_SYSCLK_ cycles later an interrupt is generated. This causes
timeout even though much less time has elapsed. So the timer
period registers should be reset before get_timer(0) is
called.
There is similar usage in nand_base.c.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
Timur Tabi [Thu, 1 Apr 2010 15:49:42 +0000 (10:49 -0500)]
p2020ds: add alternate boot bank support using the ngPIXIS FPGA
The Freescale P2020DS board uses a new type of PIXIS FPGA, called the ngPIXIS.
The ngPIXIS has one distinct new feature: the values of the on-board switches
can be selectively overridden with shadow registers. This feature is used to
boot from a different NOR flash bank, instead of having a register dedicated
for this purpose. Because the ngPIXIS is so different from the previous PIXIS,
a new file is introduced: ngpixis.c.
Also update the P2020DS checkboard() function to use the new macros defined
in the header file.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Wed, 31 Mar 2010 22:44:13 +0000 (17:44 -0500)]
fsl: improve the PIXIS code and fix a few bugs
Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx
boards. This makes the code easier to read and more flexible.
Delete pixis.h, because none of the exported functions were actually being
used by any other file. Make all of the functions in pixis.c 'static'.
Remove "#include pixis.h" from every file that has it.
Remove some unnecessary #includes.
Make 'pixis_base' into a macro, so that we don't need to define it in every
function.
Add "while(1);" loops at the end of functions that reset the board, so that
execution doesn't continue while the reset is in progress.
Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where
appropriate.
Replace ulong/uint with their spelled-out equivalents. Remove unnecessary
typecasts, changing the types of some variables if necessary.
Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make
it easier for specific boards to support variations in the PIXIS registers
sets. No current boards appears to need this feature.
Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD.
Apparently, "pixis_reset altbank" has never worked on this board.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 31 Mar 2010 04:06:53 +0000 (23:06 -0500)]
85xx: Added various P1012/P1013/P1021/P1022 defines
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 30 Mar 2010 15:07:12 +0000 (10:07 -0500)]
ppc/8xxx: Delete PCI nodes from device tree if not configured
If the PCI controller wasn't configured or enabled delete from the
device tree (include its alias).
For the case that we didn't even configure u-boot with knowledge of
the controller we can use the fact that the pci_controller pointer
is NULL to delete the node in the device tree. We determine that
a controller was not setup (because of HW config) based on the fact
that cfg_addr wasn't setup.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Dave Liu [Fri, 5 Mar 2010 04:22:00 +0000 (12:22 +0800)]
fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.
Jerry Huang [Thu, 18 Mar 2010 20:57:06 +0000 (15:57 -0500)]
fsl_esdhc: Add function to reset the eSDHC controller
To support multiple block read command we must set abort or use auto
CMD12. If we booted from eSDHC controller neither of these are used
and thus we need to reset the controller to allow multiple block read
to function.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Previous code was failing when reading back the timer less than
400us after resetting it. This lead nand operations to incorrectly
timeout any now and then. Moreover, writing the load register isn't
immediately reflected in the value register. We must wait for a clock
edge, so read_timer now waits for the value to change at least once,
otherwise nand operation would timeout anyways (though less frequently).
Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
ep93xx timer: Simplified the timer code by eliminating clk_to_systicks() and
performing (almost) all manipulation of the timer structure in read_timer()
Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
NAND Flash, DDRs.
smc.h is a common place for the register description of Memory subsystem
of S5PC100.
Note: Only SROM related registers are descibed now.
Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Joonyoung Shim [Mon, 8 Feb 2010 13:00:52 +0000 (22:00 +0900)]
s3c64xx: Add ifdef at the S3C64XX only codes
The s3c6400.h file is only for S3C64XX cpu and the pheripheral port
address(0x70000000 - 0x7fffffff) exists at only S3C64XX cpu, so they
should be included by only S3C64XX cpu.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Scott McNutt [Thu, 1 Apr 2010 04:00:56 +0000 (00:00 -0400)]
nios2: Reload timer count in reset_timer()
When the timestamp is incremented via interrupt and the interrupt
period is greater than 1 msec, successive calls to get_timer() can
produce inaccurate timing since the interrupts are asynchronous
to the timing loop. For example, with an interrupt period of 10 msec
two successive calls to get_timer() could indicate an elapsed time
of 10 msec after only several hundred usecs -- depending on when
the next interrupt actually occurs. This behavior can cause
reliability issues with components such as CFI and NAND.
This can be remedied by calling reset_timer() prior to establishing
the base timestamp with get_timer(0), provided reset_timer()
resets the hardware timer (rather than simply resetting only the
timestamp). This has the effect of synchronizing the interrupts
(and the advance of the timestamp) with the timing loop.
Scott McNutt [Mon, 22 Mar 2010 01:24:43 +0000 (21:24 -0400)]
nios2: Fix outx/writex parameter order in io.h
The outx/writex macros were using writex(addr, val) rather than
the standard writex(val, addr), resulting in incompatibilty with
architecture independent components. This change set uses standard
parameter order.
Scott McNutt [Fri, 19 Mar 2010 23:03:28 +0000 (19:03 -0400)]
nios2: Move serial drivers to individual files in drivers/serial
The standard Altera UART & JTAG UART as well as the OpenCores
YANU driver are now in individual files in drivers/serial
rather than a single file uner cpu/nios2.
Felix Radensky [Tue, 30 Mar 2010 12:02:13 +0000 (15:02 +0300)]
doc: Fix ramdisk examples in doc/uImage.FIT/multi.its
The ramdisk sections in doc/uImage.FIT/multi.its lack
load address and entry point properties. Using examples
from this file will result in unbootable image, u-boot
will issue the following error messages:
Can't get ramdisk subimage load address!
Ramdisk image is corrupt or invalid
This patch adds missing properties to ramdisk sections.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Timur Tabi [Mon, 29 Mar 2010 17:51:07 +0000 (12:51 -0500)]
mpc86xx: set the DDR BATs after calculating true DDR size
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way. If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).
Currently we are limited to power of two sized DDR since we only use a
single bat. If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 26 Mar 2010 20:14:43 +0000 (15:14 -0500)]
85xx: Fix enabling of L1 cache parity on secondary cores
Use the same code between primary and secondary cores to init the
L1 cache. We were not enabling cache parity on the secondary cores.
Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks. Than enables the cache and
makes sure its enabled before continuing.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Stefan Roese [Mon, 29 Mar 2010 13:30:46 +0000 (15:30 +0200)]
ppc4xx: Fix problem with I2C bus >= 1 initialization
This patch fixes a problem introduced with patch eb5eb2b0
[ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C
base address to the "i2c" pointer inside of the controller loop.
Otherwise controller 0 is initialized multiple times instead of
initializing each I2C controller sequentially.
Tested on Katmai.
Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
Wolfgang Denk [Sat, 27 Mar 2010 22:37:46 +0000 (23:37 +0100)]
mkimage: fix Segmentation Fault when run without "-n name" option
The restructuring of the mkimage command in commit 89a4d6b1 ("tools:
mkimage: split code into core, default and FIT image specific")
introduced a bug that caused mkimage to segfault when run without
"-n name" option. Initialize the imagename entry to prevent that.
Thomas Chou [Fri, 26 Mar 2010 00:17:00 +0000 (08:17 +0800)]
cfi flash: add status polling method for amd flash
This patch adds status polling method to offer an alternative to
data toggle method for amd flash chips.
This patch is needed for nios2 cfi flash interface, where the bus
controller performs 4 bytes read cycles for a single byte read
instruction. The data toggle method can not detect chip busy
status correctly. So we have to poll DQ7, which will be inverted
when the chip is busy.
This feature is enabled with the config def,
CONFIG_SYS_CFI_FLASH_STATUS_POLL
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
TsiChung Liew [Tue, 16 Mar 2010 17:39:36 +0000 (12:39 -0500)]
ColdFire: Fix m54455EVB save environment bug
The ATMEL flash does not have buffer write feature. Assgined
buffer_size = 1, so that when there is a write to the flash
will not use buffer write function.
TsiChung Liew [Thu, 11 Mar 2010 00:24:07 +0000 (18:24 -0600)]
ColdFire: Misc update for M53017
Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add
CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update
DRAM control and SRAM control register setting. Update cache
setting where size does not write to proper region.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
TsiChung Liew [Wed, 10 Mar 2010 22:14:01 +0000 (16:14 -0600)]
ColdFire: M5271EVB DRAM Bring up issue
Fix proper portsize: The register for portsize is either 00b, 01b,
or 1xb. The value that previous assigned is 32d.
Fix DRAM bring up: insert asm("nop") for every DRAM register setup
TsiChung Liew [Thu, 11 Mar 2010 21:04:21 +0000 (15:04 -0600)]
ColdFire: Relocate vector table - mcf5445x
Newer ColdFire processors family boot from address 0 instead of
0xFFnn_nnnn. When the boot flash base chip select is set at new
location instead of 0, an un-predictable error will occur if
there is an vector being trigger and refer it to an invalid
address or the vector table handler is not existed at address
0.
Wolfgang Wegner [Fri, 30 Oct 2009 15:55:02 +0000 (16:55 +0100)]
add block write function to spartan3 slave serial load
Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 seconds
Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
Rupjyoti Sarmah [Wed, 24 Mar 2010 11:22:02 +0000 (16:52 +0530)]
ppc4xx fix unstable 440EPx bootstrap options
440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1.
This results in the PLLOUTB being greater than the CPU clock frequency
resulting unstable 440EPx operation resulting in various software hang
conditions.
This patch reprograms the FWDVA satisfying the requirement of setting FWDVB
to a value greater than 1 while using one of the four deafult bootstrap options.
Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Acked-by : Victor Gallardo <vgallardo@appliedmicro.com> Signed-off-by: Stefan Roese <sr@denx.de>
Matthias Fuchs [Wed, 24 Mar 2010 09:16:20 +0000 (10:16 +0100)]
at91: Get rid of some warnings when building for otc570
The soft-i2c code for AT91 defines I2C_SOFT_DECLARATIONS
for direct access by dereferencing a pio pointer.
The OTC570 platform uses the AT91 gpio API so it does not
need the pio variable.
Florian Fainelli [Sat, 20 Mar 2010 18:02:58 +0000 (19:02 +0100)]
cmd_nand: show nand scrub confirmation character
When issuing a nand scrub command, the entered character is not displayed
this may be confusing. This patch makes the input character being
displayed if it is a 'y' so that an user knows he is about to scrub his
nand.
projects / u-boot / log