Francois Retief [Mon, 23 Nov 2015 11:05:44 +0000 (13:05 +0200)]
sparc: Update PROM initialization code for generic board
Fixed the prom_relocate() function in start.S file by reserving memory in
the board_init_f sequence and saving the offset to the __prom_start_reloc
variable. This value is used as the destination when relocating the PROM.
Add the prom_init() function to the end of the board_init_r sequence.
Francois Retief [Wed, 28 Oct 2015 13:18:22 +0000 (15:18 +0200)]
sparc: Update cpu_init.c to use generic timer infrastructure
Introduce the CONFIG_SYS_TIMER_* macros in include/asm/config.h to make use
of the generic timer infrastructure in lib/time.c.
Created a timer_init() function to initialize the timer hardware and update
the #ifdef in board_init_f to allow this function to be called during the
start-up sequence.
Francois Retief [Sat, 21 Nov 2015 11:25:41 +0000 (13:25 +0200)]
sparc: leon2: Updates for generic board initialization
Reworked the LEON2 start.S code to call board_init_f function at startup.
Also implemented the relocate_code function in assembly to relocate the
monitor and setup the stack pointer before calling relocated board_init_r.
Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON2 boards.
Francois Retief [Wed, 28 Oct 2015 22:02:48 +0000 (00:02 +0200)]
sparc: leon3: Updates for generic board initialization
Reworked the LEON3 start.S code to call board_init_f function at startup.
Also implemented the relocate_code function in assembly to relocate the
monitor and setup the stack pointer before calling relocated board_init_r.
Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON3 boards.
Francois Retief [Mon, 23 Nov 2015 07:49:57 +0000 (09:49 +0200)]
sparc: leon3: Clear GD_FLAG_SERIAL_READY flag on AMBA failure
Clear the GD_FLG_SERIAL_READY flag on AMBA P&P lookup failure so that the
panic function can use DEBUG_UART driver. drivers/serial/serial.c set this
flag before calling this function, preventing DEBUG_UART code from running.
As discussed on the list, we already have the needed functionality by
defining CONFIG_SYS_CONSOLE_IS_IN_ENV, CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
and adding custom overwrite_console() in the board code.
Marek Vasut [Thu, 26 Nov 2015 13:08:50 +0000 (14:08 +0100)]
arm: imx6: novena, gw_ventana: Fix use of pfuze100 bit definitions
The following patch changed the PFUZE100 swbst register bit definitions
and broke PMIC configuration on multiple boards, at least on the novena
and gw_ventana. This patch fixes it.
Sjoerd Simons [Sun, 22 Nov 2015 07:21:04 +0000 (08:21 +0100)]
rockchip: Explicitly set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN
Now that u-boot relocates the malloc area in SPL to SDRAM, with the
malloc area sitting below the SPL_STACK_R_ADDR the
SPL_STACK_R_MALLOC_SIMPLE_LEN needs to be set explicitly for
rockchip as its SPL_STACK_R_ADDR (512kb) is smaller then
STACK_R_MALLOC_SIMPLE_LEN (1Mb).
Using the same value as SYS_MALLOC_F_LEN (8kb) is enough to load u-boot
from SD card.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
Sjoerd Simons [Sun, 22 Nov 2015 07:21:03 +0000 (08:21 +0100)]
Revert "rockchip: Reconfigure the malloc based to point to system memory"
This patch was merged shortly before the v2015.10 as a minimal fix for
booting on rockchip. Now that the patch series from Hans to do the
relocation in generic code has been merged it can be dropped.
Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h
board configs are now incorrect because CONFIG_SPL_BUILD is enabled so
CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE
instead of SYS_MALLOC_SIMPLE.
This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig
option by default in rockchip-mach.
Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
Jeffy Chen [Tue, 17 Nov 2015 06:20:30 +0000 (14:20 +0800)]
rockchip: Add support for rk's second level loader
The Rockchip boot ROM could load & run an initial spl loader,
and continue to load a second level boot-loader(which stored
right after the initial loader) when it returns.
Modify idblock generation code to support it.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Jeffy Chen [Tue, 17 Nov 2015 06:20:29 +0000 (14:20 +0800)]
rockchip: Add max spl size & spl header configs
Our chips may have different max spl size and spl header, so
we need to add configs for that.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
- Add $(if...) to tools/Makefile to fix widespread build breakage
huang lin [Tue, 17 Nov 2015 06:20:28 +0000 (14:20 +0800)]
rockchip: Add basic support for evb-rk3036 board
This add some basic files required to allow the board to dispaly
serial message and can run command(mmc info etc)
Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Moved board Kconfig fragment from previous patch into this one to fix
build error: Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- moved board Kconfig fragment from previous patch into this one
huang lin [Tue, 17 Nov 2015 06:20:27 +0000 (14:20 +0800)]
rockchip: rk3036: Add core Soc start-up code
rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.
Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
huang lin [Tue, 17 Nov 2015 06:20:24 +0000 (14:20 +0800)]
rockchip: mmc: get the fifo mode and fifo depth property from dts
rk3036 mmc do not have internal dma, so we use fifo mode when read
and write data, we get the fifo mode and fifo depth property from
dts, pass to dw_mmc driver.
Similar to load an fdt, when loading an initrd about the 512Mb mark
things seem to break. For now force loading below 512Mb until the reason
why this fails has been determined/solved.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
Michael Heimpold [Sun, 15 Nov 2015 21:47:12 +0000 (22:47 +0100)]
ARM: mxs: fix VDDD brownout setting
At the moment, the desired brownout is at 1.0V. However,
this setting cannot be realized by hardware since we have
only 3 bits to represent the voltage difference from the
target value.
Target value is 1500 mV, brownout target is 1000 mV,
voltage steps are 25 mV.
But 0x4 * 25 [mV] = 100 [mV], that means that actual
brownout level is 1500 [mV] - 100 [mV] = 1.4 V.
Minimum possible BO level is
1500 [mV] - 0x7 * 25 [mV] = 1315 [mV].
So lets use this value as desired BO value (which is
also the same as FSL bootlets use).
Signed-off-by: Michael Heimpold <mhei@heimpold.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
Simon Glass [Fri, 27 Nov 2015 02:51:30 +0000 (19:51 -0700)]
dm: pci: Disable PCI compatibility functions by default
We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 27 Nov 2015 02:51:27 +0000 (19:51 -0700)]
pci: Use a separate 'dev' variable for the PCI device
In the 'pci' command, add a separate variable to hold the PCI device. When
this code is converted to driver model, this variable will be used to hold a
struct udevice instead.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 27 Nov 2015 02:51:26 +0000 (19:51 -0700)]
pci: Use common functions to read/write config
Currently we use switch() and access PCI configuration via several
functions, one for each data size. Adjust the code to use generic functions,
where the data size is a parameter.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 27 Nov 2015 02:51:20 +0000 (19:51 -0700)]
pci: Refactor the pciinfo() function
This function uses macros to output data. It seems better to use a table of
registers rather than macro-based code generation. It also reduces the
code/data size by 2KB on ARM.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 20 Nov 2015 03:27:02 +0000 (20:27 -0700)]
dm: tegra: pci: Convert tegra boards to driver model for PCI
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Fri, 20 Nov 2015 03:26:58 +0000 (20:26 -0700)]
dm: pci: Support decoding ranges with duplicate entries
At present we add a new resource entry for every range entry. But some range
entries refer to configuration regions. To make this work, avoid adding two
regions of the same type. The later ranges will overwrite the earlier
(configuration) ones.
There does not seem to be a way to distinguish the configuration ranges
other than by ordering (as per the device tree binding).
We could perhaps instead just store one region of each type in a simple
array. Once we are sure that we don't need to support multiple regions, we
could change this. It would be easier to do it when all drivers are
converted to use driver model for PCI.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Fri, 20 Nov 2015 03:26:56 +0000 (20:26 -0700)]
dm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUM
This is not supported with driver model, so print a message instead of
generating a build error. Rescanning PCI is not yet implemented.
This function will be implemented later once some additional PCI driver
model improvements are merged. It was confirmed on the mailing list
that no one on the tegra side will miss this feature, so it is disabled
for tegra.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Sun, 29 Nov 2015 05:16:35 +0000 (22:16 -0700)]
dm: timer: Avoid using timer before it is ready
At present bootstage will try to read the timer very early after relocation.
When driver model is used to provide the timer, we cannot read it until
driver model is ready. Correct this by adding a separate stage for the
post-relocation bootstage init.
This fixes booting on chromebook_link.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Bin Meng [Tue, 24 Nov 2015 20:31:17 +0000 (13:31 -0700)]
dm: timer: Support 64-bit counter
There are timers with a 64-bit counter value but current timer
uclass driver assumes a 32-bit one. Modify timer_get_count()
to ask timer driver to always return a 64-bit counter value,
and provide an inline helper function timer_conv_64() to handle
the 32-bit/64-bit conversion automatically.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 13 Nov 2015 08:11:15 +0000 (00:11 -0800)]
dm: timer: Implement pre_probe()
Every timer device needs to have a valid clock frequency and it
can be specified in the device tree. Use pre_probe() to get this
in the timer uclass driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Thu, 5 Nov 2015 08:37:53 +0000 (16:37 +0800)]
arm: at91/spl: atmel_sfr: move saic redirect to separate file
To make saic redirect code sharing with other SoCs, move the
saic redirect code from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/atmel_sfr.c
Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each
SoC has its own value.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Remove the security peripheral select code, keep the default value
in these registers, that is, the peripheral address space is
configured as "Secured" access, it is suitable for SPL.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Thu, 5 Nov 2015 08:37:49 +0000 (16:37 +0800)]
arm: at91/spl: matrix: move matrix init to separate file
To make the matrix initialization code sharing with other SoCs,
move it from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/matrix.c
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Fri, 30 Oct 2015 01:55:52 +0000 (09:55 +0800)]
arm: atmel: Add SAMA5D2 Xplained board
The board supports following features:
- Boot media support: SD card/e.MMC/SPI flash,
- Support LCD display (optional, disabled by default),
- Support ethernet,
- Support USB mass storage.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
[fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
projects / u-boot / log