Allen Martin [Fri, 31 Aug 2012 08:30:08 +0000 (08:30 +0000)]
tegra20: remove timer_init from SPL build
Don't use timer_init from tegra board.c. This comes out of arm720t
for the SPL build.
Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:07 +0000 (08:30 +0000)]
ARM: Fix arm720t SPL build
Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code
Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:06 +0000 (08:30 +0000)]
MAKEALL: update to work with new boards.cfg syntax
Update MAKEALL to handle the optional SPL CPU field that was added to
boards.cfg. This impacts the cases in MAKEALL that have to match
against CPU type (field 3). In these cases use ':' as a field
separator to split the u-boot CPU from the SPL CPU.
Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:05 +0000 (08:30 +0000)]
mkconfig: remove bashisms and cleanup config.mk generation
This adds some cleanup to mkconfig related to SPL support. Bash
specific script has been replaced with awk for better shell
compatibility. config.mk generation is done through a subshell and
single redirect to improve readability.
Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:04 +0000 (08:30 +0000)]
tegra20: make board mkdir commands unconditional
Change the mkdir commands for the object directories to be
unconditional. This fixes an issue when building for SPL where
SRCTREE and OBJTREE are the same, but $(obj) is under SPLTREE.
Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:03 +0000 (08:30 +0000)]
tegra20: tec: add tegra20-common-post.h
Add tegra20-common-post.h to be consistent with other tegra20 boards.
Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:02 +0000 (08:30 +0000)]
tegra20: rename CONFIG_MACH_TEGRA_GENERIC
Rename CONFIG_MACH_TEGRA_GENERIC to the less confusing CONFIG_TEGRA.
The meaning of the config options is now:
CONFIG_TEGRA - Any tegra chip
CONFIG_TEGRA20 - A tegra20 family chip
CONFIG_TEGRA30 - A tegra30 family chip (not added yet)
Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:01 +0000 (08:30 +0000)]
tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common
In preparation for splitting out the armv4t code from tegra20, move
the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will
be compiled armv4t for the arm7tdmi and armv7 for the cortex A9.
Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Allen Martin [Fri, 31 Aug 2012 08:30:00 +0000 (08:30 +0000)]
tegra20: rename tegra2 -> tegra20
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Sun, 5 Aug 2012 16:07:22 +0000 (16:07 +0000)]
ARM: add Raspberry Pi model B board, using BCM2835 SoC
The Raspberry Pi model B uses the BCM2835 SoC, has 256MB of RAM,
contains an SMSC 9512 USB LAN/Hub chip, and various IO connectors.
For more details, see http://www.raspberrypi.org/.
Various portions (cache enable, MACH_TYPE setup, RAM size limit, stack
relocation to top of RAM) extracted from work by:
Oleksandr Tymoshenko <gonzo@bluezbox.com>.
GPIO driver enablement by Vikram Narayanan <vikram186@gmail.com>.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Tom Rini <trini@ti.com>
Stephen Warren [Sun, 5 Aug 2012 16:07:21 +0000 (16:07 +0000)]
ARM: add basic support for the Broadcom BCM2835 SoC
This SoC is used in the Raspberry Pi, for example.
For more details, see:
http://www.broadcom.com/products/BCM2835
http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf.
Initial support is enough to boot to a serial console, execute a minimal
set of U-Boot commands, download data over a serial port, and boot a
Linux kernel. No storage or network drivers are implemented.
GPIO driver originally by Vikram Narayanan <vikram186@gmail.com>
with many fixes from myself.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
John Rigby [Tue, 31 Jul 2012 08:59:31 +0000 (08:59 +0000)]
u8500: Separating mmc config parameters from driver
Configuration in vexpress and u8500.v1 is different from what
is needed in u8500.v2. As such, card configuration specifics need
to reside in the board file rather than the driver.
Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
u8500: Moving processor-specific functions to cpu area.
Functions such as providing power to the MMC device and reading
the processor version register should be in the cpu area for
access by multiple u8500-based boards.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 27 Jun 2012 05:27:05 +0000 (05:27 +0000)]
davinci, c6x: Always use C version of reset code
We can safely use the same reset code written in C for both Davinci and
C6X platforms. In addition the C version of the code is marginally
smaller on Davinci.
Tested-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
Jeroen Hofstee [Tue, 14 Aug 2012 10:39:29 +0000 (10:39 +0000)]
arm: omap: Fix switching back to nandecc sw.
Orjan Friberg wrote at [1]:
"For the beagleboard, ecc.size is not explicitly set when doing 'nandecc
sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's
set to 256 bytes.
When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when
changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly
the format has changed."
No patch has been submitted and the issue was still present. This patch
adds the mentioned solution. Tested on a tam3517 board.
Heiko Schocher [Mon, 13 Aug 2012 23:51:04 +0000 (23:51 +0000)]
davinci: enbw_cmc: change switch init behaviour
change the behaviour of switch initialization:
- rename "pwl" to "lan" in hwconfig parameter
"lan" = port 1 with phy addr 2
"lmn" = port 2 with phy addr 3
- if we have a valid switch config file in flash, do not
evaluate the settings in the hwconfig "lan" or "lmn"
subcommand.
- if we have no valid switch config file in flash, start
the switch with default values, if we have a "lan" or
a "lmn" hwconfig subcommand. If no "lan" or "lmn" is
found in hwconfig, do nothing with the switch.
am33xx evm: Update secure_emif_sdram_config during ddr init
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.
During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.
Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.
Tom Rini [Thu, 9 Aug 2012 00:03:10 +0000 (17:03 -0700)]
omap4/5/am33xx: Make lowlevel_init available to all armv7 platforms
Make the lowlevel_init function that these platforms have which just
sets up the stack and calls a C function available to all armv7
platforms. As part of this we change some of the macros that are used
to be more clear. Previously (except for am335x evm) we had been
setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are
equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we
should have been doing this initially and do now.
Cc: Sricharan R <r.sricharan@ti.com> Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 8 Aug 2012 16:03:07 +0000 (09:03 -0700)]
am335x evm: Initial support for AM335x GP EVM Profiles
The AM335x GP EVM can have one of 8 different profiles selected. Each
profile has a different set of peripherals and requires different pinmux
configurations that conflict with other profiles. i2c1 is an example of
a conflicted mux currently.
Marek Vasut [Fri, 6 Jul 2012 21:25:57 +0000 (21:25 +0000)]
MX28: Fix MXS MMC DMA issues
The DMA didn't work properly because the DMA descriptor wasn't
properly cleaned after it was used once. Also, the DMA_ENABLE bit
was enabled/disabled too late.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
Marek Vasut [Fri, 6 Jul 2012 21:25:56 +0000 (21:25 +0000)]
MX28: Transfer small blocks via PIO in MXS MMC
Large blocks (> 512b) shall be transfered via DMA to make
things a bit faster.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
Marek Vasut [Fri, 6 Jul 2012 21:25:55 +0000 (21:25 +0000)]
MX28: Split out the PIO and DMA transfer functions
Move DMA and PIO data transfer parts into separate functions.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
Marek Vasut [Fri, 6 Jul 2012 21:25:54 +0000 (21:25 +0000)]
MX28: Fix up the MMC driver DMA mode
The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1.
Also, it was using SSP0 DMA channel for all SSP devices.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
Otavio Salvador [Sat, 28 Jul 2012 11:44:20 +0000 (11:44 +0000)]
MX28: use a clear name for DDR2 initialization
The mx28 prefix has been added to the initialization data and function
so it is clear by which SoC it is used as i.MX233 will have a specific
one. While on that, we also change it to static.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
This adds support for Bluegiga APX4 Development Kit. It is built around
Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC,
RTC and USB. APX4 has only one ethernet port.
Marek Vasut [Mon, 9 Jul 2012 00:48:33 +0000 (00:48 +0000)]
MX28: SPI: Add DMA transfer support
The DMA transfers happen only if the transfered data are larger
than 512 bytes. Otherwise PIO is used. This is a small speed
optimization.
The DMA transfer doesn't work if unaligned transfer is requested
due to the limitation of the DMA controller. This has to be fixed
by introducing generic bounce buffer. Therefore the DMA feature
is now disabled by default.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Marek Vasut [Mon, 9 Jul 2012 00:48:32 +0000 (00:48 +0000)]
MX28: SPI: Pull out the PIO transfer function
Pull out all the PIO transfer logic into separate function,
so DMA can be added.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Marek Vasut [Mon, 9 Jul 2012 00:48:31 +0000 (00:48 +0000)]
MX28: SPI: Refactor spi_xfer a bit
This makes it easier to adapt for addition of DMA support.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
Markus Hubig [Tue, 7 Aug 2012 15:43:23 +0000 (17:43 +0200)]
at91: Add support for taskit AT91SAM9G20 boards.
This adds support for the AT91SAM9G20 boards by taskit GmbH.
Both boards, Stamp9G20 and PortuxG20, are integrated in one
file. PortuxG20 is basically a SBC built around the Stamp9G20.
Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.deve@googlemail.com>
Markus Hubig [Tue, 7 Aug 2012 15:43:22 +0000 (17:43 +0200)]
Enable the EMAC clock in at91_macb_hw_init().
Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not
initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...]
ARM frequency = 300 MHz
DSP frequency = -536870913 MHz
DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for
the DA8xx SoCs that initialises the DSP frequency to zero (since
currently the DSP is not enabled by U-Boot on any DA8xx platform). The
separate implementation is justified because there is no common code
between DA8xx and the other SoC families. It is now much easier to
understand the flow of the two separate functions.
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in
place, it is clear how to define new clock IDs, and how these map to the
numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> Signed-off-by: Tom Rini <trini@ti.com>
Marek Vasut [Sat, 21 Jul 2012 05:02:23 +0000 (05:02 +0000)]
dm: Move OMAP GPIO driver to drivers/gpio/
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
Marek Vasut [Sat, 21 Jul 2012 05:02:27 +0000 (05:02 +0000)]
dm: Select CONFIG_SPL_GPIO_SUPPORT on OMAP
This fixes the breakage with SPL on most OMAP boards after the GPIO
driver was moved.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Tue, 31 Jul 2012 17:50:01 +0000 (10:50 -0700)]
am33xx: Rework pinmux functions
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h>
- Make some defines a little less generic now.
- Pinmux must be done by done by SPL now.
- Create 3 pinmux functions, uart0, i2c0 and board.
- Add pinmux specific to Starter Kit EVM for MMC now.
Tom Rini [Tue, 31 Jul 2012 15:55:01 +0000 (08:55 -0700)]
am33xx: Add support for TI AM335x StarterKit EVM
- Board requires gpio0 #7 to be set to power DDR3.
- Board uses DDR3, add a way to determine which DDR type to call
config_ddr with.
- Both of the above require filling in the header structure early, move
it into the data section.
Tom Rini [Mon, 30 Jul 2012 23:13:10 +0000 (16:13 -0700)]
am33xx: Remove board/ti/am335x/evm.c
The intention has always been (and boards are to support) an i2c EEPROM
that will identify what hardware they are, allowing a single binary to
support multiple boards. As such, remove the 'evm.c' file as there is
nothing EVM centric in it currently, only SoC peripheral configuration.
Tom Rini [Mon, 30 Jul 2012 21:13:56 +0000 (14:13 -0700)]
am33xx: Rework config_ddr to make DDR3 support easier.
In order to support DDR3 as well as DDR2, we need to perform the same
init sequence, but with different values. So change config_ddr() to
toggle setting pointers/etc for what DDR2 wants, and then calling.
Tom Rini [Mon, 30 Jul 2012 18:49:47 +0000 (11:49 -0700)]
am33xx: Correct and clean up ddr_regs struct
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.
Tom Rini [Tue, 24 Jul 2012 23:49:58 +0000 (16:49 -0700)]
am33xx: Do not touch 'ratio1' fields
The various ratio1 fields are not documented in any of the documentation
I can find. Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.
Tom Rini [Tue, 24 Jul 2012 23:31:26 +0000 (16:31 -0700)]
am33xx: Rework config_io_ctrl slightly
This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation). Rather than defining a struct and setting the
value repeatedly, just pass in the value.
Tom Rini [Tue, 24 Jul 2012 21:54:41 +0000 (14:54 -0700)]
am33xx: Turn a number of 'int' functions to 'void'
A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.
Tom Rini [Tue, 24 Jul 2012 21:03:24 +0000 (14:03 -0700)]
am33xx: Document what we're doing with ddrctrl->ddrckectrl
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
we're operating in the normal mode where EMIF/PHY clock is controlled
by the PHY.
EMIF parameters are calculated based on the AC timing
parameters from the SDRAM datasheet and the DDR frequency.
Current values for these paramters in AM335x U-Boot code,
though reliable, are not fully optimal. The most optimal
settings can be derived based on the guidelines published
at [1]. A pre-computed set of values with the most optimum
settings for AM335x EVM and BeagleBone can be found at [2].
Tom Rini [Tue, 3 Jul 2012 16:20:06 +0000 (09:20 -0700)]
am33xx: Move the call to ddr_pll_config, make it take the frequency
Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value. This call can be delayed
slightly to the point where we know which type of memory we have.
Tom Rini [Tue, 3 Jul 2012 15:51:34 +0000 (08:51 -0700)]
am33xx: Pass to config_ddr the type of memory that is connected
We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()). For now, pass in
the value of DDR2.
Tom Rini [Tue, 3 Jul 2012 15:48:46 +0000 (08:48 -0700)]
am33xx: Make config_cmd_ctrl / config_ddr_data take const structs
Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const. This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.
projects / u-boot / log