Guenter Roeck [Wed, 14 Feb 2018 16:57:46 +0000 (08:57 -0800)]
Save and restore bank around envmon register accesses if needed
If an external EC accesses the chip through SMBus registers
and if the chip's environmental registers are paged, it is likely
that the EC modifies the page register. If so, it likely will not
update the page on each access but assume that it "owns" the chip.
If the driver then modifies the page register, subsequent accesses
from the EC will likely have unpredictable results.
To avoid that problem, let's save the page register value after
disabling SMBus accesses and restore the original value when done.
This is only necessary if accesses are not handled through MMIO
since we don't touch the page register in that case.
"This is indeed not working, at least on Fedora. I tried specifying
MAKE and CLEAN but the outcome is the same (which makes sense, since
the defaults should already cover this)."
Guenter Roeck [Sat, 7 Oct 2017 14:38:41 +0000 (07:38 -0700)]
Fix PECI/AMDTSI selection
We can not use register 0x98 since it is typically not programmed
on systems selecting PECI. Try register 0x0a (Interface Selection)
which should be a better fit anyway.
Guenter Roeck [Mon, 2 Oct 2017 21:08:29 +0000 (14:08 -0700)]
Report actual chip name, not its ID
For some recent chips (at least IT8792E/IT8795E), the value of the chip ID
register does not match the chip name. Display the textual, not the value
of the ID register, in the kernel log.
Guenter Roeck [Mon, 2 Oct 2017 17:53:44 +0000 (10:53 -0700)]
Makefile: Versioning, take three
Make sure the build passes if the source is not in a git repository.
Again, that means that version information won't be available, but there
is only so much we can do about that.
Guenter Roeck [Mon, 2 Oct 2017 02:11:33 +0000 (19:11 -0700)]
Drop version.h
Some distributions use their own Makefile and thus won't create version.h,
resulting in a build failure. Pass the version as define instead.
That won't help for generating the driver version with those distributions,
but at least the driver will build.
Disable SMBus access while accessing Enviromnental Controller registers
Some chips support Environmental Controller access through SMBus.
On those chips, it is possible that an Embedded Controller accesses
Environmental Controller chip registers at any time. There is no real
means for synchronization. On banked chips, this can and will result in
access errors with unpredictable result.
Disable SMBus access while reading or writing environmental controller
registers to work around the problem.
Always restore previous bank register after reading/writing data
There is some indication that other entities (BIOS ? EC ?) may access
the chip asynchronously. Restore the bank selection after read/write
operations to limit any potenial impact.
It appears that some BIOSes reserve ACPI resources without using them,
and acpi_enable_resources=lax seems to result in failures to load
certain drivers.
Introduce a 'ignore_resource_conflict' module parameter as alternate
means to ignore ACPI resource conflicts.
Various chips have different numbers of valid values for pwm temperature
mapping. Rework the code to take this into account.
No longer keep map as bitmap, but maintain it as number 1..X. Do not try to
define a separate mapping entry for pwm4..6 on chips where the temperature
map for those pwm controls is taken from a different temperature input.
Introduce helpers to convert the control register contents to a map and
vice versa.
Reflect that IT8607 uses the new temperature map in bit 3..5 of the pwm
control register.
Update pwm cached control registers before writing pwm enable
If pwmX_enable is written prior to displaying any attributes,
t87_update_pwm_ctrl() is never called, and the cached pwm registers
are never read before written. This results in bad values written
into various registers, and can result in operational failures.
Guenter Roeck [Sat, 5 Aug 2017 19:48:49 +0000 (12:48 -0700)]
Fix accesses to IT8792E
If IT8792E or a compatible chip such as IT8795 (which has the same chip ID,
0x8733) resides at SIO address 0x4e/0x4f, and another Super-IO chip is at
SIO address 0x2e/0x2f, the IT8792E causes a cycle decode problem when exiting
its configuration mode. This can result in access errors for both chips, and
may result in system hangs.
Never exit configuration mode for IT8792E to avoid the problem.
Guenter Roeck [Wed, 7 Jun 2017 23:56:31 +0000 (16:56 -0700)]
Add support for 6 temperature limit registers on IT8628E
IT8628E has 6 temperature limit registers, overlayed with VIN7..VIN9
limit registers, but only 3 temperature offset registers. Given that,
introduce separate variables for the number of temperature limit
registers and the number of temperature offset registers.
Several recent chips have a different register definition for
temperature to pwm assignment. Introduce FEAT_NEW_TEMPMAP to reflect
this and assign to affected chips.
- Acquire acpi mutex (not supported in upstream kernel)
- Try to handle 0x4e access failures on Gigabyte boards
- Improve temperature register / limit / type support for recent chips
Guenter Roeck [Tue, 28 Mar 2017 13:26:19 +0000 (06:26 -0700)]
Add feature flag FEAT_FANCTL_ONOFF
Several recent chips don't support configuration bits to turn fan control
off entirely for the first three fans. Handle all of them with a
configuration flag.
Guenter Roeck [Tue, 21 Mar 2017 00:43:03 +0000 (17:43 -0700)]
Separate internal scaling from 12mV ADC
Some chips have internal voltage scaling but 10.9mV ADC,
so we can no longer associate the 12mV ADC with internal scaling
but need a different flag to distinguish scaling support.
Guenter Roeck [Wed, 8 Feb 2017 17:10:11 +0000 (09:10 -0800)]
Do not overwrite bit 2..6 of pwm control registers
In IT8620E, after setting pwm control to manual, it was observed that
pwm values for fan 4..6 have reversed results (writing 0 results in fans
running at full speed, writing 255 results in fans turned off).
With the new PWM control, pwm polarity for pwm control 4..6 is specified
in its pwm control registers. Those registers are overwritten when setting
the pwm mode or the temperature mapping. Do not touch bit 2..6 of pwm
control registers on register writes to fix the problem.
Guenter Roeck [Wed, 8 Feb 2017 14:29:43 +0000 (06:29 -0800)]
Fix fan4_ctl detection for IT8620, IT8628
fan4 control is enabled if bit 2 of GPIO control register 4 is disabled,
not when it is enabled. Since the check is for the skip condition, it is
reversed. This applies to both IT8620 and IT8628.
Ensure that pwm control cache is current before updating values
If sensor attributes were never read, the pwm control data has not been
initiialized, which can cause wrong driver behavior. Ensure that cached
data is current before acting on it.
Reported-by: Kevin Folz <kfolz@evertz.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
projects / groeck-it87 / log