Jagan Teki [Fri, 12 May 2017 11:48:22 +0000 (17:18 +0530)]
icorem6: Recover missing nand defconfig
nand defconfig is accidentally removed from below
commit, so recover the same.
"icorem6: Make SPL to pick suitable fdt"
(sha1: 15455a6b01d97d575afe2f494cfc9722424230c0)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The maximum SD clock frequency in High Speed mode is 50 MHz. This change
makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1)
instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
imx_get_perclk() used the AHB clock as the clock source for all PER
clocks, but the USB PLL output can also be a PER clock source if the
corresponding PER CLK MUX bit is set in CCM.MCR.
mmc: fsl_esdhc: Allow all supported prescaler values
On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock
frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler
can divide by up to 512. Allow both of these settings.
The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
this change makes it possible to get 48 MHz from the USB PLL
(240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
(240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
Tim Harvey [Fri, 12 May 2017 19:58:41 +0000 (12:58 -0700)]
drivers: pci: imx: add imx_pcie_remove function
There is no dedicated reset signal wired up for the MX6QDL thus if the
bootloader enables the link we need some special handling to get the core
back into a state where it is safe to touch it for configuration.
While there has been some special handling in the Linux kernel to do this,
it was removed in 4.11 thus we need to do it properly in the bootloader
and therefore without this if you enable PCI in the bootloader you will hang
while booting the 4.11 kernel.
This puts the PCIe controller back into a safe state for the kernel driver
before launching the kernel.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com>
Philipp Tomsich [Mon, 15 May 2017 22:16:32 +0000 (00:16 +0200)]
doc: document u-boot, mmc-env-offset and u-boot, mmc-env-offset-redund
Adding documentation on the new config properties:
'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
'u-boot,mmc-env-offset-redundant'
- overrides CONFIG_ENV_OFFSET_REDUND
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Philipp Tomsich [Mon, 15 May 2017 22:16:31 +0000 (00:16 +0200)]
env_mmc: configure environment offsets via device tree
This introduces the ability to override the environment offets from the
device tree by setting the following nodes in '/config':
'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
'u-boot,mmc-env-offset-redundant'
- overrides CONFIG_ENV_OFFSET_REDUND
To keep with the previous logic, the CONFIG_* defines still need to
be available and the statically defined values become the defaults,
when the corresponding properties are not set in the device-tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
Keerthy [Wed, 24 May 2017 04:49:27 +0000 (10:19 +0530)]
power: pmic: tps65218: Fix tps65218_voltage_update function
Currently while setting the vsel value for dcdc1 and dcdc2
the driver is wrongly masking the entire 8 bits in the process
clearing PFM (bit7) field as well. Hence describe an appropriate
mask for vsel field and modify only those bits in the vsel
mask.
Tom Rini [Wed, 10 May 2017 19:20:17 +0000 (15:20 -0400)]
drivers/power/regulator/max77686.c: Fix comparisons of unsigned expressions
Inside of
max77686_buck_volt2hex/max77686_buck_hex2volt/max77686_ldo_volt2hex we
check that the value we calculate is >= 0 however we declare 'hex' as
unsigned int making these always true. Mark these as 'int' instead. We
also move hex_max to int as they are constants that are 0x3f/0xff.
Given that the above functions are marked as returning an int, make the
variables we assign their return value to also be int to be able to
catch the error condition now. Reported by clang-3.8.
Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 10 May 2017 19:20:16 +0000 (15:20 -0400)]
mmc: Change 'part_config' to be a u8 not char.
In some places we check if part_config is set to MMCPART_NOAVAILABLE
(0xff). With part_config being a char this is always false. We should
be using a u8 to store this value instead, after a quick consultation
with the Linux Kernel. Reported by clang-3.8.
Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Udit Agarwal [Tue, 2 May 2017 12:13:57 +0000 (17:43 +0530)]
armv8: LS2080A: Adjust memory map for secure boot headers for NOR-boot
This patch adjusts memory map for secure boot headers on LS2080AQDS
and LS2080ARDB platforms. Secure boot headers are placed on NOR
flash at offset 0x00600000.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Tue, 16 May 2017 02:45:59 +0000 (10:45 +0800)]
armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1046A
This patch is to adjust the memory mapping for FLash/SD card on
LS1046AQDS and LS1046ARDB, such as FMAN firmware load address, U-Boot
start address on serial flash and environment address.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Tue, 16 May 2017 02:45:58 +0000 (10:45 +0800)]
armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1043A
This patch is to adjust the memory mapping for FLash/SD card on
LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
firmware load address, QE firmware load address, U-Boot start address
on serial flash and environment address.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Tue, 16 May 2017 02:45:57 +0000 (10:45 +0800)]
arm: ls1021a: Adjust memory mapping for Flash/SD card on LS1021AQDS/TWR
This patch is to adjust the memory mapping for FLash/SD card on
LS1021AQDS and LS1021ATWR, such as U-Boot start address on serial
Flash, QE firmware load address and environment address.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
LS2081ARDB board is similar to LS2080ARDB board with few differences
It hosts LS2081A SoC
Default boot source is QSPI-boot
It does not have IFC interface
RTC and QSPI flash device are different
It provides QIXIS access via I2C
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS
flag is enabled. In case QIXIS code is not enabled, use default
sysclk value as 100MHz per board documentation.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Earlier when MC is loaded but DPL is not deployed results in FDT
fix-up code execution hangs. For this case now print message on
console and return success instead of return -ENODEV. This update
allows fdt fixup to continue execution.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Priyanka Jain <Priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
board: freescale: ls2080ardb: Enable SD interface for RevF board
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
which needs to be programmed to enable high speed SD interface
by setting GPIO4_10 output to zero.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Tom Rini [Mon, 22 May 2017 19:40:11 +0000 (15:40 -0400)]
mksunxi_fit_atf.sh: Allow for this to complete when bl31.bin is missing
In situations like an autobuilder we are likely to not have bl31.bin
present and thus would fail to build and propagate the error upwards.
Instead, print a big warning to stderr so that human will see that
something is wrong but complete the build.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
Lothar Waßmann [Thu, 18 May 2017 15:26:58 +0000 (17:26 +0200)]
ColdFire: Remove rogue 'CONFIG_SYS_NO_FLASH' embedded within another CONFIG_ name
The original commit for the MCF54418TWR ColdFire development board
support defined a 'CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN'
which obviously has a rogue 'CONFIG_SYS_NO_FLASH' embedded in the
intended 'CONFIG_SYS_FAULT_ECHO_LINK_DOWN' define.
Simon Glass [Wed, 17 May 2017 09:25:38 +0000 (03:25 -0600)]
fs: Kconfig: Add a separate option for FS_JFFS2
Rather than using CMD_JFFS2 for both the filesystem and its command, we
should have a separate option for each. This allows us to enable JFFS2
support without the command, if desired, which reduces U-Boot's size
slightly.
Simon Glass [Wed, 17 May 2017 09:25:30 +0000 (03:25 -0600)]
Kconfig: Add a CONFIG_IDE option
At present IDE support is controlled by CONFIG_CMD_IDE. Add a separate
CONFIG_IDE option so that IDE support can be enabled without requiring
the 'ide' command.
Update existing users and move the ide driver into drivers/block since
it should not be in common/.
Simon Glass [Wed, 17 May 2017 09:25:28 +0000 (03:25 -0600)]
Convert CONFIG_CMD_HDMIDETECT to Kconfig
This converts the following to Kconfig:
CONFIG_CMD_HDMIDETECT
Note that we cannot do 'default y if VIDEO' because this option is only
enabled for a small subset of mx6 boards. Also this command is is not a
great implementation (it doesn't use driver model).
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 17 May 2017 15:05:34 +0000 (09:05 -0600)]
Kconfig: Add CONFIG_HASH to enable hashing API
At present CONFIG_CMD_HASH enables the 'hash' command which also brings
in the hashing API. Some boards may wish to enable the API without the
command. Add a separate CONFIG to permit this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 17 May 2017 09:25:25 +0000 (03:25 -0600)]
Convert CONFIG_CMD_HASH to Kconfig
This converts the following to Kconfig:
CONFIG_CMD_HASH
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Rework slightly, enable on some boards again] Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 17 May 2017 09:25:10 +0000 (03:25 -0600)]
Convert CONFIG_CMD_EEPROM et al to Kconfig
This converts the following to Kconfig:
CONFIG_CMD_EEPROM
CONFIG_CMD_EEPROM_LAYOUT
CONFIG_EEPROM_LAYOUT_HELP_STRING
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Rework Kconfig logic slightly, define EEPROM location on TI eval
platforms] Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 17 May 2017 09:25:05 +0000 (03:25 -0600)]
Drop digital thermometer and thermostat (DTT) drivers
This subsystem is quite old. It has been replaced with a driver-model
version (UCLASS_THERMAL). Boards are free to convert to that if required,
but here is a removal patch that could be applied in the meantime.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 17 May 2017 09:25:03 +0000 (03:25 -0600)]
Kconfig: Drop CONFIG_SYS_I2C_DTT_ADDR
This option is only defined to a non-default value by canyonlands, which
needs conversion to driver model (where the I2C address would be defined
by the device tree).
Drop this option.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 17 May 2017 09:25:01 +0000 (03:25 -0600)]
Kconfig: Drop CONFIG_CMD_DS4510
This option enables a command in the driver. But the functions defined by
the driver are not called anywhere else in U-Boot. So it does not seem
useful to have this driver without its commands.
Drop this option, move the header file out of the common include/
directory and make all the function static.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Tom Rini [Mon, 15 May 2017 16:17:49 +0000 (12:17 -0400)]
lib: move hash CONFIG options to Kconfig
Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support
using hardware acceleration.") created entries for CONFIG_SHA1,
CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
However, no defconfig has migrated to it. Complete the move by first
adding additional logic to various Kconfig files to select this when
required and then use the moveconfig tool. In many cases we can select
these because they are required to implement other drivers. We also
correct how we include the various hashing algorithms in SPL.
This commit was generated as follows (after Kconfig additions):
Tom Rini [Mon, 15 May 2017 16:17:48 +0000 (12:17 -0400)]
FIT: Rename FIT_DISABLE_SHA256 to FIT_ENABLE_SHA256_SUPPORT
We rename CONFIG_FIT_DISABLE_SHA256 to CONFIG_FIT_ENABLE_SHA256_SUPPORT which
is enabled by default and now a positive option. Convert the handful of boards
that were disabling it before to save space.
Cc: Dirk Eibach <eibach@gdsys.de> Cc: Lukasz Dalek <luk0104@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Add a USB controller driver for the EHCI block in R8A7795/R8A7796 SoC.
This is a stopgap measure until we have proper DT support, clock and
reset framework in place, at which point we can switch to ehci-generic.
projects / u-boot / log