Maxime Ripard [Fri, 3 Mar 2017 14:13:30 +0000 (15:13 +0100)]
cmd: nand: Make the NAND options default to NAND_SUNXI
If we depend on the ARCH_SUNXI configuration option, the boards that do not
have NAND support enabled (with the associated options) will not compile
anymore.
Depend on the NAND driver configuration option to make sure that is not the
case.
Reported-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Wed, 1 Mar 2017 06:03:34 +0000 (14:03 +0800)]
sunxi: Add boards/sunxi and arch/arm/mach-sunxi to sunxi MAINTAINERS entry
Recently some sunxi related code was moved to arch/arm/mach-sunxi, but
the MAINTAINERS entry was not updated to reflect this. Add this, and
the board level boards/sunxi directory to our entry.
While at it, also update its status, to reflect the current active
maintainership.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
The Sunchip CX-A99 is a board used in some media players. It features:
An Allwinner A80 ARM SoC (4 * Cortex-A7 + 4 * Cortex-A15 cores)
2 GiB or 4 GiB DDR3 DRAM
AXP808 PMIC
16 GB or 32 GB eMMC
SDIO Wifi/Bluetooth/FM module
SD card slot
1 USB 3.0 connector
2 USB 2.0 connectors
SATA connector
UART connector (internally) for serial console
Ethernet connector (10/100/1000 Mbit/s)
HDMI connector
Composite video and analog audio connector
S/PDIF connector
IR remote control receiver
This patch adds a defconfig for the board. The DRAM settings are as found
in the vendor sys_config.fex file.
It has a preliminary device tree for use until a device tree is accepted
upstream, after which it can be replaced by the upstream version.
Signed-off-by: Rask Ingemann Lambertsen <rask@formelder.dk>
[squash commits, and edited new meanful commit message] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:15 +0000 (18:22 +0100)]
sunxi: Add support for the CHIP Pro
The CHIP Pro is a SoM that features the GR8 SIP, an AXP209, a BT/WiFi chip
and a 512MiB SLC NAND.
This it's an SLC NAND, it doesn't suffer the same drawbacks than found on
the MLC NANDs, and we can enable it right away.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:14 +0000 (18:22 +0100)]
sunxi: Sync GR8 DTS and AXP209 with the kernel
Those DT will be part of 4.10, sync them so we can have our own config.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:13 +0000 (18:22 +0100)]
scripts: sunxi: Build an raw SPL image
Introduce a new sunxi-spl-with-ecc.bin image with already the right header,
ECC, randomizer and padding for the BROM to be able to read it.
It needs to be flashed using a raw access to the NAND so that the
controller doesn't change a thing to it, since we already have all the
right parameters.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Maxime Ripard [Mon, 27 Feb 2017 17:22:12 +0000 (18:22 +0100)]
nand: sunxi: Add options for the SPL NAND configuration
The SPL image needs to be built with a different ECC configuration than the
U-Boot binary.
Add Kconfig options with defaults to provide a value that should work for
anyone, but is still configurable if needs be.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:11 +0000 (18:22 +0100)]
sunxi: Add the default mtdids and mtdparts to our env
In order for the user to be able to see and modify them, add those
variables to the default environment.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Hans de Goede [Mon, 27 Feb 2017 17:22:10 +0000 (18:22 +0100)]
sunxi: Enable UBI and NAND support
Enable the NAND and UBI support in the configuration header so that we can
(finally) use it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:09 +0000 (18:22 +0100)]
mtd: sunxi: Change U-Boot offset
The default U-Boot offset for the Allwinner SoCs was set to 32kB.
This was probably to try to maintain some compatibility with the current
image that we build for the MMC where the U-Boot binary is also located at
a 32kB offset.
However, this causes a number of issues. The first one is that it prevents
us from using a backup SPL entirely, which is troublesome in case where the
first would be corrupt (especially on MLC which have a higher number of
bitflips).
We also cannot use the original MMC image on the NAND, because we need to
prepare the SPL image to include the ECCs and randomizer settings, which
reduces the interest of setting it at that particular offset.
It also prevents us from upgrading and flashing the U-Boot and SPLs
independantly, since it's very likely that it will fall in the same erase
block.
Since that default wasn't used by any board, change it for 8MB, which will
be in an erase block of its own, all the erase blocks being multiple of
two. The highest erase block size we encountered is 4MB, which means that
in this particular setup, the first and second erase blocks will be for the
SPL and its backup, and the third for U-Boot.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Boris Brezillon [Mon, 27 Feb 2017 17:22:07 +0000 (18:22 +0100)]
cmd: nand: Expose optional suboptions in Kconfig
Sometime we need to enable advanced suboptions of the nand command set.
Expose these suboptions in Kconfig.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Boris Brezillon [Mon, 27 Feb 2017 17:22:06 +0000 (18:22 +0100)]
cmd: Expose a Kconfig option to enable UBIFS commands
Create a new Kconfig entry to allow CMD_UBIFS selection from Kconfig and
add an hidden LZO option that can be selected by CMD_UBIFS.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jagan Teki <jagan@openedev.com>
Boris Brezillon [Mon, 27 Feb 2017 17:22:05 +0000 (18:22 +0100)]
mtd: ubi: Select RBTREE option from MTD_UBI Kconfig entry
Expose the RBTREE feature through Kconfig and select this option from the
MTD_UBI option.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jagan Teki <jagan@openedev.com>
[Rebased on master] Signed-off-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:04 +0000 (18:22 +0100)]
cmd: Add Kconfig option for CMD_MTDPARTS and related options
CMD_MTDPARTS is something the user might or might not want to select, and
might depends on (or be selected by) other options too.
This is even truer for the MTDIDS_DEFAULT and MTDPARTS_DEFAULT options that
might change from one board to another, or from one user to the other,
depending on what it expects and what storage devices are available.
In order to ease that configuration, add those options to Kconfig.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:03 +0000 (18:22 +0100)]
common: Move environment choice to Kconfig
The environment location is something that might change per board
(depending on what storage options are availaible there) or depending on
the user choice (when we have several options).
Instead of hardcoding it in our configuration header, create a Kconfig
choice with the options we use for now, and the symbols that depend on it.
Once done, also remove the irrelevant sunxi defines.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:02 +0000 (18:22 +0100)]
tools: sunxi: Add spl image builder
This program generates raw SPL images that can be flashed on the NAND with
the ECC and randomizer properly set up.
This has been copied (and tweaked to find the right headers) from the
sunxi-tools (https://github.com/linux-sunxi/sunxi-tools) upstream
repository, commit 1c3a6ca5.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:01 +0000 (18:22 +0100)]
bch: Allow to build for the host
We will need the bch functions in the tool to generate the SPL images for
the Allwinner SoCs.
Do the needed adjustments so that we can use it on the host.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Maxime Ripard [Mon, 27 Feb 2017 17:22:00 +0000 (18:22 +0100)]
nand: sunxi: Fix modulo by zero error
When trying to autodetect the ECC and randomization configurations, the
driver starts with a randomization disabled and no seeds.
In this case, the number of seeds is obviously 0, and the randomize boolean
is set to false.
However, the logic that retrieves the seed for a given page offset will
blindly use the number of seeds, without testing if the randomization is
enabled, basically doing a modulo by 0.
As it turns out, the libgcc in the common toolchain returns 0 here, which
was our expected value in such a case, and why we would not detect it.
However, U-Boot's libgcc will for some reason return from the function
instead, resulting in an error to load the U-Boot binary in the SPL.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Jagan Teki <jagan@openedev.com>
Add support for the NanoPi NEO Air H3 board from friendlyarm.com . This
board contains WiFi, Bluetooth, 8GB eMMC storage and 512 MB DDR3 ram.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[Rebase on master] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Philipp Tomsich [Wed, 22 Feb 2017 18:46:41 +0000 (19:46 +0100)]
sun8i_emac: configure PHY reset GPIO via DM
This ports the support for configuring a GPIO for resetting the
Ethernet PHY (incl. such details as the reset polarity and
pulse-length) from the Designware driver.
X-AffectedPlatforms: A64-uQ7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Simon Glass [Sun, 2 Apr 2017 15:50:32 +0000 (09:50 -0600)]
dm: serial: Allow driver-model serial to be disabled for TPL
Add separate enable/disable controls for driver-model serial. While this
is generally enabled in SPL it may not be in TPL, since serial output can
be obtained with the debug UART with minimal code size.
Simon Glass [Sun, 2 Apr 2017 15:50:30 +0000 (09:50 -0600)]
Makefile: Provide an option to select SPL or TPL
At present we have SPL_ which can be used in Makefiles to select between
normal and SPL CONFIGs like this:
obj-$(CONFIG_$(SPL_)DM) += core/
When TPL is being built, SPL_ has the value 'SPL' which is generally a
good idea since they tend to follow each other. But in extreme situations
we may want to distinugish between SPL and TPL. For example we may not
want to enable CONFIG_DM with TPL.
Add a new SPL_TPL_ variable which is set to either empty (for U-Boot
proper), 'SPL' or 'TPL'. This may prove useful with TPL-specific options.
Simon Glass [Fri, 31 Mar 2017 14:40:37 +0000 (08:40 -0600)]
board_f: Make init_helpers generic
This header file is used by two archs. It could be used by all of them
since it allows the cache to be on during relocation. Move it into a
generic file.
Simon Glass [Fri, 31 Mar 2017 14:40:33 +0000 (08:40 -0600)]
Move dram_init_banksize() to a common header
This is an weak function present on all archs so we should have it in the
common header file. Remove it from arch-specific headers and add a
function comment.
Simon Glass [Fri, 31 Mar 2017 14:40:27 +0000 (08:40 -0600)]
xtensa: Place relocated U-Boot in the normal place
All archs put U-Boot at the bottom of the relocated region. Xtensa does
not, but perhaps not for any good reason. Adjust it to see if things
still work OK.
Simon Glass [Fri, 31 Mar 2017 14:40:25 +0000 (08:40 -0600)]
board_f: Drop return value from initdram()
At present we cannot use this function as an init sequence call without a
wrapper, since it returns the RAM size. Adjust it to set the RAM size in
global_data instead, and return 0 on success.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Fri, 31 Mar 2017 14:40:24 +0000 (08:40 -0600)]
board_f: Drop board_type parameter from initdram()
It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Tue, 28 Mar 2017 16:27:32 +0000 (10:27 -0600)]
i2c: Drop CONFIG_SOFT_I2C_MULTI_BUS
This is not used by any board. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Clean up board_f sequence a little
This series tries to remove #ifdefs from the board_f init sequence. It
gets as far as I2C and then we need to discuss whether we can start to
remove the old I2C framework.
I think that ideally each entry in the init sequence should be enabled by
at most one CONFIG, which is in Kconfig and is not arch-specific.
END Acked-by: Lukasz Majewski <lukma@denx.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Simon Glass [Tue, 28 Mar 2017 16:27:30 +0000 (10:27 -0600)]
board_f: x86: Use checkcpu() for CPU init
At present we misuse print_cpuinfo() do so CPU init on x86. This is done
because it is the next available call after the console is enabled. But
several arches use checkcpu() instead. Despite the horrible name (which
we can fix), it seems a better choice.
Adjust the various x86 CPU implementations to move their init code into
checkcpu() and use print_cpuinfo() only for printing CPU info.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Tue, 28 Mar 2017 16:27:28 +0000 (10:27 -0600)]
board_f: sandbox: Move sandbox_early_getopt_check() into misc_init_f()
We don't need a special hook for sandbox as one of the later ones will do
just as well. We can print error messages about bad options after we
print the banner. In fact, it seems better.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Tue, 28 Mar 2017 16:27:20 +0000 (10:27 -0600)]
board_f: powerpc: Rename get_clocks_866() to get_clocks()
We really don't need to have a name like this in the generic init
sequence. Use the generic get_clocks() name so that we can merge these
two at some point.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Tue, 28 Mar 2017 16:27:18 +0000 (10:27 -0600)]
board_f: x86: Rename x86_fsp_init() to arch_fsp_init()
While x86 is the only user and this could in principle be moved to
arch_cpu_init() there is some justification for this being a separate
call. It provides a way to handle init which is not CPU-specific, but
must happen before the CPU can be set up.
Rename the function to be more generic.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Tue, 28 Mar 2017 16:27:16 +0000 (10:27 -0600)]
board_f: sandbox: Move setup_ram_buf() to private code
There is no need to have this call in the generic init sequence and no
other architecture has needed it in the time it has been there. Move it
into sandbox's private code.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Wed, 5 Apr 2017 14:42:16 +0000 (10:42 -0400)]
mx6sxsabreauto: Remove legacy CONFIG_PCA953X
When this board was switched to using more DM drivers we didn't disable
the legacy PCA953X driver. This in turn learn to a build time warning
about implicit functions as i2c.h would not say anything about
'i2c_read' nor 'i2c_write'. But this was not a fatal error as none of
the legacy driver would be linked in either.
Fixes: e389033f72b5 ("imx: mx6sxsabreauto: enable more dm drivers") Reviewed-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:29 +0000 (01:20 +0000)]
sunxi: Add OrangePi PC 2 initial support
The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
Add a (64-bit only) defconfig defining the required options to build
the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
and changing the differing components accordingly.
This is a preliminary device tree mostly for U-Boot's own sake, it
is expected to be updated once the official DT gets accepted upstream.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[squash the commits, update the commit message] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:28 +0000 (01:20 +0000)]
sunxi: introduce Allwinner H5 config option
The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores.
As the peripherals and the pinmuxing are almost identical, we piggy
back on the shared MACH_SUN8I_H3_H5 config symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:27 +0000 (01:20 +0000)]
sunxi: prepare for sharing MACH_SUN8I_H3 config symbol
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:26 +0000 (01:20 +0000)]
sunxi: DRAM: add Allwinner H5 support
The DRAM controller in the Allwinner H5 SoC is again very similar to
the one in the H3 and A64.
Based on the existing socid parameter, add support for this controller
by reusing the bulk of the code and only deviating where needed.
These new bits set or cleared here and there have been mostly found by
looking at DRAM register dumps after using the H5 boot0 and comparing
them to what we set in the code. So for now it's mostly unclear what
those bits actually mean - hence the missing names and comments.
Also add the delay line parameters taken from the boot0 and libdram
disassembly.
Register setup differences between H5 and H3 are courtesy of Jens Kuske.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:25 +0000 (01:20 +0000)]
SPI: SPL: sunxi: fix 64-bit build
Addresses passed on to readl and writel are expected to be of the same
size as a pointer. Change the parameter types of sunxi_spi0_read_data()
to make the compiler happy and allow a warning-free aarch64 compile.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:24 +0000 (01:20 +0000)]
sunxi: provide ARMv8 mem_map for every ARM64 board
Every armv8 board needs the memory map, so change the #ifdef to
ARM64 to avoid enumerating every single board or SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:23 +0000 (01:20 +0000)]
sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM
Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
while the first SRAM region is mapped at address 0.
With the extended physical memory support of the A80 this was changed,
so the BROM is now at address 0 and the SRAM region starts right behind
this at 64KB. This configuration seems to be called "high SRAM".
Instead of enumerating the SoCs which have copied this configuration,
let's call a spade a spade and introduce a Kconfig option for this setup.
SoCs implementing this (A80, A64 and H5, so far), can then select this
configuration.
Simplify the config header definition on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:22 +0000 (01:20 +0000)]
sunxi: configs: merge sun9i and sun50i SPL memory definitions
For some reason we were pretty conservative when defining the maximum
SPL size for the Allwinner A80(sun9i) SoC.
According to the manual the SRAM A1 is even 40KB, but the BROM
probably still has the 32 KiB load limit. For the sake of simplicity,
merge the SPL memory definitions for the A64 and A80 SoCs, since both
SoC share the BROM/SRAM A1 memory layout.
This helps to further simplify this is in the next patch.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:21 +0000 (01:20 +0000)]
sunxi: simplify ACTLR.SMP bit set #ifdef
Instead of enumerating all SoC families that need that bit set, let's
just express this more clearly: The SMP bits needs to be set on
SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
other way round, so we use ! CPU_IS_UP and ! ARM64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:20 +0000 (01:20 +0000)]
fsl: ls102x: remove redundant GENERIC_TIMER_CLK
Some Freescale boards used an extra version of the constant to hold the
Generic Timer frequency. This can easily be covered by the now unified
COUNTER_FREQUENCY constant, so remove this extra variable from those
boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:19 +0000 (01:20 +0000)]
ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY
Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the
frequency of the ARM Generic Timer (aka. arch timer).
ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same
purpose. It seems useful to unify them.
Since there are less occurences of the latter version, lets convert all
users over to COUNTER_FREQUENCY.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Andre Przywara [Thu, 16 Feb 2017 01:20:18 +0000 (01:20 +0000)]
sunxi: fix ACTLR.SMP assembly routine
If we take the liberty to use register r0 to perform our bit set, we
should be nice enough to tell the compiler about it.
Add r0 to the clobber list to avoid potential mayhem.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jagan Teki <jagan@openedev.com>
Vikas Manocha [Fri, 24 Mar 2017 21:47:44 +0000 (14:47 -0700)]
dm: avoid dropping pin control DT properties in case of SPL_PINCTRL
This patch replaces SPL_PINCTRL_FULL with SPL_PINCNTRL. It is to avoid removal
of pin control properties in case of SPL_PINCTRL. No impact in case of
SPL_PINCTRL_FULL as it depends on SPL_PINCTRL.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Mon, 20 Mar 2017 11:51:50 +0000 (12:51 +0100)]
arm: bootm: Add dm_remove_devices_flags() call to announce_and_cleanup()
This patch adds a call to dm_remove_devices_flags() to
announce_and_cleanup() so that drivers that have one of the removal flags
set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may do some
last-stage cleanup before the OS is started.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Mon, 27 Mar 2017 08:58:53 +0000 (10:58 +0200)]
dm: core: Add dm_remove_devices_flags() and hook it into device_remove()
The new function dm_remove_devices_flags() is intented for driver specific
last-stage cleanup operations before the OS is started. This patch adds
this functionality and hooks it into the common device_remove()
function.
Drivers wanting to use this feature for some last-stage removal calls,
need to add one of the DM_REMOVE_xx flags to their driver .flags.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Mon, 20 Mar 2017 11:51:48 +0000 (12:51 +0100)]
dm: core: Add flags parameter to device_remove()
This patch adds the flags parameter to device_remove() and changes all
calls to this function to provide the default value of DM_REMOVE_NORMAL
for "normal" device removal.
This is in preparation for the driver specific pre-OS (e.g. DMA
cancelling) remove support.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
Jernej Skrabec [Wed, 29 Mar 2017 23:23:14 +0000 (01:23 +0200)]
rockchip: Add support for MiQi rk3288 board
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Jernej Skrabec [Wed, 29 Mar 2017 23:23:13 +0000 (01:23 +0200)]
rockchip: cosmetic: Sort RK3288 boards
Sort rk3288 boards in alphabetical order.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 29 Mar 2017 19:19:25 +0000 (21:19 +0200)]
dts: rk3399: move rockchip, vbus-gpio properties into board-specific files
The (shared) rk3399.dtsi had defined the 'rockchip,vbus-gpio'
properties for each USB 3.0 controller.
As the GPIO usage will vary (e.g. one of those GPIOs shuts down one of
the regulators on the RK3399-Q7) between boards, we move this from the
shared dtsi into the device tree file for the EVB board which these
GPIO definitions match.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 28 Mar 2017 16:48:52 +0000 (18:48 +0200)]
defconfig: puma-rk3399: add defconfig for the RK3399-Q7 (Puma)
This commit adds the baseline defconfig for the RK3399-Q7 (Puma) SoM
(under the name 'puma-rk3399_defconfig') featuring the Rockchip RK3399
in a Qseven compatible module.
This subsumes the following changes:
* defconfig: rk3399: migrate CONFIG_SPL_LIBCOMMON_SUPPORT/CONFIG_SPL_LIBGENERIC_SUPPORT
* defconfig: rk3399-puma: add CONFIG_MMC_DW_ROCKCHIP
* defconfig: rk3399-puma: disable CONFIG_SPL_OF_PLATDATA
* defconfig: rk3399-puma: don't USE_TINY_PRINTF
* defconfig: rk3399-puma: set up CONFIG_SYS_BOARD for the RK3399-Q7
* defconfig: rk3399-puma: enable the multi-image loading via CONFIG_SPL_FIT
* defconfig: rk3399-puma: SPL should be able to boot from MMC/SD card
* defconfig: rk3399-puma: enable GMAC support
* defconfig: rk3399-puma: enable support for SPI and Winbond SPI flash
* defconfig: rk3399-puma: enable SPI as a boot-source in SPL
* defconfig: rk3399-puma: disallow non-FIT images from being loaded
* defconfig: rk3399-puma: rename to puma-rk3399
* rockchip: config: rk3399: update defconfigs and rk3399_common
For the RK3399-Q7, we want a default boot-order of SPI -> MMC -> uSD.
This both follows how the BootROM probes devices and is a sane default
for customers in device-personalisation (e.g. it allows for quick and
easy factory programming of unpersonalised devices using an SD card)
and field usage (with customer devices expected to have their firmware
either in SPI or MMC).
However, when probing multiple interfaces (according to the result
from the board_boot_order function), we need to ensure that only valid
FIT images are considered and disable the fallback to assuming that a
raw (binary-only) U-Boot image is loaded (to avoid hangs/crashes from
jumping to random content loaded from devices that are probed, but
don't contain valid image content).
By disabling the SPL_RAW_IMAGE_SUPPORT and SPL_LEGACY_IMAGE_SUPPORT
options, we ensure that raw images (indistinguishable from random
data) are not considered for booting.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
Drop CONFIG_DEBUG_UART_BOARD_INIT: Signed-off-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 28 Mar 2017 16:48:51 +0000 (18:48 +0200)]
dts: rk3399-puma: add DTS for RK3399-Q7 (Puma) SoM
The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399
in a Qseven-compatible form-factor.
These changes add a device-tree describing the board and its
interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card).
This includes the following changes from the original development:
* dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile
* dts: rk3399-puma: add gmac for the RK3399-Q7
This change enables the Gigabit Ethernet support on the RK3399-Q7.
* dts: rk3399-puma: use serial0 for stdout
* dts: rk3399-puma: prepare the sdmmc node for SPL booting
* dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash
The RK3399-Q7 (Puma) unsually (this is a build-time option for
customised boards) has an on-module SPI-flash connected to SPI1.
As of today, this is a Winbond W25Q32DW (32MBit) device.
The SPI5 controller is routed to the Q7 edge connector and provides
general-purpose SPI connectivity for customer base-boards.
With some minor improvements on integration into our outbound tree
- explicitly modelled the SPI flash as 'spiflash' under spi0
[dts: rk3399-puma: explicitly model spi-flash under spi1]
- renamed the aliases to spi0 and spi1 to allow easier use of
commands and legacy (SPL) infrastructure... i.e. the controllers
will be 0 and 1 for 'sf probe', 'sspi', etc.
[dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands]
* dts: rk3399-puma: include SPI in the spl-boot-order property
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
rockchip: spi: rk3399: move CONFIG_SPI and CONFIG_SPI_FLASH to defconfig
On the RK3399-Q7 we need to enable a number of configuration options
(e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI
and CONFIG_SPI_FLASH active.
To allow for these being defined in Kconfig (e.g. via defconfig) and
to avoid a warning on having the macro defined multiple times, we
remove them from the common header file.
Note that the rk3399-evb does not currently have the rk_spi.c driver
active (i.e. CONFIG_ROCKCHIP_SPI), so there's no change to the
evb-rk3399_defconfig as part of this change.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
For the initial validation of the RK3399-Q7 (Puma), the DDR3 has been
clocked at 666MHz (i.e. DDR3-1333) using the same (safe) settings as
used in Rockchip's MiniLoader.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 28 Mar 2017 09:03:00 +0000 (11:03 +0200)]
rockchip: rk3399: spl: make SPL boot-order configurable via /chosen
The RK3399 does not have any boot selection pins and the BootROM probes
the boot interfaces using the following boot-order:
1. SPI
2. eMMC (sdhci in DTS)
3. SD card (sdmmc in DTS)
4. USB loader
For ease of deployment, the SPL stage should mirror the boot order of
the ROM and use the same probing order (assuming that valid images can
be detected by SPL) unless instructed otherwise. The boot-order can
then be configured via the 'u-boot,spl-boot-order' property in the
chosen-node of the DTS.
While this approach is easily extensible to other boards, it is only
implemented for the RK3399 for now, as the large SRAM on the RK3399
makes this easy to fit the needed infrastructure into SPL and our
production setup already runs with DM, OF_CONTROL and BLK in SPL.
The new boot-order property is expected to be used in conjunction with
FIT images (and all legacy image formats disabled via Kconfig).
A boot-sequence with probing and fallthroughs from SPI via eMMC to SD
card (i.e. &spiflash, &sdhci, &sdmmc) has been validated on the RK3399-Q7.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Sun, 26 Mar 2017 19:09:55 +0000 (21:09 +0200)]
rockchip: rk3188: Add Radxa Rock board
The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Fix sort order in defconfig, enable CONFIG_SPL_TINY_MEMSET: Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 2 Apr 2017 15:50:28 +0000 (09:50 -0600)]
string: Provide a slimmed-down memset()
Most of the time the optimised memset() is what we want. For extreme
situations such as TPL it may be too large. For example on the 'rock'
board, using a simple loop saves a useful 48 bytes. With gcc 4.9 and
the rodata bug, this patch is enough to reduce the TPL image below the
limit.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Commit 3a649407a49b ("arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce
SPL_SYS_THUMB_BUILD") moved the THUMB_BUILD symbols from the header to
Kconfig symbols. With it still defined in the rk3188 header we end up
with a duplicate symbol and compile errors, so fix that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 24 Mar 2017 18:24:26 +0000 (19:24 +0100)]
net: gmac_rockchip: Add support for the RK3399 GMAC
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it
is a Designware GMAC core and requires similar configuration as the
RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit).
The key difference is that the register offsets (within the GRF block)
and bit-offsets (within those registers) used to hold the configuration
differ between the various RK32/33 CPUs.
This change refactors the gmac_rockchip.c driver to use a function
table (selected via driver_data) to factor out these differences. Each
function's implementation then matches the underlying processor.
Some collateral changes are needed in the definitions describing the
bits and offsets in the GRF are needed to prefix each set of symbolic
constants with the SoC name to avoid name clashes... and in doing so,
the shifts for masks and constants have been moved into the header
files for readability (and to make it easier to stay below 80 chars).
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
Fixed commit message typo s/factor our/factor out/: Signed-off-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 24 Mar 2017 18:24:25 +0000 (19:24 +0100)]
rockchip: clk: rk3399: add clocking support for Ethernet
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock
is ungated through a call to clk_set_rate(...). Even though nothing
needs to be done on the RK3399 (the clock gates are open and the clock
is external), we need to implement enough support to at least return
success to enable driver probing.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 24 Mar 2017 18:24:24 +0000 (19:24 +0100)]
rockchip: clk: rk3399: fix warnings for unused variables in SPL/non-SPL
Due to differences in the code paths for SPL and non-SPL, some static
constant structures remain unused in each build variant. This raises
warnings with recent GCC versions (we currently use GCC-6.3).
The warnings addressed in this commit (by matching #if conditions for
the variable definition with their uses) are:
* for the SPL build:
drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=]
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
^~~~~~~~~~~~~
drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=]
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
^~~~~~~~~~~~~
* for the non-SPL build:
drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=]
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
^~~~~~~~~~~~~
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 24 Mar 2017 18:24:23 +0000 (19:24 +0100)]
rockchip: pinctrl: rk3399: add GMAC (RGMII only) support
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII signalling mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* adds the required defines (in the GRF support) for configuring the
GPIOC pins for RGMII
* configures the RGMII pins (in GPIOC) when requested via pinctrl
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log