Tom Rini [Fri, 11 May 2018 15:45:28 +0000 (11:45 -0400)]
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze:
- Align defconfig
zynq:
- Rework fpga initialization and cpuinfo handling
zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING
zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation
mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode
nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params
mmc: sdhci: Read capabilities register1 and update host caps
This patch reads the capabilities register1 and update the host
caps accordingly for mmc layer usage. This patch mainly reads
for UHS capabilities inorder to support SD3.0.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support to disable clock if clk_disable
was set and then enable or set clock if the clock was changed
or clock was disabled when clock needs to be enabled.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Thu, 3 May 2018 06:50:54 +0000 (12:20 +0530)]
mmc: Changed the datatype of the variable to handle 64-bit arch
This patch changed the datatype of variable "start" from uint to ulong
to work properly on 64-bit machines as well. Also the return type of
get_timer() function is ulong.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 12 Apr 2018 15:39:46 +0000 (17:39 +0200)]
arm: zynqmp: Add ZynqMP minimal R5 support
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.
This configuration with uart1 was tested on zcu100-revC.
Model: Xilinx ZynqMP R5
DRAM: 512 MiB
WARNING: Caches not enabled
MMC:
In: serial@ff010000
Out: serial@ff010000
Err: serial@ff010000
Net: Net Initialization Skipped
No ethernet found.
ZynqMP r5>
There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no && bootelf -p 20000000
cpu 4 disable && cpu 4 release 10000000 lockstep
or
cpu 4 disable && cpu 4 release 10000000 split
2. Load via jtag when directly to R5
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:52 +0000 (14:18 +0200)]
tools: zynqmpimage: Add bif support
The officially described way to generate boot.bin files for ZynqMP is to
describe the contents of the target binary using a file of the "bif"
format. This file then links to other files that all get packed into a
bootable image.
This patch adds support to read such a .bif file and generate a respective
ZynqMP boot.bin file that can include the normal image and pmu files, but
also supports image partitions now. This makes it a handy replacement for
the proprietary "bootgen" utility that is currently used to generate
boot.bin files with FSBL.
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:51 +0000 (14:18 +0200)]
MAINTAINERS: Declare tools/zynqmp* as Xilinx maintained
The zynqmpimage.c and the new zynqmpbif.c files are all maintained by
Xilinx for the Zynq platforms. Let's match them accordingly
in the MAINTAINERS file.
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Fri, 13 Apr 2018 12:18:49 +0000 (14:18 +0200)]
tools: zynqmpimage: Add partition read support
The zynqmp image format has support for inline partitions which are
used by FSBL to describe payloads that are loaded by FSBL itself.
While we can't create images that contain partitions (yet), we should
still at least be able to examine them and show the user what's inside
when we analyze an image created by bootgen.
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fills the MMU map for DDR at run time based on information read
from Device Tree or automatically detected from static configuration.
The patch is needed because for systems which has for example 1GB of memory
but MMU map is 2GB there could be spurious accesses which was seen in past
when mapping is not fitting with actual memory installed.
Michal Simek [Thu, 19 Apr 2018 13:43:50 +0000 (15:43 +0200)]
arm64: zynqmp: Enable cadence WDT for zcu100
Enable watchdog on zcu100 to make sure if there is a bug in the u-boot
there is proper reset.
Watchdog expires and PMU fw is informed and based on setting proper
action is taken.
The patch is enabling reset-on-timeout feature and also fixing fixed
clock rate for watchdog where 100MHz is max (and also default) clock value.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 19 Apr 2018 13:22:04 +0000 (15:22 +0200)]
watchdog: cadence: Show used timeout value
Debug message was showing timeout value which was passed to start
function but there is a checking if this value can be setup.
The patch is moving this debug printf function below checking.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
nand: zynq: Send address cycles as per onfi parameter page
Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 6 Apr 2018 11:32:52 +0000 (13:32 +0200)]
scsi: ceva: Convert driver to use UCLASS_AHCI instead of SCSI
In v2018 the patch
"dm: ahci: Correct uclass private data"
(sha1: bfc1c6b4838501d10aa48c0e92eaf70976f4b2dd)
was causing an issue for ceva_sata.
But this issue is not in v2018.05-rc1 but still converting to
UCLASS_AHCI would make more sense.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini [Mon, 7 May 2018 21:02:21 +0000 (17:02 -0400)]
SPDX: Convert a few files that were missed before
As part of the main conversion a few files were missed. These files had
additional whitespace after the '*' and before the SPDX tag and my
previous regex was too strict. This time I did a grep for all SPDX tags
and then filtered out anything that matched the correct styles.
Fixes: 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style") Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
Without the patch gcc 8 produces:
warning: ignoring attribute ‘noreturn’ because it conflicts with
attribute ‘const’ [-Wattributes]
int ____ilog2_NaN(void);
So let's update the include from Linux kernel v4.16.
This removes static checks of ilog2() arguments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
tools/file2include: create Linux style SPDX header
file2include is used to convert a binary file to a C include.
With the patch the SPDX header is written to the first line as
expected by scripts/checkpatch.pl.
Lukasz Majewski [Wed, 2 May 2018 14:10:54 +0000 (16:10 +0200)]
bootcount: spl: Extend SPL to support bootcount incrementation
This patch adds support for incrementation of the bootcount in SPL.
Such feature is necessary when we do want to use this feature with
'falcon' boot mode (which loads OS directly in SPL).
Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
armv8/fsl-lsch2: make the workaround for PIN MUX erratum A010539 robust
Mask HRESET_B after cleared the the RCW_SRC, because in the workaround
we override the RCW_SRC and if HRESET_B is issued after the override
then SoC cannot find valid RCW as the RCW_SRC was overwritten and
result in hang. So we need to mask HRESET_B in case user asserts it,
and the PORESET_B should be asserted which leads to resampling of
cfg_rcw_src pins and loading of correct RCW_SRC.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
armv8: sec_firmware: Remove JR3 from device tree node in all cases
JR3 was getting removed from device tree only if random number
generation was successful. However, if SEC firmware is present,
JR3 should be removed from device tree node irrespective of the
random seed generation as SEC firmware reserves it for it's use.
Not removing it in case of random number generation failure causes
the kernel to crash.
Random number generation was being called twice. This is not
required. If SEC firmware is running, SIP call can be made to the SEC
firmware to get the random number. This call itself would return
failure if function is not supported. Duplicate calling of random
number generation function has been removed.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Jagdish Gediya [Fri, 23 Mar 2018 21:25:51 +0000 (02:55 +0530)]
mtd: nand: fsl_ifc: Fix eccstat array overflow for IFC ver >= 2.0.0
Number of ECC status registers i.e. (ECCSTATx) has been increased in
IFC version 2.0.0 due to increase in SRAM size. This is causing
eccstat array to over flow.
So, replace eccstat array with u32 variable to make it fail-safe and
independent of number of ECC status registers or SRAM size.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Rajat Srivastava [Thu, 22 Mar 2018 08:00:55 +0000 (13:30 +0530)]
spi: fsl_qspi: Introduce is_controller_busy function
Some SoCs have different endianness of QSPI IP if compared
to endianness of core. The function is_controller_busy()
checks if the QSPI controller is busy or not, considering
the endianness of the QSPI IP.
Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This patch solves assert failed displayed in the console during a boot.
The root cause is that the ubifs_inode is not already allocated when
ubifs_printdir and ubifs_finddir functions are called.
Trace showing the issue:
feed 'boot.scr.uimg', ino 94, new f_pos 0x17b40ece
dent->ch.sqnum '7132', creat_sqnum 3886945402880
UBIFS assert failed in ubifs_finddir at 436
INODE ALLOCATION: creat_sqnum '7129'
Found U-Boot script /boot.scr.uimg
Tom Rini [Tue, 1 May 2018 16:32:37 +0000 (12:32 -0400)]
bootm.c: Correct the flush_len used in bootm_load_os()
In do_bootm_states when doing BOOTM_STATE_LOADOS we use load_end
uninitialized and Coverity notes this now. This however leads down
another interesting path. We pass this pointer to bootm_load_os and
that in turn uses this uninitialized value immediately to calculate the
flush length, and is wrong. We do not know what load_end will be until
after bootm_decomp_image is called, so we must only set flush_len after
that. All of this also makes it clear that the only reason we pass a
pointer for load_end to bootm_load_os is so that we can call lmb_reserve
on success. Rather than initialize load_end to 0 in do_bootm_states we
can just call lmb_reserve ourself.
Reported-by: Coverity (CID: 175572) Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
arm: bitops: fix find_next_zero_bit() for case size < 32
find_next_zero_bit() incorrectly handles cases when:
- total bitmap size < 32
- rest of bits to process
static inline int find_next_zero_bit(void *addr, int size, int offset)
{
unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
[1]
goto found_first;
if (~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size & ~31UL) {
tmp = *(p++);
if (~tmp)
goto found_middle;
result += 32;
size -= 32;
}
[2]
if (!size)
return result;
tmp = *p;
found_first:
[3] tmp |= ~0UL >> size;
^^^ algo can reach above line from from points:
[1] offset > 0 and size < 32, tmp[offset-1..0] bits set to 1
[2] size < 32 - rest of bits to process
in both cases bits to search are tmp[size-1..0], but line [3] will simply
set all tmp[31-size..0] bits to 1 and ffz(tmp) below will fail.
example: bitmap size = 16, offset = 0, bitmap is empty.
code will go through the point [2], tmp = 0x0
after line [3] => tmp = 0xFFFF and ffz(tmp) will return 16.
found_middle:
return result + ffz(tmp);
}
Fix it by correctly seting tmp[31..size] bits to 1 in the above case [3].
Mario Six [Fri, 27 Apr 2018 12:53:37 +0000 (14:53 +0200)]
pci: Don't use pci_indirect when DM is active
Declaration of indirect PCI bridges is not compatible with DM: Both
define PCI operations, but in different ways. Hence, don't use indirect
bridges if DM is active.
Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
Ramon Fried [Fri, 20 Apr 2018 19:39:50 +0000 (22:39 +0300)]
db410c: set clk node to be probed before relocation
The clock node is used by the serial driver and it's needed
before relocation.
This patch ensures that the msm-serial driver can actually
use the clock node.
Signed-off-by: Ramon Fried <ramon.fried@linaro.org>
STiH410 has 2 PHYs wired on the DWC3 IP, USB2 and USB3 PHYs.
As currently no U-boot driver is available for the USB3 PHY and to avoid
issue during DWC3 drive probe, we use DWC3 IP with only USB2 PHY
using stih410-b2260-u-boot.dtsi file.
Sam Protsenko [Thu, 19 Apr 2018 20:57:30 +0000 (23:57 +0300)]
arm: ti: boot: Extract PARTS_DEFAULT to boot.h
Eliminate code duplication: the same PARTS_DEFAULT was defined in
am57xx_evm.h and in dra7xx_evm.h. Extract it to environment/boot.h and
use in all OMAP5-based boards.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Marek Vasut [Sun, 15 Apr 2018 11:15:33 +0000 (13:15 +0200)]
tools: socfpga: Add SFP image V1 support
Add support for the SoCFPGA header v1 , which is used on Arria 10.
Thus far the mkimage-socfpga image only supported header format v0
used on Cyclone V and Arria V, but is not supported on Arria 10.
The layout of the v0 and v1 header is similar, yet there are a few
differences, see the patch body for details.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Chin Liang See <chin.liang.see@intel.com>
Marek Vasut [Sun, 15 Apr 2018 11:15:33 +0000 (13:15 +0200)]
image: socfpga: Add SFP image version 1 definition
Add support for the SoCFPGA header v1, which is used on Arria 10.
The layout of the v0 and v1 header is similar, yet there are a few
differences which make it incompatible with previous v0 header, so
add a new entry.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Chin Liang See <chin.liang.see@intel.com>
Marek Vasut [Sun, 15 Apr 2018 11:15:33 +0000 (13:15 +0200)]
ARM: socfpga: Add boot trampoline for Arria10
The Arria10 uses slightly different boot image header than the Gen5 SoCs,
in particular the header itself contains an offset from the start of the
header to which the Arria10 jumps. This offset must not be negative, yet
the header is placed at offset 0x40 of the bootable binary. Therefore, to
jump into U-Boot, add a trampoline just past the Arria10 boot header and
point to this trampoline at fixed offset from the header generated using
the mkimage -T socfpgaimage_v1 . Note that it is not needed to jump back
to offset 0x0 of the image, it is possible to jump directly at the reset
label and save processing two instructions.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Chin Liang See <chin.liang.see@intel.com>
Neil Armstrong [Mon, 23 Apr 2018 14:19:23 +0000 (16:19 +0200)]
adc: add Amlogic Meson SAR ADC driver
This patch adds the driver for the Amlogic Meson Successive Approximation
Register (SAR) A/D Converter based on the Linux IIO driver thanks to the
great work of Martin Blumenstingl.
The driver has been adapted to U-Boot and the ADC UClass.
This patch depends on the regmap "regmap: add regmap_update_bits() helper"
patch and has been tested using the newly introducted "adc" CLI command
in the "cmd: add ADC cli commands" patch.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add regulator driver for STM32 voltage reference buffer which can be
used as voltage reference for ADCs, DACs and external components through
dedicated VREF+ pin.
configs: stm32mp15_basic: Set regulator relative flags
Enable DM_REGULATOR_STPMU1 flag to activate regulator
driver for STM32MP15 SoC and CMD_REGULATOR flag to be
able to set/get regulator state int U-boot command line.
Disable PMIC_CHILDREN as this flag is not needed in SPL
for STM32MP1.
Enable support for the regulator functions of the STPMU1X PMIC. The
driver implements get/set api for the various BUCKS and LDOs supported
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
projects / u-boot / log