Tom Rix [Sun, 27 Sep 2009 16:10:09 +0000 (11:10 -0500)]
Add support for Eukrea CPU9260/CPU9G20 SBC
these boards are built around Atmel's AT91SAM9260/9G20 and have
up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND
and include a 10/100 Ethernet PHY in RMII mode.
Signed-off-by: Eric Benard <eric@eukrea.com> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
The DM365 config was using the 'CONFIG_CMD_SAVEENV' flag.
This is already included when we include the
config_cmd_default.h header file. So this flag is removed.
Also another flag to enable NAND functions was being
enabled incorrectly.
This patch does the following
1) Enables the NAND driver which is now available.
2) Enables the 'CONFIG_MTD_DEVICE' as without this the
compilation will fail
3) We now have a safe place to store environment and defines
an offset where this can be stored. This offset value is such that it is after
the location where U-Boot is flashed using TI flash utilities.
4) Enables Bootdelay
5) Increases malloc() arena size. Manufacturers are coming out with
NAND with large blocks sizes of upto 1 MiB. It has been noticed that
as the block size of the NAND used is increased, if this particular
value is not increased, the NAND driver will output out of memory
errors.
TI DaVinci: DM646x: Initial Support for DM646x SOC
DM646x is an SOC from TI which has both an ARM and a DSP.
There are multiple variants of the SOC mainly dealing with different
core speeds.
This patch adds the initial framework for the DM646x SOC.
TI DaVinci: DM6446: Fix Compilation error in NAND mode
The Default mode that is built for the Davinci DVEVM happens
to be the NOR mode.
When we want to build for the NAND mode, we get a compilation
error. This is overcome by defining the CONFIG_MTD_DEVICE
flag in the NAND mode.
The image built for NAND mode was successfully tested on the
DaVinci DM6446 EVM.
Tom Rix [Thu, 10 Sep 2009 19:27:57 +0000 (15:27 -0400)]
OMAP3 Move cache routine to cache.S
v7_flush_dcache_all, because it depends on omap ROM code is not
generic. Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.
Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S. This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.
The conversion from cache.c to cache.S was done most through
disassembling the uboot binary. The only significant change was
to change the comparision for the return of get_cpu_rev from
cmp r0, #0
beq earlier_than_label
Which was lost information to
cmp r0, #CPU_3XX_ES20
blt earlier_than_label
The paths through the enable routine were verified by
adding an infinite loop and seeing the hang. Then
removing the infinite loop and seeing it continue.
The disable routine is similar enough that it was not
tested with this method.
Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.
This patch removes the asm/sizes.h header file from being
included in the DaVinci SOC configs.
References to SZ_xx have been replaced by appropriate
bit shifted values.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Wolfgang Denk <wd@denx.de>
Ed Swarthout [Thu, 9 Oct 2008 06:27:18 +0000 (01:27 -0500)]
Leave x86emu op code tables in default section
Forcing the tables into got2 caused extra relocation when using -mrelocatable.
This patch requires any board defining CONFIG_BIOSEMU to use -mrelocatable.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Jin Zhengxiong <Jason.Jin@freescale.com>
Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an arbitrary number of mii buses.
This feature is useful when your board uses different mii buses for different
phys and all (or a part) of these buses are implemented via bit-banging mode.
The driver requires that the following macros should be defined into the board
configuration file:
CONFIG_BITBANGMII - Enable the miiphybb driver
CONFIG_BITBANGMII_MULTI - Enable the multi bus support
If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
to define at least the following macros:
MII_INIT - Generic code to enable the MII bus (optional)
MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
MDIO_ACTIVE - Activate the MDIO pin as out pin
MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
MDIO_READ - Read the MDIO pin
MDIO(v) - Write v on the MDIO pin
MDC_DECLARE - Declaration needed to access to the MDC pin (optional)
MDC(v) - Write v on the MDC pin
The previous macros make the driver compatible with the previous version
(that didn't support the multi-bus).
When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
the bb_miiphy_buses[] array with a record for each required bus and declare
the bb_miiphy_buses_num variable with the number of mii buses.
The record (struct bb_miiphy_bus) has the following fields/callbacks (see
miiphy.h for details):
char name[] - The symbolic name that must be equal to the MII bus
registered name
int (*init)() - Initialization function called at startup time (just
before the Ethernet initialization)
int (*mdio_active)() - Activate the MDIO pin as output
int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
int (*set_mdio)() - Write the MDIO pin
int (*get_mdio)() - Read the MDIO pin
int (*set_mdc)() - Write the MDC pin
int (*delay)() - Delay function
void *priv - Private data used by board specific code
NULL is an absolute value and should not be relocated.
After this correction code like:
void weak_fun(void) __attribute__((weak));
printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.
Peter Tyser [Wed, 7 Oct 2009 16:45:00 +0000 (11:45 -0500)]
85xx: Ensure BSS segment isn't linked at address 0
When U-Boot is relocated from flash to RAM pointers are modified
accordingly. However, pointers initialzed with NULL values should not
be modified so that they maintain their intended NULL value. If the
BSS segment is linked at address 0 its address will not be
updated as necessary during relocation.
This is a temporary workaround. The end goal is to add support to
U-Boot to dynamically locate the BSS at an arbitrary address at
runtime. When the ability to fixup the BSS inteligently is
added, this workaround can be removed and the 85xx link script
can put the BSS at a fixed address at link time.
Detlev Zundel [Wed, 7 Oct 2009 14:38:05 +0000 (16:38 +0200)]
tqm5200: Correct comment and code in post_hotkeys_pressed.
This fixes the code and the comment according to the original intent of
doing an intensive memory test when PSC6_3 is pulled low on the STK52xx.
Notably PORT_CONFIG will be overridden with this correct code now,
so beware.
The original code only worked by coincidence depending on the PORT_CONFIG
setting from the header file. The new code was tested to ensure that the
(undocumented) memory test still works on the STK52x.
Signed-off-by: Detlev Zundel <dzu@denx.de> CC: Martin Krause <Martin.Krause@tqs.de>
Minor white-space cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Sun, 4 Oct 2009 20:56:08 +0000 (22:56 +0200)]
mpc512x: fix fixed_sdram() init code.
Commit 054197ba and later fixes used an array to initialize some of
the MDDRC parameters; however, the use of an array turned out to be a
bad idea as it was not possible to correlate structure entries to
array indices in readable and reliable way. Now we use a struct
instead, which makes this self-explanatory.
Niklaus Giger [Sun, 4 Oct 2009 18:04:22 +0000 (20:04 +0200)]
ppc4xx: respect 80-chars per line in ppc*.h files
After running checkstyle.pl on the three previous patches I noted that in
the *.h files there were a lot of long lines. This patch solves this problem.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
Niklaus Giger [Sun, 4 Oct 2009 18:04:21 +0000 (20:04 +0200)]
ppc4xx: Rework cmd reginfo
The command "reginfo" got an overhaul for the ppc4xx. It dumps all the
relevant HW configuration registers (address, symbolic name, content).
This allows to easily detect errors in *.h files and changes in the HW
configuration.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
Niklaus Giger [Sun, 4 Oct 2009 18:04:19 +0000 (20:04 +0200)]
ppc4xx: Cleanup some HW register names
Here you find all the changes in the include directory for new register names
and adapting other ones to the names used by AMCC in their manuals, e.g.
For 440EPx/GRPPC440EPx/GRX, Revision 1.15 – September 22, 2008
For PPC405GP Embedded Processor, Revision 1.02 – March 22, 2006
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Fri, 2 Oct 2009 12:35:16 +0000 (14:35 +0200)]
ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scan
This message is printed upon PCIe bus scan, not only upon error, but also
if no PCIe device is detected at all. Since this is not an error, let's
remove this message in this case. We already have the message
"link is not up." if there is no PCIe device present.
Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
Mike Nuss [Mon, 5 Oct 2009 16:33:28 +0000 (12:33 -0400)]
PPC4xx: Denali core: Fix incorrect DDR row bits
The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.
Signed-off-by: Mike Nuss <mike@terascala.com> Signed-off-by: Stefan Roese <sr@denx.de>
Ben Warren [Mon, 5 Oct 2009 05:37:03 +0000 (22:37 -0700)]
Convert SMC91111 Ethernet driver to CONFIG_NET_MULTI API
All in-tree boards that use this controller have CONFIG_NET_MULTI
added
Also:
- changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111
- cleaned up line lengths
- modified all boards that override weak function in this driver
- modified all eeprom standalone apps to work with new driver
- updated blackfin standalone EEPROM app after testing
Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
James Clough [Thu, 10 Sep 2009 07:11:50 +0000 (09:11 +0200)]
net: Fix problem with 405EZ ethernet interrupt
On 405EZ the RX-/TX-interrupts are coalesced into one IRQ bit in the
UIC. We need to acknowledge the RX-/TX-interrupts in the
SDR0_ICINTSTAT reg as well.
This problem was introduced with commit d1631fe1 [ppc4xx: Consolidate PPC4xx UIC defines]
Signed-off-by: James Clough <james@rtetc.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Mike Frysinger [Wed, 2 Sep 2009 08:18:55 +0000 (04:18 -0400)]
net: add random_port() prototype
The random_port() is meant to be used by other net code, but without a
prototype, we get fun warnings like:
dns.c: In function 'DnsSend':
dns.c:89: warning: implicit declaration of function 'random_port'
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Peter Tyser [Mon, 21 Sep 2009 16:20:37 +0000 (11:20 -0500)]
ppc: Remove reloc_off field from global_data structure
Now that proper relocation is supported, the reloc_off field is no longer
necessary.
Note that the location of the standalone application jump table pointer
in the global data structure is affected by this change, breaking
execution of standalone applications compiled for previous versions of
U-Boot.
We therefore increment XF_VERSION to 6
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
These architectures don't need relocation fixups, so reduce their
codesize a bit by defining CONFIG_RELOC_FIXUP_WORKS.
Also remove the reloc_off field from their global data structures
as it is no longer needed.
Note that the location of the standalone application jump table pointer
in the global data structure is affected by this change, breaking
execution of standalone applications compiled for previous versions of
U-Boot. We will therefore increment XF_VERSION in the next commit,
which also touches this area.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
Peter Tyser [Mon, 21 Sep 2009 16:20:36 +0000 (11:20 -0500)]
Conditionally perform common relocation fixups
Add #ifdefs where necessary to not perform relocation fixups. This
allows boards/architectures which support relocation to trim a decent
chunk of code.
Note that this patch doesn't add #ifdefs to architecture-specific code
which does not support relocation.
Peter Tyser [Mon, 21 Sep 2009 16:20:32 +0000 (11:20 -0500)]
fpga: Remove relocation fixups
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups. Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.
Peter Tyser [Mon, 21 Sep 2009 16:20:26 +0000 (11:20 -0500)]
ppc: Check for compilers that don't support relocation
Certain ppc compilers are known not to generate the .fixup section
properly. The .fixup section is necessary to create a relocatable
U-Boot image. A basic check for the existence of the .fixup section
should hopefully catch the majority of broken compilers which don't
support relocation.
Peter Tyser [Mon, 21 Sep 2009 16:20:25 +0000 (11:20 -0500)]
ppc: Enable full relocation to RAM
The following changes allow U-Boot to fully relocate from flash to
RAM:
- Remove linker scripts' .fixup sections from the .text section
- Add -mrelocatable to PLATFORM_RELFLAGS for all boards
- Define CONFIG_RELOC_FIXUP_WORKS for all boards
Previously, U-Boot would partially relocate, but statically initialized
pointers needed to be manually relocated.
This patch adds support to detect the amount of DDR2 SDRAM
on PMC440 modules. Detection is done by probing through
a list of available and supported hardware configurations
from 1GByte down to 256MB.
The static TLB entry is replaced by dynamically created entries.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Mon, 28 Sep 2009 15:33:45 +0000 (17:33 +0200)]
ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.
Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.
Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Felix Radensky <felix@embedded-sol.com> Cc: Grant Erickson <gerickson@nuovations.com> Cc: Pieter Voorthuijsen <pv@prodrive.nl>
Felix Radensky [Sun, 27 Sep 2009 21:56:12 +0000 (23:56 +0200)]
ppc4xx: Reorganize DDR2 ECC handling
Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.
Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
Mike Frysinger [Mon, 21 Sep 2009 22:04:49 +0000 (18:04 -0400)]
Blackfin: bf533-ezkit: update env location
The u-boot image has outgrown the current space and overflowed into the
env sector. So move the env to the next available sector (we've already
allocated the first few sectors anyways for u-boot).
Mingkai Hu [Wed, 23 Sep 2009 07:20:38 +0000 (15:20 +0800)]
On-chip ROM boot: MPC8536DS support
The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.
The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.
The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Wed, 23 Sep 2009 07:20:37 +0000 (15:20 +0800)]
NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Fri, 25 Sep 2009 15:14:11 +0000 (11:14 -0400)]
sbc8548: reclaim wasted sector in boot flash
By nature of being based off the MPC8548CDS board, this
board inherited an ENV_SIZE setting of 256k. But since
it has a smaller flash device (8MB soldered on), it has
a native sector size of 128k, and hence the ENV_SIZE was
causing 2 sectors to be used for the environment.
By removing the unused sector, we can push TEXT_BASE up
closer to the end of address space and reclaim that
sector for any other application. This also fixes the
mismatch between TEXT_BASE and MONITOR_LEN reported by
Kumar earlier.
Since this board also supports the ability to boot off
the 64MB SODIMM flash, this change is forward looking
with that in mind; i.e. the settings for MONITOR_LEN
and ENV_SIZE will work when the 512k sectors of the
SODIMM flash are used for alternate boot in the future.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 29 Sep 2009 02:38:00 +0000 (21:38 -0500)]
ppc/85xx: Clean up immap_85xx.h
* Converted all white space to tabs
* Converted all types to u8/u16/u32
* Reduce lines to fit in 80 columns
* Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Scott Wood [Mon, 28 Sep 2009 21:33:18 +0000 (16:33 -0500)]
NAND: davinci: Fix warnings when 4-bit ECC not used
I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
The commit ecad289fc6bd9d89ef4d5093cc7b6fd712fd0d29 (OneNAND: Remove
unused read_spareram and add unlock_all as kernel does) forgot to remove
a local reference to read_spareram in board/micronas/vct/ebi_onenand.c,
which causes the following build failure when configured with OneNAND:
ebi_onenand.c: In function 'onenand_board_init':
ebi_onenand.c:196: error: 'struct onenand_chip' has no member named 'read_spareram'
make[1]: *** [ebi_onenand.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [board/micronas/vct/libvct.a] Error 2
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Stefan Roese [Thu, 24 Sep 2009 11:59:57 +0000 (13:59 +0200)]
ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
__i2c_read always ends with a STOP condition thereby releasing
the bus. It is cleaner to do the STOP magic in i2c_read(), like
i2c_write() does. This may also help future multimaster systems which
wants to hold on to the bus until all transactions are finished.
fsl_i2c: Impl. AN2919, rev 5 to calculate FDR/DFSR
The latest AN2919 has changed the way FDR/DFSR should be calculated.
Update the driver according to spec. However, Condition 2
is not accounted for as it is not clear how to do so.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Wolfgang Grandegger <wg@grandegger.com>
Kim Phillips [Fri, 25 Sep 2009 23:19:44 +0000 (18:19 -0500)]
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields
some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.
Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.
also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.
also start to use i/o accessors.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Paul Gortmaker [Mon, 21 Sep 2009 21:44:51 +0000 (17:44 -0400)]
sbc8349: tidy up Makefile to use new configuration script.
Commit 804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the board config header. This takes advantage of
that for the sbc8349 board.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Wed, 16 Sep 2009 19:21:59 +0000 (23:21 +0400)]
mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUs
This patch fixes various ethernet issues with gigabit links handling
in U-Boot. The workarounds originally implemented by Kim Phillips for
Linux kernel.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Though, it appears that QE Ethernet in Gigabit mode can't transmit
large packets when it tries to work with a data in LBC SDRAM (memtest
didn't discover any issues, is LBC SDRAM just too slow?).
With this patch we can still use the board without DDR memory, but
if DDR is available, we don't use LBC SDRAM.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Ken MacLeod [Fri, 11 Sep 2009 20:16:18 +0000 (15:16 -0500)]
cmd_fdt.c: fix parse of byte streams and strings
Commit 4abd844d8e extended the fdt command parser to handle property
strings which are split across multiple arguments but it was broken for
byte streams and strings.
Byte stream parsing:
* Fixes where it would terminate early or go into an endless loop.
* Fixes a 0x00 being inserted into the data if there is a space after
'[' or a separate argument.
* Fixes dereferencing the argument pointer after the last argument.
* Checks for bad characters.
String parsing:
* Treat multiple arguments as a string list. This fixes an issue where
only the last argument was stored.
mucmc52, uc101: delete ata@3a00 node, if no CF card is detected
U-Boot can detect if an IDE device is present or not.
If not, and this new config option is activated, U-Boot
removes the ATA node from the DTS before booting Linux,
so the Linux IDE driver does not probe the device and
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.
- As these boards are similiar, collect common config options
in manroland/common.h and manroland/mpc52xx-common.h
for mpc5200 specific common options for this manufacturer.
- add OF support
- update default environment
Signed-off-by: Heiko Schocher <hs@denx.de>
Minor edit of commit message.
Wolfgang Denk [Thu, 24 Sep 2009 22:57:49 +0000 (00:57 +0200)]
Fix "ppc/85xx: Clean up use of LAWAR defines" breakage
Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_
defines were only enabled for the 83xx platform, but they are also
needed on MPC512x system. Enabling these for E300 systems seems thus
more appropriate.
Kumar Gala [Thu, 19 Mar 2009 07:46:19 +0000 (02:46 -0500)]
ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms. Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks. We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 17 Sep 2009 06:52:37 +0000 (01:52 -0500)]
ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
the core not longer controls the enabling of the timebase. We now need
to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 19 Mar 2009 07:39:17 +0000 (02:39 -0500)]
ppc/p4080: Add various p4080 related defines (and p4040)
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style. Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
projects / u-boot / log