Heiko Schocher [Thu, 5 Mar 2015 08:02:23 +0000 (09:02 +0100)]
travis.yml: some adaptions
- adapt to build with eldk-5.4
- add more targets for building with buildman:
- freescale -x arm,m68k,aarch64
- arm1136
- arm1176
- arm720t
- arm920t
- davinci
- kirkwood
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Roger Meier <r.meier@siemens.com>
Marcel Ziswiler [Wed, 4 Mar 2015 13:57:31 +0000 (14:57 +0100)]
arm: pxa: introducing cpuinfo display for marvell pxa270m
According to table 2-3 on page 87 of Marvell's latest PXA270
Specification Update Rev. I from 2010.04.19 [1] there exists a breed of
chips with a new CPU ID for PXA270M A1 stepping which our latest
Colibri PXA270 V2.4A modules actually have assembled. This patch helps
in correctly identifying those chips upon boot as well which then looks
as follows:
Simon Glass [Tue, 3 Mar 2015 15:03:02 +0000 (08:03 -0700)]
ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACK
Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f(). Adjust the
code paths in these cases to be correct. In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment). In these cases switch to CONFIG_SPL_STACK_R. In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM Tested-by: Matt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 3 Mar 2015 15:03:00 +0000 (08:03 -0700)]
arm: spl: Allow board_init_r() to run with a larger stack
At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and
environment) require a lot of stack, some boards set CONFIG_SPL_STACK to
point into SDRAM. They then set up SDRAM very early, before board_init_f(),
so that the larger stack can be used.
This is an abuse of lowlevel_init(). That function should only be used for
essential start-up code which cannot be delayed. An example of a valid use is
when only part of the SPL code is visible/executable, and the SoC must be set
up so that board_init_f() can be reached. It should not be used for SDRAM
init, console init, etc.
Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new
address before board_init_r() is called in SPL.
The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README.
Signed-off-by: Simon Glass <sjg@chromium.org>
For version 1: Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Tue, 3 Mar 2015 15:02:58 +0000 (08:02 -0700)]
arm: spl: Avoid setting up a duplicate global data structure
This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.
As an interim measure, remove it only if CONFIG_DM is not defined. This
allows us to press ahead with driver model in SPL and allow the stragglers
to catch up.
Simon Glass [Tue, 3 Mar 2015 15:02:57 +0000 (08:02 -0700)]
arm: Reduce the scope of lowlevel_init()
This function has grown into something of a monster. Some boards are setting
up a console and DRAM here in SPL. This requires global_data which should be
set up in one place (crt0.S).
There is no need for SPL to use s_init() for anything since board_init_f()
is called immediately afterwards.
board: samsung: reserve memory for the secure firmware
Since more than one board requires memory reservation
for the secure firmware, the reservation code can be
made in a common code.
Now, to reserve some part of the the last bank,
board config should define:
- CONFIG_TZSW_RESERVED_DRAM - len in bytes
- CONFIG_NR_DRAM_BANKS - number of memory banks
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Hyungwon Hwang <human.hwang@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Lukasz Majewski [Thu, 26 Feb 2015 12:23:49 +0000 (13:23 +0100)]
MAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibility
After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.
Raul Cardenas [Fri, 27 Feb 2015 17:22:06 +0000 (11:22 -0600)]
imx6: Added DEK blob generator command
Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.
During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process, is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.
Commands added
--------------
dek_blob - encapsulating DEK as a cryptgraphic blob
Commands Syntax
---------------
dek_blob src dst len
Encapsulate and create blob of a len-bits DEK at
address src and store the result at address dst.
Fabio Estevam [Mon, 23 Feb 2015 12:09:09 +0000 (09:09 -0300)]
mx35: Fix boot hang by avoiding vector relocation
Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx35
does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX35 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
Fabio Estevam [Mon, 23 Feb 2015 12:09:08 +0000 (09:09 -0300)]
mx31: Fix boot hang by avoiding vector relocation
Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx31
does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX31 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
Masahiro Yamada [Thu, 26 Feb 2015 17:27:06 +0000 (02:27 +0900)]
ARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macros
Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs. The line
size is still 128 byte. Thus, the way size is 32KB/64KB for old/new
SoCs.
To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB. It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.
Masahiro Yamada [Thu, 26 Feb 2015 17:27:05 +0000 (02:27 +0900)]
ARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initialization
This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.
Masahiro Yamada [Thu, 26 Feb 2015 17:27:03 +0000 (02:27 +0900)]
ARM: UniPhier: switch to 1CS support card
The 3CS support card (CONFIG_DCC_MICRO_SUPPORT_CARD) used to be used
very often before, but it is recently getting a minority. Swith to
the 1CS support card (CONFIG_PFC_MICRO_SUPPORT_CARD).
Masahiro Yamada [Thu, 26 Feb 2015 17:27:02 +0000 (02:27 +0900)]
ARM: UniPhier: support 1CS support card for all the UniPhier SoCs
Two support card variants are used with UniPhier reference boards:
- 1 chip select support card (original CPLD)
- 3 chip selects support card (ARIMA-compatible CPLD)
Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.
Masahiro Yamada [Thu, 26 Feb 2015 17:27:01 +0000 (02:27 +0900)]
ARM: UniPhier: switch to xHCI for PH1-Pro4
PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously. Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.
Masahiro Yamada [Thu, 26 Feb 2015 17:26:59 +0000 (02:26 +0900)]
ARM: UniPhier: add xHCI device nodes to PH1-Pro4 device tree
Each USB port corresponds to the following IP core:
port0: xHCI (0x65a00000) SS+HS
port1: xHCI (0x65c00000) HS (SS PHY is not implemented)
port2: EHCI (0x5a800100) HS
port3: EHCI (0x5a810100) HS
Masahiro Yamada [Thu, 26 Feb 2015 17:26:54 +0000 (02:26 +0900)]
ARM: UniPhier: remove EHCI platform devices
Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers. We still keep UART platform devices because they might
be useful for SPL.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
Masahiro Yamada [Thu, 26 Feb 2015 17:26:52 +0000 (02:26 +0900)]
ARM: UniPhier: reset NAND core in SPL for non-NAND boot mode
For all the UniPhier SoCs so far, the reset signal of the NAND core
is automatically deasserted after the PLL gets stabled.
(The bit 2 of SC_RSTCTRL is default to one.)
This causes a fatal problem on the NAND controller of PH1-LD4.
For that SoC, the NAND I/O pins are not set up yet at the power-on
reset except the NAND boot mode. As a result, the NAND controller
begins automatic device scanning with wrong I/O pins and finally
hangs up.
Actually, U-Boot dies after printing "NAND:" on the console unless
the boot mode latch detected the NAND boot mode.
To work around this problem, reset the NAND core in SPL for non-NAND
boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is
deasserted again in U-Boot proper. At this time, I/O pins have been
correctly set up, the device scanning should succeed.
Masahiro Yamada [Thu, 26 Feb 2015 17:26:49 +0000 (02:26 +0900)]
ARM: UniPhier: fix SBC init code
Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.
Masahiro Yamada [Thu, 26 Feb 2015 17:26:46 +0000 (02:26 +0900)]
serial: UniPhier: use 32 bit register access
For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11)
is not working correctly. As a side effect, it also modifies MCR
register (offset = 0x10) and results in unexpected behavior.
Masahiro Yamada [Thu, 26 Feb 2015 17:26:44 +0000 (02:26 +0900)]
ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>
Since commit 0e7368c6c426 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.
Doug Anderson [Fri, 20 Feb 2015 07:57:20 +0000 (13:27 +0530)]
Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).
This also provides a big cleanup of the L2 cache init code avoiding
some duplication. The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
time) and left resident in iRAM for the kernel to use when bringing
up additional CPUs. It used configure_l2_ctlr() and
configure_l2_actlr() when it detected it was on an A15. This was
needed (despite the L2 cache registers being shared among all A15s)
because we might have been the first man in after the whole A15
cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
time. Strangely this called configure_l2_ctlr() but not
configure_l2_actlr() which was almost certainly wrong. Given that
we'll call both (see next bullet) later in the boot process it
didn't matter for normal boot, but I guess this is how L2 cache
settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
This should happen at boot time (normally in the SPL except for USB
boot where it happens in main U-Boot).
Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time. For resume time we'd get it
anyway when the 2nd A15 core came up.
Let's make this a whole lot simpler. Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.
Intended net effects of this change (other than cleanup):
* Timings go from before:
data: 0 cycle setup, 3 cycles (0x2) latency
tag: 0 cycle setup, 3 cycles (0x2) latency
after:
data: 1 cycle setup, 4 cycles (0x3) latency
tag: 1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.
One note is that we're still relying on luck to keep low_power_start()
working. The compiler is being nice and not storing anything on the
stack.
Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL. The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
(after it has turned the L2 cache off). This is why the functions
are in a header file instead of lowlevel_init.c.
* Have the kernel save the L2 cache settings of the boot CPU and apply
them to all other CPUs. We get a little lucky here because the old
code was using "|=" to modify the registers and all of the bits that
it's setting are also present in the new settings (!). That means
that when the 2nd CPU in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:19 +0000 (13:27 +0530)]
Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do jump to 0x0 but consider following instructions as a Thumb
instructions which in turn makes them loop inside the iROM code instead of
jumping to power_down_core.
This issue is fixed by replacing the "mov pc" instruction with a "bx"
instruction which switches state along with the jump to make the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:18 +0000 (13:27 +0530)]
Exynos542x: Fix secondary core booting for thumb
When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:17 +0000 (13:27 +0530)]
Exynos542x: add L2 control register configuration
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switching.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:16 +0000 (13:27 +0530)]
Exynos542x: cache: Disable clean/evict push to external
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:15 +0000 (13:27 +0530)]
Exynos542x: Add workaround for exynos iROM errata
iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.
Logic of the workaround:
Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:14 +0000 (13:27 +0530)]
Exynos542x: Add workaround for ARM errata 799270
This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value."
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:13 +0000 (13:27 +0530)]
Exynos542x: Add workaround for ARM errata 798870
This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:12 +0000 (13:27 +0530)]
Exynos542x: CPU: Power down all secondary cores
This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 & 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
it puts pointer to function power_down_core into 0x02020004
and provides DSB and SEV for all cores so that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Akshay Saraswat [Fri, 20 Feb 2015 07:57:11 +0000 (13:27 +0530)]
Exynos542x: Config: Add various configs
This patch adds "iRAM, CPU state and low power" configs
which are the addresses acting as flag registers.
iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal
to CONFIG_LOWPOWER_EN then it jumps to the address (0x02020000+CPUID*4).
This is a part of iROM logic. Rest other flags are being used at
various places during kernel switching and reset.
They are nowhere documented because they are part programming.
These configs are serving as flags for us because they are
representing the addresses in iRAM which we are using for
storing and extracting CPU Status and GIC status.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Lukasz Majewski [Thu, 26 Feb 2015 12:23:49 +0000 (13:23 +0100)]
MAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibility
After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.
gaurav rana [Fri, 20 Feb 2015 07:21:46 +0000 (12:51 +0530)]
crypto/fsl - Add progressive hashing support using hardware acceleration.
Currently only normal hashing is supported using hardware acceleration.
Added support for progressive hashing using hardware.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
projects / u-boot / log