Stephen Warren [Mon, 5 Oct 2015 18:09:01 +0000 (12:09 -0600)]
ARM: tegra: add custom MMU setup on ARMv8
This sets up a fine-grained page table, which is a requirement for
noncached_init() to operate correctly.
MMU setup code currently exists in a number of places:
- A version in the core ARMv8 support code that sets up page tables that
use very large block sizes that CONFIG_SYS_NONCACHED_MEMORY doesn't
support.
- Enhanced versions for fsl-lsch3 and zynmq that set up finer grained
page tables.
Ideally, rather than duplicating the MMU setup code yet again this patch
would instead consolidate all the different routines into the core ARMv8
code so that it supported all use-cases. However, this will require
significant effort since there appear to be a number of discrepancies[1]
between different versions of the code, and between the defines/values by
some copies of the MMU setup code use and the architectural MMU
documentation. Some reverse engineering will be required to determine the
intent of the current code.
[1] For example, in the core ARMv8 MMU setup code, three defines named
TCR_EL[123]_IPS_BITS exist, but only one of them sets the IPS field and
the others set a different field (T1SZ) in the page tables. As far as I
can tell so far, there should be no need to set different values per
exception level nor to modify the T1SZ field at all, since TTBR1 shouldn't
be enabled anyway. Another example is inconsistent values for *_VA_BITS
between the current core ARMv8 MMU setup code and the various SoC-
specific MMU setup code. Another example is that asm/armv8/mmu.h's value
for SECTION_SHIFT doesn't match asm/system.h's MMU_SECTION_SHIFT;
research is needed to determine which code relies on which of those
values and why, and whether fixing the incorrect value will cause any
regression.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 5 Oct 2015 18:09:00 +0000 (12:09 -0600)]
armv8: allow custom MMU setup routines on ARMv8
In order for noncached_init() to operate correctly, SoCs must set up a
custom page table with fine-grained (2MiB) sections, which can be
configured from noncached_init().
This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c
by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There
are some other reasons for the duplication there though, such as enabling
icache early, and enabling dcaching earlier with a different configuration.
This change makes mmu_setup() a weak implementation, so that the MMU setup
code can be replaced without having to duplicate other code that calls it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 5 Oct 2015 18:08:59 +0000 (12:08 -0600)]
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
The implementation of noncached_init() uses define MMU_SECTION_SIZE.
Define this on ARM64.
Move the prototype of noncached_{init,alloc}() to a location that
doesn't depend on !defined(CONFIG_ARM64).
Note that noncached_init() calls mmu_set_region_dcache_behaviour() which
relies on something having set up translation tables with 2MB block size.
The core ARMv8 MMU setup code does not do this by default, but currently
relies on SoC specific MMU setup code. Be aware of this before enabling
this feature on your platform!
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arm: stm32f4: fix a bug when a random sector gets erased
Old sector number is not being cleared from FLASH_CR register. For example
when first erased sector was 001 and then you want to erase sector 010,
sector 011 gets erased instead.
This patch clears old sector number from FLASH_CR register before a new
one is written.
Albert ARIBAUD [Fri, 23 Oct 2015 16:06:43 +0000 (18:06 +0200)]
Revive OpenRD targets
Revert commit 7a2c1b13 which dropped OpenRD boards.
Assume maintainership of OpenRD.
Remove OpenRD from scrapyard.
Switch OpenRD to generic board.
Switch to Thumb build.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert ARIBAUD [Fri, 23 Oct 2015 16:06:40 +0000 (18:06 +0200)]
arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.
This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert ARIBAUD [Fri, 23 Oct 2015 16:06:39 +0000 (18:06 +0200)]
stm32f429-discovery: add CONFIG_SYS_THUMB_BUILD
This target is ARMv7-M therefore can only build for Thumb,
but it did not #define CONFIG_SYS_THUMB_BUILD, so the U-Boot
code did not know it had to build for Thumb(2), not ARM.
This patch is binary-invariant: builds of stm32f429-discovery
with and without this patch were compared and found to differ
only by their U-Boot version strings.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
arm: add support for semihosting for ARMv7M targets
If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile
error looking like this:
arch/arm/lib/semihosting.c: In function 'smh_read':
{standard input}: Assembler messages:
{standard input}:34: Error: invalid swi expression
{standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0
scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed
The source of the problem is "svc #0x123456" instruction. This instruction
can not be encoded using Thumb2 instruction set used by ARMv7M CPUs.
ARM documentation suggests using "bkpt #0xAB" instruction instead [1].
This patch fixes compile errors and adds support for semihosting for
STM32F429 or any other ARMv7M target.
This change was sested on STM32F429-DISCOVERY board using OpenOCD and
"smhload" u-boot command.
Michal Simek [Thu, 5 Nov 2015 16:06:29 +0000 (17:06 +0100)]
ARM64: zynqmp: Sync zynq_sdhci_init() declaration
This patch fix compilation error:
drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for
‘zynq_sdhci_init’
int zynq_sdhci_init(phys_addr_t regbase)
^
In file included from drivers/mmc/zynq_sdhci.c:14:0:
./arch/arm/include/asm/arch/sys_proto.h:16:5: note: previous declaration
of ‘zynq_sdhci_init’ was here
int zynq_sdhci_init(unsigned long regbase);
^
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The move to 'generic board' as well as changes in the generic
bootm code broke the boot of FIT uImage's. Especially uImage's
with additional initramfs images or FDT's do not work anymore.
Refactor the bootm code to work again with the generic bootm code.
Always relocate ramdisk and FDT in step 'bootm prep' because the
generic bootm code does this only for legacy uImage's.
Move the step 'bootm cmdline' to 'bootm prep' because the Linux
kernel parameters rd_start and rd_size have to be initialized after
the relocation of the ramdisk.
Furthermore support the step 'bootm fake'.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
common/board_f: enable setup_board_part1() for MIPS
The variables bd_t:bi_memstart and bd_t:bi_memsize have to be
initialized also on MIPS. Otherwise LMB and cmd_bdinfo do not
correctly work. This currently breaks the booting of FIT images
on MIPS. Enable the board_init_f hook setup_board_part1()
for MIPS to fix this.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Thomas Chou [Fri, 6 Nov 2015 01:37:08 +0000 (09:37 +0800)]
net: altera_tse: use BIT macro
Replace numerical bit shift with BIT macro
in altera_tse
:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Thomas Chou [Fri, 6 Nov 2015 01:36:52 +0000 (09:36 +0800)]
net: altera_tse: remove the useless parenthesis
Remove the useless parenthesis.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Thomas Chou [Fri, 6 Nov 2015 01:36:41 +0000 (09:36 +0800)]
net: altera_tse: fix packed and aligned attribute
Fix packed and aligned attribute warnings.
WARNING: __packed is preferred over __attribute__((packed))
#14: FILE: drivers/net/altera_tse.h:14:
+#define __packed_1_ __attribute__ ((packed, aligned(1)))
WARNING: __aligned(size) is preferred over
__attribute__((aligned(size)))
#14: FILE: drivers/net/altera_tse.h:14:
+#define __packed_1_ __attribute__ ((packed, aligned(1)))
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Thomas Chou [Fri, 6 Nov 2015 01:36:26 +0000 (09:36 +0800)]
net: altera_tse: use data type u32 for regs and desc
Use data type u32/u16/u8 for regs and desc, as it is more
portable.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Thomas Chou [Fri, 6 Nov 2015 01:36:06 +0000 (09:36 +0800)]
net: altera_tse: remove unused macro and regs def
Remove unused macro and regs def.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Thomas Chou [Wed, 4 Nov 2015 05:25:20 +0000 (13:25 +0800)]
nios2: trim CONFIG_SYS_MEMTEST_END
Trim CONFIG_SYS_MEMTEST_END location.
CONFIG_SYS_MONITOR_LEN
Reserving 256k for U-Boot at: d7fc0000
CONFIG_ENV_SIZE
CONFIG_SYS_MALLOC_LEN
Reserving 256k for malloc() at: d7f80000
0x10000 for the rest
Reserving 68 Bytes for Board Info at: d7f7ffbc
Reserving 208 Bytes for Global Data at: d7f7feec
Reserving 12000 Bytes for FDT at: d7f7d00c
Stack
Thomas Chou [Sat, 31 Oct 2015 12:53:23 +0000 (20:53 +0800)]
serial: altera_uart: minor clean up
- Moved macro definitions to top
- Re-arrange header includes ascending order
- Remove unused header linux/compiler.h
- Remove the penultimate comma in of_match ids
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
Thomas Chou [Sat, 31 Oct 2015 12:52:38 +0000 (20:52 +0800)]
serial: altera_jtag_uart: minor clean up
- Moved macro definitions to top
- Give spaces around the '>>' in ALTERA_JTAG_WSPACE()
- Re-arrange header includes ascending order
- Remove unused header linux/compiler.h
- Remove the penultimate comma in of_match ids
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
Thomas Chou [Tue, 27 Oct 2015 01:02:17 +0000 (09:02 +0800)]
nios2: change virt_to_phys to use physaddr_mask in global data
As virt_to_phys() is used a lot in DMA transfer, change it
to use physaddr_mask in global data. This will save an "if"
statement and get a little faster.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de>
Fabio Estevam [Thu, 5 Nov 2015 14:43:42 +0000 (12:43 -0200)]
sf: Add SPI NOR protection mechanism
Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
status register that can protect selected regions of the SPI NOR.
Take these bits into account when performing erase operations,
making sure that the protected areas are skipped.
Tested on a mx6qsabresd:
=> sf probe
SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB
=> sf protect lock 0x3f0000 0x10000
=> sf erase 0x3f0000 0x10000
offset 0x3f0000 is protected and cannot be erased
SF: 65536 bytes @ 0x3f0000 Erased: ERROR
=> sf protect unlock 0x3f0000 0x10000
=> sf erase 0x3f0000 0x10000
SF: 65536 bytes @ 0x3f0000 Erased: OK
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
[re-worked to fit the lock common to dm and non-dm] Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
Fabio Estevam [Thu, 5 Nov 2015 14:43:41 +0000 (12:43 -0200)]
sf: Add SPI protection mechanism from the kernel
Add the SPI NOR protection mechanism from the kernel.
This code is based on the work from
Brian Norris <computersforpeace@gmail.com>
Here is the commit details:
"mtd: spi-nor: refactor block protection functions"
(sha1: 62593cf40b23b523b9fc9334ca61ba6c595ebb09)
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Thu, 5 Nov 2015 14:43:40 +0000 (12:43 -0200)]
powerpc: Remove __ilog2_u64 and ffs4 from bitops
Remove __ilog2_u64 and ffs4 from powerpc bitops to align with the
kernel implementation.
Use the generic __ffs64 instead of a custom powerpc implementation.
Cc: York Sun <yorksun@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
Andy Fleming [Wed, 21 Oct 2015 23:59:06 +0000 (18:59 -0500)]
rtc: Add MCP79411 support to DS1307 rtc driver
The code is from Adrian Cox, and is patterned after similar
support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
chip is used on the Cyrus board from Varisys.
Signed-off-by: Andy Fleming <afleming@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
Simon Glass [Sun, 18 Oct 2015 01:41:24 +0000 (19:41 -0600)]
arm: zynq: dts: Add U-Boot device tree additions
We need to mark some device tree nodes so that they are available before
relocation. This enables driver model to find these automatically. In the
case of SPL it ensures that these nodes will be retained in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Simon Glass [Sun, 18 Oct 2015 01:41:19 +0000 (19:41 -0600)]
dm: spl: Support device tree when BSS is in a different section
At present in SPL we place the device tree immediately after BSS. This
avoids needing to copy it out of the way before BSS can be used. However on
some boards BSS is not placed with the image - e.g. it can be in RAM if
available.
Add an option to tell U-Boot that the device tree should be placed at the
end of the image binary (_image_binary_end) instead of at the end of BSS.
Note: A common reason to place BSS in RAM is to support the FAT filesystem.
We should update the code so that it does not use so much BSS.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Simon Glass [Sun, 18 Oct 2015 01:41:15 +0000 (19:41 -0600)]
fdt: Correct handling of alias regions
At present the last four bytes of the alias region are dropped in
the case where the last alias is included. This results in a corrupted
device tree. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>