lpc32xx: move common SLC NAND defines to arch/config.h
A number of LPC32xx SLC NAND defines is dictated by controller
hardware limits and OOB layout is defined by operating system, the
definitions are common for all users. Since those macro are used
in out of NAND SLC driver code (simple NAND SPL framework), they can
not be placed into the driver, therefore move them from board config
files to arch/config.h
The change also adds OOB layout details specific to small page NAND
devices taken from Linux kernel.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Vignesh R [Mon, 17 Aug 2015 07:59:57 +0000 (13:29 +0530)]
ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi
Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With
DMA enabled there is almost 3x improvement in read performance. This
helps in reducing boot time in qspiboot mode
Also add EDMA3 base address for DRA7XX and AM57XX.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Tom Rini [Mon, 17 Aug 2015 07:59:54 +0000 (13:29 +0530)]
sf: ops: Add spi_flash_copy_mmap function
When doing a memory mapped copy we may have DMA available and thus need
to have this copy abstracted so that the driver can do it, rather than a
simple memcpy.
Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Ravi Babu [Mon, 17 Aug 2015 07:59:49 +0000 (13:29 +0530)]
env: use cache line aligned memory for flash read
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers.
This is required because, flash drivers may use DMA for read operations
and may have to invalidate the buffer before read.
Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
Ravi Babu [Mon, 17 Aug 2015 07:59:48 +0000 (13:29 +0530)]
sf: allocate cache aligned buffers to copy from flash
Use memalign() with ARCH_DMA_MINALIGN to allocate read buffers.
This is required because, flash drivers may use DMA for read operations
and may have to invalidate the buffer before read.
Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Jagan Teki <jteki@openedev.com>
This patch enabled the MVEBU PCIe support on the db-88f6820-gp A38x
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
Stefan Roese [Tue, 11 Aug 2015 07:36:15 +0000 (09:36 +0200)]
arm: mvebu: db-mv784mp-gp: Enable PCI support
This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Anton Schubert [Tue, 11 Aug 2015 09:54:01 +0000 (11:54 +0200)]
pci: mvebu: Add PCIe driver
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.
Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are not needed anymore, since this PCIe
driver now creates the windows dynamically.
Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp
eval board using this Intel E1000 PCIe card in the PCIe 0 slot.
This port was done in cooperation with Anton Schubert.
Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
Stefan Roese [Thu, 6 Aug 2015 12:43:13 +0000 (14:43 +0200)]
arm: mvebu: Add complete SDRAM ECC scrubbing
This patch introduces the SDRAM scrubbing for ECC enabled board
to fill/initialize the ECC bytes. This is done via the XOR engine
to speed up the process. The scrubbing is a 2-stage process:
1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot
2) U-Boot scrubs the remaining SDRAM area(s)
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 10 Aug 2015 13:11:27 +0000 (15:11 +0200)]
arm: mvebu: dram.c: Rework dram_init() and dram_init_banksize()
Rework these functions so that dram_init_banksize() does not call
dram_init() again. It only needs to set the banksize values in the
bdinfo struct.
Make sure to also clip the size of the last bank if it exceeds the
maximum allowed value of 3 GiB (0xc000.0000). Otherwise other
address windows (e.g. PCIe) will overlap with this memory window.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 6 Aug 2015 12:27:36 +0000 (14:27 +0200)]
arm: mvebu: Move CONFIG_SYS_TEXT_BASE to an address < 16 MiB
This patch moves CONFIG_SYS_TEXT_BASE to 0x00800000 for all Armada
XP / 38x boards in mainline U-Boot. This is done in preparation for
the ECC SDRAM scrubbing that needs to be done in the main U-Boot.
The SPL (previously bin_hdr) has already scrubbed the area:
0x0000.0000 - 0x0100.0000
In this area this main U-Boot needs to get loaded. The main U-Boot
then can scrub the remaining SDRAM area while running from this
location.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 3 Aug 2015 11:15:31 +0000 (13:15 +0200)]
arm: mvebu: Display ECC enabled / disabled upon bootup
This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM
bootup text. Making it easier for board with SPD DIMM's to see,
if ECC is enabled or not.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 22 Jul 2015 16:05:43 +0000 (18:05 +0200)]
arm: mvebu: db-mv785mp-gp: Add USB/EHCI support
This patch enabled the USB/EHCI support for the Marvell
DB-MV784MP-GP Armada XP eval board.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 22 Jul 2015 16:26:13 +0000 (18:26 +0200)]
arm: mvebu: Enable USB EHCI support on Armada XP
This patch enables the USB EHCI support for the Marvell Armada XP (AXP)
SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure
the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done
this already in the bin_hdr (SPL U-Boot). Without this, accessing the
controller registers in U-Boot or Linux will hang the CPU.
Additionally, the AXP uses a different USB EHCI base address. This
patch also takes care of this by runtime SoC detection in the Marvell
EHCI driver.
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Thu, 16 Jul 2015 08:40:05 +0000 (10:40 +0200)]
arm: mvebu: Enable NAND controller on MVEBU SoC's
This patch enables the NAND controller on the Armada XP/38x and provides
a new function that returns the NAND controller input clock. This
function will be used by the MVEBU NAND driver.
As part of this patch, the multiple BIT macro definitions are moved
to a common place in soc.h.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 11:28:39 +0000 (13:28 +0200)]
arm: mvebu: Disable MBUS error propagation
Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 11:23:52 +0000 (13:23 +0200)]
arm: mvebu: Flush caches and disable MMU only on A38x
Only with disabled MMU its possible to switch the base register address
on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also
not accessible, as its still locked to cache.
So to fully release / unlock this area from cache, we need to first
flush all caches, then disable the MMU and disable the L2 cache.
On Armada XP this does not seem to be needed. Even worse, with this
code added, I sometimes see strange input charactes loss from the
console.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 10:44:51 +0000 (12:44 +0200)]
arm: mvebu: Setup the MBUS bridge registers
With this patch, the MBUS bridge registers (base and size) are
configured upon each call to mbus_dt_setup_win(). This is needed, since
the board code can also call this function in later boot stages. As
done in the maxbcm board.
This is needed to fix a problem with the secondary CPU's not booting
in Linux on AXP.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 10:55:07 +0000 (12:55 +0200)]
arm: mvebu: Change MBUS base addresses and sizes
This patch changes the MBUS base addresses and sizes to use more
generic names and also adds defines for the sizes. It also moves
the base address to higher addresses.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Tue, 11 Aug 2015 15:08:01 +0000 (17:08 +0200)]
arm: mvebu: sdram: Enable ECC support on Armada XP
This is tested on the DB-MV784MP-GP eval board. To really enable ECC
support on this board the I2C EEPROM needs to get changed. As it
saves the enabling of ECC support internally. For this the following
commands can be used to enable ECC support on this board:
Its recommended for first save (print) the value(s) in this EEPROM
address:
=> i2c md 4e 0.1 2
0000: 05 00 ..
To enable ECC support you need to set bit 1 in the 2nd byte:
Marvell>> i2c mw 4e 1.1 02
Marvell>> i2c md 4e 0.1 2
0000: 05 02 ..
To disable ECC support again, please use this command:
Marvell>> i2c mw 4e 1.1 00
Marvell>> i2c md 4e 0.1 2
0000: 05 00 ..
On other AXP boards, simply plugging an ECC DIMM should be enough to
enable ECC support.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Marek Vasut [Sun, 2 Aug 2015 23:28:56 +0000 (01:28 +0200)]
sf: Make 4K sector support configurable
Make the support for 4K subpage I/O on a SPI NOR flash configurable.
A board which requires the SPI NOR to be accessed in larger 32KiB
or 64KiB pages can disable the 4K subpage support, but by default,
the support for 4K subpage I/O is enabled. The functionality of this
option is the same as CONFIG_MTD_SPI_NOR_USE_4K_SECTORS in Linux.
This is extremely useful in case one uses UBI on a SPI NOR flash.
UBI needs at least 15k EBs and can not work on a flash which uses
4k ones, so disabling the support for 4k subpages lets UBI work on
such flash.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
Thomas Abraham [Mon, 3 Aug 2015 12:28:01 +0000 (17:58 +0530)]
ARM: exynos: fix regression for Origen4210
The do_lowlevel_init() function includes certian CA15 specific L2 cache
configuration which is only applicable on Exynos5420 and members of its
family. Fix the regression on Origen4210 by skipping the Exynos5420
specific portions of the code.
Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Lokesh Vutla [Thu, 13 Aug 2015 14:56:38 +0000 (20:26 +0530)]
ARM: OMAP5+: configs: Fix default boot command
The default boot command searches for dofastboot varaiable
and does a fastboot if it is set to 1.
But the condition "if test ${dofastboot} -eq 1" always
returns true if dofastboot is not defined and breaking mmc boot.
So make dofastboot as 0 by default and let the runtime
environment set it if fastboot is required.
Reported-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
It also happens to break SPI flash on Minnowboard max which is how I noticed
that this was applied. I can send a patch to tidy that up, but in any case
I think we should consider a revert until the function is better implemented.
Simon Glass [Thu, 13 Aug 2015 16:36:17 +0000 (10:36 -0600)]
x86: Add a simple interrupt script to the README
It is a bit tedious to figure out the interrupt configuration for a new
x86 platform. Add a script which can do this, based on the output of
'pci long'. This may be helpful in some cases.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Mon, 10 Aug 2015 06:58:39 +0000 (23:58 -0700)]
x86: Set APs' req_seq to the reg number from device tree
Multiple APs are brought up simultaneously and they may get the same
seq num in the uclass_resolve_seq() during device_probe(). To avoid
this, set req_seq to the reg number in the device tree in advance.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 11 Aug 2015 04:02:54 +0000 (22:02 -0600)]
x86: Show the un-relocated IP address in exceptions
When trying to figure out where an exception has occured, the relocated
address is not a lot of help. Its value depends on various factors. Show
the un-relocated IP as well. This can be looked up in System.map directly.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Unfortunately this commit breaks chromebook_link because it adds lots of PCI devices
before relocation and there is not enough pre-reloc malloc() memory.
Rathar then increase this memory, revert for now until we figure this out.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 11 Aug 2015 02:44:32 +0000 (20:44 -0600)]
x86: Switch to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.
Drop the unneeded code and adjust the hooks in board_f.c to cope.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 11 Aug 2015 02:44:31 +0000 (20:44 -0600)]
x86: Move the GDT into global_data
Rather than keeping track of the Global Descriptor Table in its own memory
we may as well put it in global_data with everything else. As a first step,
stop using the separately allocated GDT.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 11 Aug 2015 02:44:30 +0000 (20:44 -0600)]
Allow arch-specific setting of global_data in board_init_f_mem()
At present we have a simple assignment to gd. With some archs this is
implemented as a register or through some other means; a simple assignment
does not suit in all cases.
Change this to a function and add documentation to describe how this all
works.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Stephen Warren [Sun, 9 Aug 2015 17:25:00 +0000 (11:25 -0600)]
cm5200: fix FAT function prototypes
Remove FAT function prototypes from the cm5200 firmware update code, and
include the relevant headers instead.
This exposes the fact that the custom prototyoe for do_fat_read() in
this file was incorrect. Rather than simply fixing the call-site, replace
do_fat_read() with fat_exists(). This removes the only use of
do_fat_read() outside of the FAT code.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Peng Fan [Fri, 14 Aug 2015 09:36:16 +0000 (11:36 +0200)]
Add missing part of: "power: pmic: pfuze100 support driver model"
This part of mentioned commit, was missed by my mistake during the rebase. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Original commit message:
power: pmic: pfuze100 support driver model
1. Support driver model for pfuze100.
2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100
3. This driver intends to support PF100, PF200 and PF3000, so add
the device id into the udevice_id array.
4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS.
Change-Id: I4fc88414f3c0285f9648e47ec7aed60addeccc4d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 10 Aug 2015 13:05:07 +0000 (07:05 -0600)]
x86: Split out fsp_init_phase_pci() code into a new function
This code may be useful for boards that use driver model for PCI.
Note: It would be better to have driver model automatically call this
function somehow. However for now it is probably safer to have it under
board control.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 10 Aug 2015 13:05:04 +0000 (07:05 -0600)]
dm: pci: Add a way to iterate through all PCI devices
These functions allow iteration through all PCI devices including bridges.
The children of each PCI bus are returned in turn. This can be useful for
configuring, checking or enumerating all the devices.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 10 Aug 2015 13:05:03 +0000 (07:05 -0600)]
dm: pci: Provide friendly config access functions
At present there are no PCI functions which allow access to PCI
configuration using a struct udevice. This is a sad situation for driver
model as it makes use of PCI harder. Add these functions.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Sat, 8 Aug 2015 14:01:23 +0000 (22:01 +0800)]
x86: fsp: Do not assert VPD_IMAGE_REV when DEBUG
When using different release version of Intel FSP, the VPD_IMAGE_REV
is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304).
Remove the asserting of this so that U-Boot does not hang in a debug
build.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Andrew Bradford [Fri, 7 Aug 2015 12:36:35 +0000 (08:36 -0400)]
x86: baytrail: Configure FSP UPD from device tree
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.
Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.
Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 6 Aug 2015 09:36:01 +0000 (02:36 -0700)]
x86: baytrail: Add all IDE/SATA PCI device IDs
The BayTrail SoC has 4 different PCI devices IDs regarding to IDE
and AHCI. Add these IDs in pci_ids.h and also add the other SATA
ID in the Bayley Bay and MinnowMax board configuration header.
Bin Meng [Thu, 6 Aug 2015 08:31:20 +0000 (01:31 -0700)]
common: Display >=4GiB memory bank size
bd->bi_dram[] has both start address and size defined as 32-bit,
which is not the case on some platforms where >=4GiB memory bank
is used. Change them to support such memory banks.
Hans de Goede [Sat, 8 Aug 2015 14:03:29 +0000 (16:03 +0200)]
video: Add support for the ANX9804 parallel lcd to dp bridge chip
Add support for the ANX9804 bridge chip, which can take pixel data coming
from a parallel LCD interface and translate it on the fly into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Thu, 6 Aug 2015 18:10:20 +0000 (20:10 +0200)]
sunxi: gpio: Add support for the gpio banks which are part of the R-io cluster
sun6i and later have a couple of io-blocks which are shared between the
main CPU core and the "R" cpu which is small embedded cpu which can be
active while the main system is suspended.
These gpio banks sit at a different mmio address then the normal banks,
and have a separate devicetree node and compatible, this adds support for
these banks to the sunxi-gpio code when built with device-model support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Thu, 6 Aug 2015 13:39:05 +0000 (15:39 +0200)]
sunxi: Fix gmac not working on the Colombus board
The phy is using a RGMII interface, which we need to specify in our
board-config, and the dts needs a gmac section (the dts changes have
also been submitted to the kernel).
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
projects / u-boot / log