Simon Glass [Tue, 7 May 2013 06:11:51 +0000 (06:11 +0000)]
image: Move timestamp #ifdefs to header file
Rather than repeat the line
#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
defined(USE_HOSTCC)
everywhere, put this in a header file and #define IMAGE_ENABLE_TIMESTAMP
to either 1 or 0. Then we can use a plain if() in most code and avoid
the #ifdefs.
The compiler's dead code elimination ensures that the result is the same.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
Simon Glass [Tue, 7 May 2013 06:11:48 +0000 (06:11 +0000)]
bootstage: Don't build for HOSTCC
We don't measure boot timing on the host, or with SPL, so use both
conditions in the bootstage header. This allows us to avoid using
conditional compilation around bootstage_...() calls. (#ifdef)
Simon Glass [Tue, 7 May 2013 06:11:47 +0000 (06:11 +0000)]
hash: Add a way to calculate a hash for any algortihm
Rather than needing to call one of many hashing algorithms in U-Boot,
provide a function hash_block() which handles this, and can support all
available hash algorithms.
Once we have md5 supported within hashing, we can use this function in
the FIT image code.
Doug Anderson [Wed, 17 Apr 2013 16:13:41 +0000 (16:13 +0000)]
bootstage: Copy bootstage strings post-relocation
Any pointers to name strings that were passed to bootstage_mark_name()
pre-relocation should be copied post-relocation so that they don't get
trashed as the original location of U-Boot is re-used for other
purposes.
This change introduces a new API call that should be called from
board_init_r() after malloc has been initted on any board that uses
bootstage.
Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 17 Apr 2013 16:13:39 +0000 (16:13 +0000)]
x86: Re-enable PCAT timer 2 for beeping
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.
Simon Glass [Wed, 17 Apr 2013 16:13:37 +0000 (16:13 +0000)]
x86: Remove old broken timer implementation
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Michael Spang <spang@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
Simon Glass [Wed, 17 Apr 2013 16:13:35 +0000 (16:13 +0000)]
x86: Rationalise kernel booting logic and bootstage
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michael Spang <spang@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
Simon Glass [Wed, 17 Apr 2013 16:13:33 +0000 (16:13 +0000)]
x86: Declare global_data pointer when it is used
Several files use the global_data pointer without declaring it. This works
because the declaration is currently a NOP. But still it is better to
fix this so that x86 lines up with other archs.
Commit 1865286466a5d0c7f2e3c37632da56556c838e9e (Introduce generic link
section.h symbol files) changed the __bss_end symbol type from char[] to
ulong. This led to wrong relocation parameters which ended up in a not working
u-boot. Unfortunately this is not clear to see cause due to RAM aliasing we
may get a 'half-working' u-boot then.
Fix this by dereferencing the __bss_end symbol where needed.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Sonic Zhang [Thu, 2 May 2013 05:46:21 +0000 (13:46 +0800)]
bfin: Move gpio support for bf54x and bf60x into the generic driver folder.
The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx.
A lot of machine macros are used to accomodate both code in one gpio driver.
This patch split the old gpio driver and move new gpio2 support to the generic
gpio driver folder.
- To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's
config header file.
- The gpio2 driver supports bf54x, bf60x and future ADI processors, while the
older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561.
- All blackfin specific gpio function names are replaced by the generic gpio APIs.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Sonic Zhang [Sun, 7 Apr 2013 11:04:14 +0000 (19:04 +0800)]
blackfin: Move blackfin serial driver out of blackfin arch folder.
- Move blackfin serial driver to the generic driver folder.
- Move blackfin serial headers to blackfin arch head folder.
- Update the include path to blackfin serial header in start up code.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Sonic Zhang [Wed, 13 Mar 2013 11:06:16 +0000 (19:06 +0800)]
blackfin: Enable early print via the generic serial API.
Remove blackfin specific implementation of the generic serial API when
early print macro is defined.
In BFIN_BOOT_BYPASS mode, don't call generic serial_puts, because
early print in bypass mode is running before code binary is relocated
to the link address.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Sonic Zhang [Wed, 20 Feb 2013 10:05:16 +0000 (18:05 +0800)]
blackfin: Fit u-boot image size into limited nor flash on blackfin.
- Disable NAND driver on bf537-stamp.
- Make MMC_SPI optional.
- Disable LCD driver on bf527-ezkit.
- Enlarge BF609 nor flash reserved size from 256k to 512k bytes.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
Sonic Zhang [Fri, 30 Nov 2012 09:39:32 +0000 (17:39 +0800)]
blackfin: Correct early serial mess output in BYPASS boot mode.
The early serial should not be configured again in initcode() for BYPASS
boot mode and in start() for the other LDR boot modes.
In BYPASS boot mode, the start up code is located in Nor flash address other
than the DRAM address defined in link script. The code embedded string can't
be addressed by its compile time symbol. Calculate it according to the flash
offset.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Sonic Zhang [Tue, 5 Feb 2013 10:57:49 +0000 (18:57 +0800)]
blackfin: run core1 from L1 code sram start address in uboot init code on core 0
Define core 1 L1 code sram start address.
Add function to enable core 1 for BF609 and BF561.
Add config macro to allow customer to run core 1 in uboot init code on core 0.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Mike Frysinger [Tue, 31 Jul 2012 09:38:56 +0000 (05:38 -0400)]
Blackfin: adjust asm constraints with NMI workaround
Newer gcc versions will sometimes use a Preg when "r" constraints, but
that'll fail if we use an Ireg in the assignment. So force the code
to always use a Dreg.
This also fixes early boot crashes for older Blackfin parts when compiled
with gcc-4.5. This version ends up selecting the same register for the
input and output variables which corrupts the output assignment triggering
an exception.
P2 = 0xffe02008; /* EVT2 */
R0 = RETS;
CALL 1f;
RTN;
1: P2 = RETS; <-- BAD
RETS = R0;
[P2] = P2; <-- BAD
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Justin Sobota [Fri, 15 Feb 2013 16:06:10 +0000 (11:06 -0500)]
Added license header to dtc/libfdt/fdt.h and libfdt_env.h
This commit adds a license header to fdt.h and libfdt_env.h
because the license was omitted.
U-Boot note: the u-boot libfdt_env.h header portion was not applied to
the u-boot libfdt_env.h because that file was created by Gerald Van Baren
(with a license header). - gvb
Egbert Eich [Wed, 1 May 2013 01:13:19 +0000 (01:13 +0000)]
fs/ext4: Support device block sizes != 512 bytes
The 512 byte block size was hard coded in the ext4 file systems.
Large harddisks today support bigger block sizes typically 4096
bytes.
This patch removes this limitation.
Many boot image configuration files refer to the
appropriate documentation file, but these references
contain typos in the directory and file name. Fix
them. Also fix reference to doc/README.SPL file.
Michal Simek [Mon, 6 May 2013 04:11:58 +0000 (04:11 +0000)]
patman: Do not hardcode python path
Patman requires python 2.7.4 to run but it doesn't
need to be placed in /usr/bin/python.
Use env to ensure that the interpreter used is
the first one on environment's $PATH on system
with several versions of Python installed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 2 May 2013 14:46:02 +0000 (14:46 +0000)]
buildman: Allow conflicting tags to avoid spurious errors
Conflicting tags can prevent buildman from building two series which exist
one after the other in a branch. There is no reason not to allow this sort
of workflow with buildman, so ignore conflicting tags in buildman.
Change-Id: I2231d04d8684fe0f8fe77f8ea107e5899a3da5e8 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
If the environment contains an entry like "=value" "\0" we should throw
an error when parsing the environment. Otherwise, U-Boot will enter in
an infinite loop.
Marek Vasut [Sat, 27 Apr 2013 07:50:11 +0000 (07:50 +0000)]
build: Pull -DBUILD_TAG into separate ifdef
Currently the base setting for CFLAGS is split in two possibilities,
one with -DBUILD_TAG appended at the end and one without, the rest of
CFLAGS is the same in both cases. Change this so CFLAGS are always set
and the -DBUILD_TAG is appended in separate ifdef.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
Michal Simek [Wed, 24 Apr 2013 08:01:20 +0000 (10:01 +0200)]
gpio: Add support for microblaze xilinx GPIO
Microblaze uses gpio which is connected to the system reset.
Currently gpio subsystem wasn't used for it.
Add gpio driver and change Microblaze reset logic to be done
via gpio subsystem.
There are various configurations which Microblaze can have
that's why gpio_alloc/gpio_alloc_dual(for dual channel)
function has been introduced and gpio can be allocated
dynamically.
Adding several gpios IP is also possible and supported.
For listing gpio configuration please use "gpio status" command
This patch also remove one compilation warning:
microblaze-generic.c: In function 'do_reset':
microblaze-generic.c:38:47: warning: operation on '*1073741824u'
may be undefined [-Wsequence-point]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Davide Bonfanti [Thu, 29 Nov 2012 01:06:53 +0000 (01:06 +0000)]
davinci, mmc: Added a delay reading ext CSD register
Without this additional delay, some eMMC don't negotiate properly bus width
Tested on:
- Toshiba THGBM2G8D8FBAIB
- Toshiba THGBM4G4D1HBAR
- Micron MTFC4GMVEA (the one giving the problem)
- Hynix H26M64002BNR
- SanDisk SDIN5E1-32G
Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Che-Liang Chiou [Wed, 28 Nov 2012 15:21:13 +0000 (15:21 +0000)]
mmc: Split device init to decouple OCR-polling delay
Most of time that MMC driver spends on initializing a device is polling
OCR (operation conditions register). To decouple this polling loop,
device init is split into two parts: The first part fires the OCR query
command, and the second part polls the result. So the caller is now no
longer bound to the OCR-polling delay; he may fire the query, go
somewhere and then come back later for the result.
To use this, call mmc_set_preinit() on any device which needs this.
This can save significant amounts of time on boot (e.g. 200ms) by
hiding the MMC init time behind other init.
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
usb: hub: Parallelize power-cycling of root-hub ports
Untill now we power-cycle (aka: disable power on a port
and re-enabling again) one port at a time.
Delay of 20ms for Port-power to change multiplies with
number of ports in this case.
So better we parallelize this process:
disable power on all ports, wait for port-power to stabilize
and then re-enable the power subsequently.
Patch b6d7852c increases timeout for enumeration, taking
worst case to be 10 sec.
get_timer() api returns timestamp in milliseconds, which is
what we are checking in the do-while() loop in usb_hub_configure()
(get_timer(start) < CONFIG_SYS_HZ * 10).
This should give us a required check for 10 seconds, and thereby
we don't need to add additional mdelay of 100 microseconds in
each cycle.
usb: common: Weed out USB_**_PRINTFs from usb framework
USB_PRINTF, USB_HUB_PRINTF, USB_STOR_PRINTF, USB_KBD_PRINTF
are nothing but conditional debug prints, depending on DEBUG.
So better remove them and use debug() simply.
Julius Werner [Thu, 28 Feb 2013 18:08:40 +0000 (18:08 +0000)]
usb: Add new command to set USB 2.0 port test modes
This patch adds a new 'usb test' command, that will set a port to a USB
2.0 test mode (see USB 2.0 spec 7.1.20). It supports all five test modes
on both downstream hub ports and ordinary device's upstream ports. In
addition, it supports EHCI root hub ports.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Tom Rini [Fri, 3 May 2013 13:19:43 +0000 (09:19 -0400)]
P1022DS: Set CONFIG_SPL_MAX_SIZE directly
With the u-boot-with-spl.bin rule calling $(OBJCOPY) with
CONFIG_SPL_PAD_TO, and CONFIG_SPL_PAD_TO defaulting to
CONFIG_SPL_MAX_SIZE we cannot use math here, so set it to 4096 rather
than 4 * 1024.
Shaohui Xie [Mon, 25 Mar 2013 07:30:15 +0000 (07:30 +0000)]
powerpc/85xx: set USB2 default mode to 'device' for (super)hydra boards
The Hydra and Superhydra (P3041DS, P5020DS, and P5040DS) boards have a
second USB port that can be configured in either host, peripheral (aka
device), or OTG (on-the-go) mode. When configured in host mode, if
the port is connected to another USB host, damage to the board can
occur.
To avoid this, we change the default setting to peripheral mode. Ideally,
we'd set it to OTG mode, but currently there is no OTG support for
these boards.
Setting the hwconfig variable will also update the device tree, and so
Linux will configure the port for peripheral mode as well.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
Xu Jiucheng [Mon, 25 Mar 2013 07:30:13 +0000 (07:30 +0000)]
powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PC
When P1021RDB-PC reboot system, the board will hung at uboot DDR
configuration. For P1021RDB-PC DDR reset pin is multiplex with
QE, so uboot will reserve this pin for QE and skip DDR reset.
Other platforms without QE will do this reset. This patch adds
a slight code to reset DDR chip by QE CE_PB8 pin for NAND and
NOR FLASH boot. For booting from SPI FALSH and SD card, it
seems possible to use the rom on chip to write to the GPIO
pins before configuring the DDR.
Extending LIODN offset range from 1-5 to 1-10
While using a qman portal with a higher index the LIODN offset
is incorrectly set, thus extending the range of offsets covers
all 10 qman portals
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Acked-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Zhicheng Fan [Mon, 25 Mar 2013 07:30:07 +0000 (07:30 +0000)]
qoriq/p1_p2_rdb_pc: USB device-tree fixups for P1020
Resolve P1020 second USB controller multiplexing with eLBC
- mandatory to mention USB2 in hwconfig string to select it
over eLBC, otherwise USB2 node is removed
- works only for SPI and SD boot
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Zhicheng Fan <B32736@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Poonam Aggrwal [Mon, 25 Mar 2013 07:30:06 +0000 (07:30 +0000)]
doc/ramboot.mpc85xx: Documented the RAMBOOT for MPC85xx
There could be scenarios where the user would like to manually(via JTAG)
configure the DDR/L2SRAM and load the bootloader binary onto DDR/L2SRAM.
This document explains thse usecases and the detailed explanation of what needs
to be done to use it.
Most of the code from CONFIG_SYS_RAMBOOT will be used except for small changes
of CCSRBAR etc.
The changes are not very large, but it is good to document them so that user
can get it working at once.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
projects / u-boot / log