]> git.sur5r.net Git - u-boot/log
u-boot
6 years agorockchip: rk3128: add evb-rk3128 support
Kever Yang [Tue, 28 Nov 2017 08:04:19 +0000 (16:04 +0800)]
rockchip: rk3128: add evb-rk3128 support

evb-rk3128 is an evb from Rockchip based on rk3128 SoC:
- 2 USB2.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: rk3128: add pinctrl driver
Kever Yang [Tue, 28 Nov 2017 08:04:18 +0000 (16:04 +0800)]
rockchip: rk3128: add pinctrl driver

Add rk3128 pinctrl driver and grf/iomux structure definition.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: rk3128: add clock driver
Kever Yang [Tue, 28 Nov 2017 08:04:17 +0000 (16:04 +0800)]
rockchip: rk3128: add clock driver

Add rk3128 clock driver and cru structure definition.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: rk3128: add soc basic support
Kever Yang [Tue, 28 Nov 2017 08:04:16 +0000 (16:04 +0800)]
rockchip: rk3128: add soc basic support

RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU
and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host
and device, HDMI/LVDS/MIPI display.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: rk3128: add device tree file
Kever Yang [Tue, 28 Nov 2017 08:04:15 +0000 (16:04 +0800)]
rockchip: rk3128: add device tree file

Add dts binding header for rk3128, files origin from kernel.

Series-Changes: 2
- fix i2c address
- add saradc and usb phy node
- emmc using fifo mode for there is no dma support in rk3128 emmc
- add some clock id in cru.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: board: evb_rv1108: update README
Andy Yan [Mon, 27 Nov 2017 11:59:45 +0000 (19:59 +0800)]
rockchip: board: evb_rv1108: update README

After commit d962e5dadc2c("rockchip: mkimage: use spl_boot0 for all Rockchip SoCs"),
the mkimage will not pad the Tag memroy, so we shoud
pass a Taged ddr.bin/spl.bin to it.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agoMAINTAINERS: update maintained files for Rockchip
Philipp Tomsich [Sun, 26 Nov 2017 23:18:42 +0000 (00:18 +0100)]
MAINTAINERS: update maintained files for Rockchip

With some of the recent cleanups (e.g. moving the DRAM controller
drivers for Rockchip devices to drivers/ram/rockchip), the files
and paths listed in MAINTAINERS no longer covered what really is
looked after as part of the Rockchip port.

This commit updates the files/paths listed in MAINTAINERS for the
Rockchip port.  I am certain, though, that this will have missed some
additional paths that should have been included...

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agoMerge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh
Tom Rini [Thu, 30 Nov 2017 15:39:04 +0000 (10:39 -0500)]
Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh

6 years agoMerge git://git.denx.de/u-boot-marvell
Tom Rini [Thu, 30 Nov 2017 15:38:40 +0000 (10:38 -0500)]
Merge git://git.denx.de/u-boot-marvell

6 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Thu, 30 Nov 2017 15:37:43 +0000 (10:37 -0500)]
Merge git://git.denx.de/u-boot-x86

6 years agoARM: rmobile: Rework the ULCB CPLD driver
Marek Vasut [Sun, 26 Nov 2017 19:32:44 +0000 (20:32 +0100)]
ARM: rmobile: Rework the ULCB CPLD driver

Rework the ULCB CPLD driver and make it into a sysreset driver,
since that is what the ULCB CPLD driver is mostly for.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: mvebu: correct comments around cas_wl/cas_l
Chris Packham [Tue, 28 Nov 2017 21:38:34 +0000 (10:38 +1300)]
arm: mvebu: correct comments around cas_wl/cas_l

The order of members in struct hws_topology_map is cas_wl, cas_l. The
comments in the original db-88f6820-gp.c had this wrong and have been
copied to other Armada-385 based boards. Practically this hasn't made a
difference since all these boards set both cas_wl and cas_l to 0
(autodetect) but if there were ever a board that did need to set these
explicitly they would run into unexpected issued.

Update the comments to reflect the correct order of structure members.

Reported-by: Tobi Wulff <tobi.wulff@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: mvebu: armada-7k/8k: drop useless #ifdef
Baruch Siach [Sun, 26 Nov 2017 07:21:23 +0000 (09:21 +0200)]
arm64: mvebu: armada-7k/8k: drop useless #ifdef

CONFIG_ENV_IS_IN_NAND has been removed in commit 2be296538e2e (Convert
CONFIG_ENV_IS_IN_MMC/NAND/UBI and NOWHERE to Kconfig).
CONFIG_ENV_IS_IN_SPI_FLASH has been removed in commit 91c868fe7cd
(Convert CONFIG_ENV_IS_IN_SPI_FLASH to Kconfig). The environment #ifdef
is now empty. Remove it.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm: mvebu: enable boot from NAND
Sean Nyekjaer [Fri, 24 Nov 2017 13:01:47 +0000 (14:01 +0100)]
arm: mvebu: enable boot from NAND

Check if we are booting from NAND and let the bootrom
continue to load the rest of the bootloader

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm: mvebu: fix boot from UART when in fallback mode
Sean Nyekjaer [Fri, 24 Nov 2017 13:01:28 +0000 (14:01 +0100)]
arm: mvebu: fix boot from UART when in fallback mode

It's the first 8 bits of the bootrom error register that
contain the boot error/fallback error code. Let's check that
and continue to boot from UART.

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm: mvebu: add nand pins
Sean Nyekjaer [Fri, 24 Nov 2017 13:00:48 +0000 (14:00 +0100)]
arm: mvebu: add nand pins

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agofix: nand: pxa3xx: fix defined but not used warnings
Sean Nyekjaer [Wed, 22 Nov 2017 12:39:08 +0000 (13:39 +0100)]
fix: nand: pxa3xx: fix defined but not used warnings

bbt_mirror_descr and bbt_main_descr is defined but not used
when compiling without CONFIG_SYS_NAND_USE_FLASH_BBT set.

Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agox86: lib: Implement standalone __udivdi3 etc instead of libgcc ones
Stefan Roese [Wed, 29 Nov 2017 15:23:31 +0000 (16:23 +0100)]
x86: lib: Implement standalone __udivdi3 etc instead of libgcc ones

This patch removes the inclusion of the libgcc math functions and
replaces them by functions coded in C, taken from the coreboot
project. This makes U-Boot building more independent from the toolchain
installed / available on the build system.

The code taken from coreboot is authored from Vadim Bendebury
<vbendeb@chromium.org> on 2014-11-28 and committed with commit
ID e63990ef [libpayload: provide basic 64bit division implementation]
(coreboot git repository located here [1]).

I modified the code so that its checkpatch clean without any
functional changes.

[1] git://github.com/coreboot/coreboot.git

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
6 years agodistro bootcmd: define bootloader name for x86
Heinrich Schuchardt [Fri, 24 Nov 2017 21:32:35 +0000 (22:32 +0100)]
distro bootcmd: define bootloader name for x86

Currently X86 does not properly support distro defaults.
This patch is only a partial fix.

It provides the name of the bootloader EFI application
for the X86 architecture.

The architecture dependent file names are defined in the UEFI
specification.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agoRevert "x86: bootm: Fix FIT image booting on x86"
Anatolij Gustschin [Thu, 23 Nov 2017 17:59:45 +0000 (18:59 +0100)]
Revert "x86: bootm: Fix FIT image booting on x86"

This reverts commit 13c531e52a09b4e6ffa8b5a1457199b0a574cb27.

The error message with FIT style image mentioned in the above commit
only happens when booting using FIT image containing bzImage kernel
and without setup node (setup.bin). The current documentation for
x86 FIT support in doc/uImage.FIT/x86-fit-boot.txt mentions that
kernel's setup.bin file is required for building x86 FIT images.
The above commit breaks FIT images generated as described in the
documentation. Revert it to allow booting with images built in the
documented way.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: don't compare pointers to 0
Heinrich Schuchardt [Mon, 20 Nov 2017 18:45:56 +0000 (19:45 +0100)]
x86: don't compare pointers to 0

x86_vendor_name is defined as

static const char *const x86_vendor_name[]

So its elements should not be compared to 0.

Remove superfluous paranthesis.

Problem identified with Coccinelle.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: conga-qeval20-qa3-e3845: Adjust VGA rom address
Anatolij Gustschin [Fri, 17 Nov 2017 01:29:59 +0000 (02:29 +0100)]
x86: conga-qeval20-qa3-e3845: Adjust VGA rom address

Adjust VGA rom address to 0xfffb0000 so that u-boot.rom image
can be built again.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: qemu: Move Cache-As-RAM memory from area mapped to ROM
Anton Gerasimov [Tue, 14 Nov 2017 17:47:16 +0000 (18:47 +0100)]
x86: qemu: Move Cache-As-RAM memory from area mapped to ROM

ROM has been made read-only in qemu recently (namely commit 208fa0e4:
"pc: make 'pc.rom' readonly when machine has PCI enabled"). So this
patch restores compatibility between U-Boot and qemu.

Signed-off-by: Anton Gerasimov <anton@advancedtelematic.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: mention qemu commit title in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
6 years agofat: Use cache aligned buffers for fat_opendir
Neil Armstrong [Fri, 24 Nov 2017 08:54:41 +0000 (09:54 +0100)]
fat: Use cache aligned buffers for fat_opendir

Before this patch one could receive following errors when executing "fatls"
command on machine with cache enabled (ex i.MX6Q) :

=> fatls mmc 0:1
CACHE: Misaligned operation at range [4f59dfc84f59e7c8]
CACHE: Misaligned operation at range [4f59dfc84f59e7c8]
ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x4f59dfc8
ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x4f59e7c8
CACHE: Misaligned operation at range [4f59dfc84f59e7c8]
CACHE: Misaligned operation at range [4f59dfc84f59e7c8]
ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x4f59dfc8
ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x4f59e7c8

To alleviate this problem - the calloc()s have been replaced with
malloc_cache_aligned() and memset().

After those changes the buffers are properly aligned (with both start
address and size) to SoC cache line.

Fixes: 09fa964bba80 ("fs/fat: Fix 'CACHE: Misaligned operation at range' warnings")
Suggested-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
6 years agoboard: laird: add WB50N CPU module
Ben Whitten [Thu, 23 Nov 2017 13:47:48 +0000 (13:47 +0000)]
board: laird: add WB50N CPU module

This board is based on the Atmel sama5d3 eval boards.
Supporting the following features:
 - Boot from NAND Flash
 - Ethernet
 - FIT
 - SPL

Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
6 years agoboard: laird: add WB45N CPU module
Ben Whitten [Thu, 23 Nov 2017 13:47:47 +0000 (13:47 +0000)]
board: laird: add WB45N CPU module

This board is based on the Atmel 9x5 eval board.
Supporting the following features:
 - Boot from NAND Flash
 - Ethernet
 - FIT
 - SPL

Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
6 years agoenv: suppress a spurious warning with GCC 7.1
Philipp Tomsich [Tue, 21 Nov 2017 22:29:40 +0000 (23:29 +0100)]
env: suppress a spurious warning with GCC 7.1

GCC 7.1 seems to be smart enough to track val through the various
static inline functions, but not smart enough to see that val will
always be initialised when no error is returned.  This triggers
the following warning:
  env/mmc.c: In function 'mmc_get_env_addr':
  env/mmc.c:121:12: warning: 'val' may be used uninitialized in this function [-Wmaybe-uninitialized]

To make it easier for compiler to understand what is going on, let's
initialise val.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agospl: make CONFIG_OF_EMBED pass dts through fdtgrep
Goldschmidt Simon [Tue, 21 Nov 2017 12:29:56 +0000 (12:29 +0000)]
spl: make CONFIG_OF_EMBED pass dts through fdtgrep

Building spl with CONFIG_OF_EMBED enabled results in an error message
on my board: "SPL image too big". This is because the fdtgrep build
step is only executed for CONFIG_OF_SEPARATE.

Fix this by moving the fdtgrep build step ('cmd_fdtgreo') from
scripts/Makefile.spl to dts/Makefile so that the reduced dtb is
available for all kinds of spl builds.

The resulting variable name for the embedded device tree blob changes,
too, which is why common.h and fdtdec.c have tiny changes.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoARM: dts: Rename logicpd-toredp-37xx-devkit in U-Boot
Adam Ford [Mon, 20 Nov 2017 15:56:03 +0000 (09:56 -0600)]
ARM: dts: Rename logicpd-toredp-37xx-devkit in U-Boot

In U-Boot, this device tree is compatible with both the Torpedo and
SOM-LV kits.  Let's rename it in the device tree since the U-Boot code and
show a more generic OMAP3 name.  The code auto detects between the two and
loads the proper DTB file for Linux.  This would eliminate the SOM-LV showing
the name Torpedo during boot and hopefully eliminate some confusion.

Signed-off-by: Adam Ford <aford173@gmail.com>
6 years agofs: avoid possible NULL dereference in fs_devread
Heinrich Schuchardt [Sun, 19 Nov 2017 22:49:21 +0000 (23:49 +0100)]
fs: avoid possible NULL dereference in fs_devread

It is unwise to first dereference a variable
and then to check if it was NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agocmd: blk: remove unreachable code
Heinrich Schuchardt [Sun, 19 Nov 2017 22:25:32 +0000 (23:25 +0100)]
cmd: blk: remove unreachable code

Remove an unreachable return statement.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agocommon: command: tempory buffer should have size of command line buf
Heinrich Schuchardt [Sun, 19 Nov 2017 22:07:50 +0000 (23:07 +0100)]
common: command: tempory buffer should have size of command line buf

When copying the command line buffer the target array should
at least have the same size.

Cf. definition of console_buffer in common/cli_readline.c.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
6 years agodisk: efi: correct the allocation size for mbr header in stack
Patrick Delaunay [Fri, 17 Nov 2017 09:08:18 +0000 (10:08 +0100)]
disk: efi: correct the allocation size for mbr header in stack

use ALLOC_CACHE_ALIGN_BUFFER_PAD for mbr header allocation
in stack to fix alloc issue in is_gpt_valid()

this patch fix also issue for GPT partition handling
with blocksize != 512 in set_protective_mbr()

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
6 years agoboard: atmel: add sama5d2_ptc_ek board
Ludovic Desroches [Fri, 17 Nov 2017 06:57:12 +0000 (14:57 +0800)]
board: atmel: add sama5d2_ptc_ek board

Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board
which was a prototype.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
6 years agoARM: at91: add sama5d2 smc header
Ludovic Desroches [Fri, 17 Nov 2017 06:57:11 +0000 (14:57 +0800)]
ARM: at91: add sama5d2 smc header

Add a header for SAMA5D2 SMC since it's not compatible with
SAMA5D3 one.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[wenyou: fix the wrong base address of the SMC register]
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
6 years agommc: atmel_sdhci: not on capabilities to set gck rate
Ludovic Desroches [Fri, 17 Nov 2017 06:51:27 +0000 (14:51 +0800)]
mmc: atmel_sdhci: not on capabilities to set gck rate

The capabilities have default values which doesn't reflect the reality
when it concerns the base clock and the mul value. Use a fixe rate
for the gck. 240 MHz is an arbitrary choice, it is a multiple of the
maximum SD clock frequency handle by the controller and it allows to
get a 400 kHz clock for the card initialisation.

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
6 years agoclk: at91: clk-generated: fix incorrect index of clk source
Wenyou Yang [Fri, 17 Nov 2017 06:50:22 +0000 (14:50 +0800)]
clk: at91: clk-generated: fix incorrect index of clk source

Differentiate the generic clock source selection value from the parent
clock index to fix the incorrect assignment of the generic clock
source selection.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
6 years agoclk: at91: clk-generated: select absolute closest rate
Ludovic Desroches [Fri, 17 Nov 2017 06:50:21 +0000 (14:50 +0800)]
clk: at91: clk-generated: select absolute closest rate

To get the same behavior as the Linux driver, instead of selecting
the closest inferior rate, select the closest inferior or superior
rate

Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
6 years agoclk: at91: Kconfig: fix the dependency of AT91_UTMI
Wenyou Yang [Fri, 17 Nov 2017 06:46:43 +0000 (14:46 +0800)]
clk: at91: Kconfig: fix the dependency of AT91_UTMI

What the AT91_UTMI depends on SPL_DM isn't right. AT91_UTMI is not
only used in SPL, also in other place, even if SPL_DM isn't enabled.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
6 years agomach-stm32: Factorize MPU's region config for STM32 SoCs
Patrice Chotard [Thu, 16 Nov 2017 07:59:21 +0000 (08:59 +0100)]
mach-stm32: Factorize MPU's region config for STM32 SoCs

MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family
and used a common MPU's region config.

Only one exception for STM32H7 which doesn't have device area
located at 0xA000 0000.

For STM32F4, configure_clocks() need to be moved from arch_cpu_init()
to board_early_init_f().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agostm32: migrate clock structs in include/stm32_rcc.h
Patrice Chotard [Wed, 15 Nov 2017 12:14:53 +0000 (13:14 +0100)]
stm32: migrate clock structs in include/stm32_rcc.h

In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.h

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoclk: clk_stm32fx: add clock configuration for mmc usage
Patrice Chotard [Wed, 15 Nov 2017 12:14:52 +0000 (13:14 +0100)]
clk: clk_stm32fx: add clock configuration for mmc usage

MMC block needs 48Mhz source clock, for that we choose
to select the SAI PLL.
Update also stm32_clock_get_rate() to retrieve the MMC
clock source needed in MMC driver.

STM32F4 uses a different RCC variant than STM32F7. For STM32F4
sdmmc clocks bit are located into dckcfgr register whereas there
are located into dckcfgr2 registers on STM32F7.
In both registers, bits CK48MSEL and SDMMC1SEL are located at
the same position.

Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agodm: misc: bind STM32F4/F7 clock from rcc MFD driver
Patrice Chotard [Wed, 15 Nov 2017 12:14:51 +0000 (13:14 +0100)]
dm: misc: bind STM32F4/F7 clock from rcc MFD driver

Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoconfigs: stm32f746-disco: enable MISC/DM_RESET/STM32_RESET and STM32_RCC
Patrice Chotard [Wed, 15 Nov 2017 12:14:50 +0000 (13:14 +0100)]
configs: stm32f746-disco: enable MISC/DM_RESET/STM32_RESET and STM32_RCC

This allows to add rcc MFD support to stm32f746-disco board
This rcc MFD driver manages clock and reset for STM32 SoCs family

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoclk: stm32fx: migrate define from rcc.h to driver
Patrice Chotard [Wed, 15 Nov 2017 12:14:49 +0000 (13:14 +0100)]
clk: stm32fx: migrate define from rcc.h to driver

STM32F4 doesn't get rcc.h file, to avoid compilation
issue, migrate RCC related defines from rcc.h to driver
file and remove rcc.h file.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoclk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c
Patrice Chotard [Wed, 15 Nov 2017 12:14:48 +0000 (13:14 +0100)]
clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c

Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnings.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoclk: stm32f7: add STM32F4 support
Patrice Chotard [Wed, 15 Nov 2017 12:14:47 +0000 (13:14 +0100)]
clk: stm32f7: add STM32F4 support

STM32F4 and STM32F7 RCC clock IP are very similar.
Same driver can be used to managed RCC clock for
these 2 SoCs.

Differences between STM32F4 and F7 will be managed using
different compatible string :
 _ overdrive clock is only supported by STM32F7
 _ different sys_pll_psc parameters can be used between STM32F4
   and STM32F7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoARM: DTS: stm32: update rcc compatible for STM32F746
Patrice Chotard [Wed, 15 Nov 2017 12:14:46 +0000 (13:14 +0100)]
ARM: DTS: stm32: update rcc compatible for STM32F746

Align the RCC compatible string with the one used by kernel.
It will allow to use the same clock driver for STM32F4
and STM32F7 and to manage the differences between the 2 SoCs

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoclk: stm32f7: add dedicated STM32F7 compatible string
Patrice Chotard [Wed, 15 Nov 2017 12:14:45 +0000 (13:14 +0100)]
clk: stm32f7: add dedicated STM32F7 compatible string

Add a dedicated stm32f7 compatible string to use clk_stm32f7
driver with both STM32F4 and STM32F7 SoCs.
It will be needed to manage differences between these 2 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoclk: stm32f7: retrieve PWR base address from DT
Patrice Chotard [Wed, 15 Nov 2017 12:14:44 +0000 (13:14 +0100)]
clk: stm32f7: retrieve PWR base address from DT

PWR IP is used to enable over-drive feature in
order to reach a higher frequency.
Get its base address from DT instead of hard-coded value

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agoARM: DTS: stm32: add pwrcfg node for stm32f746
Patrice Chotard [Wed, 15 Nov 2017 12:14:43 +0000 (13:14 +0100)]
ARM: DTS: stm32: add pwrcfg node for stm32f746

This node is needed to enable performance mode
when system frequency is set up to 200Mhz.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
6 years agotools: env: Add support for direct read/write UBI volumes
S. Lockwood-Childs [Wed, 15 Nov 2017 07:01:26 +0000 (23:01 -0800)]
tools: env: Add support for direct read/write UBI volumes

Up to now we were able to read/write environment data from/to UBI
volumes only indirectly by gluebi driver. This driver creates NAND MTD
on top of UBI volumes, which is quite a workaroung for this use case.

Add support for direct read/write UBI volumes in order to not use
obsolete gluebi driver.

Forward-ported from this patch:
http://patchwork.ozlabs.org/patch/619305/

Original patch:
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Forward port:
Signed-off-by: S. Lockwood-Childs <sjl@vctlabs.com>
6 years agoMerge git://git.denx.de/u-boot-nds32
Tom Rini [Thu, 30 Nov 2017 03:03:26 +0000 (22:03 -0500)]
Merge git://git.denx.de/u-boot-nds32

6 years agonds32: ftsdc010: Fix SD detech fail on AE3XX.
Rick Chen [Fri, 25 Aug 2017 06:03:00 +0000 (14:03 +0800)]
nds32: ftsdc010: Fix SD detech fail on AE3XX.

AE3XX can not support SD high-speed mode.
SW can work-around by removing HS capibility.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agonds32: ftsdc010: fix wait status error coding.
Rick Chen [Fri, 25 Aug 2017 06:02:13 +0000 (14:02 +0800)]
nds32: ftsdc010: fix wait status error coding.

Bit of DATA_END and DATA_CRC_OK shall be checked for
returning pass or fail of a request.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agonds32: board: Support ftsdc010 DM.
Rick Chen [Mon, 28 Aug 2017 08:17:13 +0000 (16:17 +0800)]
nds32: board: Support ftsdc010 DM.

AG101P/AE3XX enable ftsdc010 dm flow.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agonds32: dts: Support ftsdc010 DM.
Rick Chen [Thu, 1 Jun 2017 07:09:25 +0000 (15:09 +0800)]
nds32: dts: Support ftsdc010 DM.

Add dts to support ftsdc010 dm flow on AG101P/AE3XX platform.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agonds32: ftsdc010: Support ftsdc010 DM.
Rick Chen [Mon, 28 Aug 2017 08:44:11 +0000 (16:44 +0800)]
nds32: ftsdc010: Support ftsdc010 DM.

ftsdc010 support device tree flow.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agonds32: mmc: Support ftsdc010 DM.
Rick Chen [Tue, 14 Nov 2017 06:47:09 +0000 (14:47 +0800)]
nds32: mmc: Support ftsdc010 DM.

Add nds32_mmc to support ftsdc010 dm flow.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agodt-bindings: spi: Add andestech atcspi200 spi binding doc
Rick Chen [Wed, 15 Nov 2017 08:03:34 +0000 (16:03 +0800)]
dt-bindings: spi: Add andestech atcspi200 spi binding doc

Add a document to describe Andestech atcspi200 spi and
binding information.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agocosmetic: atcspi200: Rename function name as atcspi200
Rick Chen [Thu, 23 Nov 2017 06:17:35 +0000 (14:17 +0800)]
cosmetic: atcspi200: Rename function name as atcspi200

Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agospi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi
Rick Chen [Thu, 23 Nov 2017 06:19:36 +0000 (14:19 +0800)]
spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi

atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.

Signed-off-by: Rick Chen <rick@andestech.com>
6 years agoatcpit100: timer: Remove arch dependency.
Rick Chen [Thu, 23 Nov 2017 04:48:46 +0000 (12:48 +0800)]
atcpit100: timer: Remove arch dependency.

ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agodt-bindings: timer: Add andestech atcpit100 timer
Rick Chen [Thu, 23 Nov 2017 02:22:17 +0000 (10:22 +0800)]
dt-bindings: timer: Add andestech atcpit100 timer

Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agocosmetic: atcpit100_timer: Use device api to get platdata
Rick Chen [Tue, 28 Nov 2017 01:14:20 +0000 (09:14 +0800)]
cosmetic: atcpit100_timer: Use device api to get platdata

Use dev_get_platdata to get private platdata.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agocosmetic: atcpit100_timer: Rename function name as atcpit100
Rick Chen [Thu, 23 Nov 2017 02:15:20 +0000 (10:15 +0800)]
cosmetic: atcpit100_timer: Rename function name as atcpit100

Integrate function and struct name as atcpit100 will be
more reasonable.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoae3xx: timer: Rename AE3XX to ATCPIT100
Rick Chen [Tue, 28 Nov 2017 01:23:23 +0000 (09:23 +0800)]
ae3xx: timer: Rename AE3XX to ATCPIT100

ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoae3xx: timer: Fix ae3xx timer work abnormal in 64 bit.
Rick Chen [Thu, 23 Nov 2017 03:04:34 +0000 (11:04 +0800)]
ae3xx: timer: Fix ae3xx timer work abnormal in 64 bit.

It will be work fine with unsigned long declaretion in timer
register struct when system is 32 bit. But it will not work
well when system is 64 bit. Replace it by u32 and verify both
ok in 32/64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agogpio: rmobile: Set GPIO mode in GPSR when requested
Marek Vasut [Sun, 26 Nov 2017 17:08:53 +0000 (18:08 +0100)]
gpio: rmobile: Set GPIO mode in GPSR when requested

When requesting a GPIO, set the PFC GPSR register to GPIO mode,
otherwise the GPIO cannot work.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agopfc: rmobile: Add hook to configure pin as GPIO
Marek Vasut [Sun, 26 Nov 2017 17:07:29 +0000 (18:07 +0100)]
pfc: rmobile: Add hook to configure pin as GPIO

Add hook into the PFC driver to allow the GPIO driver to toggle
GPSR registers into GPIO mode when GPIO is requested.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agopinctrl: rmobile: Add support for setting single pins
Marek Vasut [Sun, 26 Nov 2017 16:42:16 +0000 (17:42 +0100)]
pinctrl: rmobile: Add support for setting single pins

Add code to handle single pins nodes from DT in addition to already
support groups handling.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Migrate boards to RCar IIC drivers
Marek Vasut [Mon, 27 Nov 2017 06:36:22 +0000 (07:36 +0100)]
ARM: rmobile: Migrate boards to RCar IIC drivers

Stop using the old ad-hoc SH I2C driver and use the new RCar IIC
driver instead. The SH I2C driver should be deprecated and removed
eventually.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Use PRR driver on all Gen3 boards
Marek Vasut [Thu, 9 Nov 2017 20:56:01 +0000 (21:56 +0100)]
ARM: rmobile: Use PRR driver on all Gen3 boards

Mark the PRR as u-boot,dm-pre-reloc in all Gen3 board DTs as it is
needed very early and turn on the CONFIG_SYSCON to allow the PRR
driver to bind as a syscon uclass.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Convert PRR to DM and OF control
Marek Vasut [Thu, 9 Nov 2017 20:49:48 +0000 (21:49 +0100)]
ARM: rmobile: Convert PRR to DM and OF control

Implement DM driver for the Renesas PRR into RCar cpu info and convert
all users with DM and OF enabled to this new driver. This means all of
the boards with DM and OF enabled can fetch PRR address from DT, which
is useful on ie. V3M which has different PRR address than the rest of
Gen3 SoCs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Remove SCIF configs
Marek Vasut [Tue, 28 Nov 2017 07:37:23 +0000 (08:37 +0100)]
ARM: rmobile: Remove SCIF configs

Since we use DM and DT, these SCIF configuration options are useless.
Remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Clean up ad-hoc clock macros
Marek Vasut [Mon, 27 Nov 2017 05:38:12 +0000 (06:38 +0100)]
ARM: rmobile: Clean up ad-hoc clock macros

As we have a proper clock framework driver, these macros are not
needed, so drop them and clean up the whitelist.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Zap ad-hoc DRAM configuration macros
Marek Vasut [Mon, 27 Nov 2017 05:01:20 +0000 (06:01 +0100)]
ARM: rmobile: Zap ad-hoc DRAM configuration macros

These macros are no longer needed since the DRAM configuration is parsed
from the DT. Drop them all.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Configure DRAM sizes from DT
Marek Vasut [Mon, 27 Nov 2017 04:37:53 +0000 (05:37 +0100)]
ARM: rmobile: Configure DRAM sizes from DT

Drop the ad-hoc DRAM configuration with macros and just decode
the DRAM configuration from device tree instead. This makes it
far cleaner and easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Zap rmobile_sysinfo on Gen3
Marek Vasut [Mon, 27 Nov 2017 04:48:30 +0000 (05:48 +0100)]
ARM: rmobile: Zap rmobile_sysinfo on Gen3

Since checkboard() is gone, rmobile_sysinfo is also pointless on Gen3.
Furthermore, nuke ad-hoc CONFIG_RCAR_BOARD_STRING which is also dead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Zap checkboard on Gen3
Marek Vasut [Mon, 27 Nov 2017 04:45:46 +0000 (05:45 +0100)]
ARM: rmobile: Zap checkboard on Gen3

The checkboard() function showing hard-coded board model for which the
U-Boot was built is superseded on Gen3 by show_board_info() displaying
the Model from device tree. Add small ifdef to stop compiling the
function into U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Drop CPU type ifdef from salvator-x
Marek Vasut [Sat, 25 Nov 2017 23:01:32 +0000 (00:01 +0100)]
ARM: rmobile: Drop CPU type ifdef from salvator-x

We can now use rmobile_get_cpu_type() to check the CPU ID rather
than using a macro, make it so.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Unify R8A7795 and R8A7796 in rmobile Makefile
Marek Vasut [Sat, 25 Nov 2017 23:05:08 +0000 (00:05 +0100)]
ARM: rmobile: Unify R8A7795 and R8A7796 in rmobile Makefile

Since both R8A7795 and R8A7796 now use the same files, unify the
Makefile entry to CONFIG_RCAR_GEN3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Unify memory map for RCar Gen3
Marek Vasut [Sat, 25 Nov 2017 22:24:01 +0000 (23:24 +0100)]
ARM: rmobile: Unify memory map for RCar Gen3

Unify the R7A7795 and R8A7796 memory maps in memmap-gen3 and, for now,
select which one is used based on which SoC is selected. Since this is
done in C code instead of statically assigned now, the decision can be
taken by PRR SoC match as well, which will be done in a subsequent patch.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Add PRR CPU ID macros
Marek Vasut [Sat, 25 Nov 2017 22:54:10 +0000 (23:54 +0100)]
ARM: rmobile: Add PRR CPU ID macros

Replace the ad-hoc values in the PRR CPU ID table with macros,
so that users can use rmobile_get_cpu_type() can compare the
returned value with these macros to figure out on which CPU they
are running.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Dispose of r8a779x.h for Gen3
Marek Vasut [Sat, 25 Nov 2017 21:53:04 +0000 (22:53 +0100)]
ARM: rmobile: Dispose of r8a779x.h for Gen3

These files no longer contain anything useful, so remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Stop using rcar-common/common.c on Gen3
Marek Vasut [Sat, 25 Nov 2017 21:43:57 +0000 (22:43 +0100)]
ARM: rmobile: Stop using rcar-common/common.c on Gen3

Since the Gen3 clock driver now has a .remove callback, it is no
longer necessary to shut the clock down before booting Linux in the
arch_preboot_os hook. Stop using it and while doing so, remove all
the ad-hoc config options which this hook used.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Zap Gen3 PFC tables
Marek Vasut [Wed, 13 Sep 2017 22:27:33 +0000 (00:27 +0200)]
ARM: rmobile: Zap Gen3 PFC tables

These old PFC tables are no longer needed as there is now a proper
PFC pinmux driver in drivers/pinctrl/renesas . Remove them .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Enable xHCI on RCar Gen3 boards
Marek Vasut [Sun, 10 Sep 2017 10:33:11 +0000 (12:33 +0200)]
ARM: rmobile: Enable xHCI on RCar Gen3 boards

Enable the XHCI support on all boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Clean up GIC macros
Marek Vasut [Tue, 28 Nov 2017 07:25:21 +0000 (08:25 +0100)]
ARM: rmobile: Clean up GIC macros

Pull out the GIC macros from the board configuration files
into the common Gen3 configuration file since these macros
are the same for all Gen3 systems.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Remove CONFIG_CMD_SDRAM from Salvator-X
Marek Vasut [Tue, 28 Nov 2017 07:20:34 +0000 (08:20 +0100)]
ARM: rmobile: Remove CONFIG_CMD_SDRAM from Salvator-X

This command is useless on Salvator-X as it is reading DRAM info from
SPD. We have no SPD on Salvator-X.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Drop SDHI address macros from Gen3
Marek Vasut [Sat, 25 Nov 2017 20:15:36 +0000 (21:15 +0100)]
ARM: rmobile: Drop SDHI address macros from Gen3

Since the RCar Gen3 no longer uses the SH SDHI driver, but rather
uses the Matsushita SD driver, which loads all the properties from
device tree, these macros are no longer used, remove them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Drop CONFIG_USB_MAX_CONTROLLER_COUNT on Gen3 boards
Marek Vasut [Sat, 25 Nov 2017 22:13:37 +0000 (23:13 +0100)]
ARM: rmobile: Drop CONFIG_USB_MAX_CONTROLLER_COUNT on Gen3 boards

The USB support has been switched to DM, so this macro is no
longer meaningful, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Enable Micrel KSZ90x1 PHY driver on ULCB
Marek Vasut [Sun, 26 Nov 2017 19:59:23 +0000 (20:59 +0100)]
ARM: rmobile: Enable Micrel KSZ90x1 PHY driver on ULCB

Enable the Micrel KSZ90x1 driver on ULCB, since the board is populated
with KSZ9031 and without this driver, the PHY cannot be operated.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoARM: rmobile: Fix eMMC signal voltage on ULCB
Marek Vasut [Sun, 26 Nov 2017 13:50:37 +0000 (14:50 +0100)]
ARM: rmobile: Fix eMMC signal voltage on ULCB

The eMMC is 1V8 device only and the signaling is always 1V8,
fix the DT for ULCB to describe the hardware correctly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agonet: ravb: Fix reset GPIO handling
Marek Vasut [Thu, 9 Nov 2017 21:49:19 +0000 (22:49 +0100)]
net: ravb: Fix reset GPIO handling

Fix handling of the reset GPIO. Drop the _nodev() suffix from the
gpio_request_by_name() call as there is now a proper DM capable
GPIO driver. Also check if the GPIO is valid before freeing it in
remove path, otherwise U-Boot will crash.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoi2c: rcar_iic: Add RCar IIC driver
Marek Vasut [Tue, 28 Nov 2017 07:02:27 +0000 (08:02 +0100)]
i2c: rcar_iic: Add RCar IIC driver

Add driver for the RCar IIC or DVFS I2C controller. This driver is based
on the SH I2C driver, but supports DM and DT probing as well as modern
I2C framework API.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoserial: sh: Unify R8A7795 and R8A7796 as Gen3
Marek Vasut [Sat, 25 Nov 2017 22:08:34 +0000 (23:08 +0100)]
serial: sh: Unify R8A7795 and R8A7796 as Gen3

Unify the CONFIG_R8A7795 and CONFIG_R8A7796 as CONFIG_RCAR_GEN3
so that every time we add a new SoC, we won't have to add more
stuff to this list.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: rmobile: Add R8A7796 xHCI clock
Marek Vasut [Fri, 10 Nov 2017 22:17:51 +0000 (23:17 +0100)]
clk: rmobile: Add R8A7796 xHCI clock

Add xHCI entry into the clock tables, so that the xHCI USB driver
can enable the clock for the xHCI block via clock framework.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoclk: rmobile: Move preboot clock shutdown to the driver
Marek Vasut [Sat, 25 Nov 2017 21:08:55 +0000 (22:08 +0100)]
clk: rmobile: Move preboot clock shutdown to the driver

The MSTP registers were poked in boards/renesas/rcar-common/common.c
in arch_preboot_os hook thus far to shut down the clock before Linux
takes over. With DM, this is no longer needed and we can do the same
in the clock driver .remove callback. This patch adds such a .remove
callback for R8A7795 and R8A7796.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agofdtdec: Support parsing multiple /memory nodes
Marek Vasut [Mon, 27 Nov 2017 04:32:42 +0000 (05:32 +0100)]
fdtdec: Support parsing multiple /memory nodes

It is legal to have multiple /memory nodes in a device tree . Currently,
fdtdec_setup_memory_size() only supports parsing the first node . This
patch extends the function such that if a particular /memory node does
no longer have further "reg" entries and CONFIG_NR_DRAM_BANKS still
allows for more DRAM banks, the code moves on to the next memory node
and checks it's "reg"s. This makes it possible to handle both systems
with single memory node with multiple entries and systems with multiple
memory nodes with single entry.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>