Bin Meng [Mon, 15 Jun 2015 10:40:19 +0000 (18:40 +0800)]
net: designware: Program MAC address to hardware after soft reset
commit f566c99 "net: Update hardware MAC address if it changes in env"
removes writing MAC address to designware controller after soft reset.
This makes designware ethernet port fail to work. Actually the MAC
address should always be programmed after soft reset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Mugunthan V N [Mon, 22 Jun 2015 09:13:10 +0000 (14:43 +0530)]
ARM: DRA72x: fix io delay calibration for ethernet
we currently use in-development IODelay values for DRA72x which are
proposed in the data sheet, however, DRA72x EVM uses DP83865 ethernet
Phy over RGMII. The PHY characteristics and routing choices made on
the EVM, make the current iodelay values fail ethernet communication.
Instead, we need to choose custom values for DRA72x-evm specifically
designed for the PHY and routing on the platform for ethernet to
function.
Simon Glass [Tue, 2 Jun 2015 17:08:21 +0000 (11:08 -0600)]
Revert "break build if it would produce broken binary"
The root cause of this problem should now be fixed.
This reverts commit a6a4c542d316b3401f0840ac5378743191bca851. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Tested-by: Pavel Machek <pavel@denx.de>
Simon Glass [Tue, 2 Jun 2015 17:08:20 +0000 (11:08 -0600)]
arm: Add ENTRY/ENDPROC to private libgcc functions
When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from
Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is
used to call these ARM functions, instead of plain BL, which will fail.
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Pavel Machek <pavel@denx.de>
Axel Lin [Tue, 14 Apr 2015 06:55:24 +0000 (14:55 +0800)]
gpio: lpc32xx: Use priv_data instead of platdata
The LPC32XX GPIO driver platdata currently contains GPIO state information,
which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:27 +0000 (19:57 +0800)]
sunxi: Add Sinlinx SinA33 defconfig
Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has
the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO
and GPIO headers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:26 +0000 (19:57 +0800)]
sunxi: Sync sun8i dts files with the linux kernel
Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2.
This adds a dts file for Sinlinx SinA33 dev board, and the required
changes in the .dtsi files.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:24 +0000 (19:57 +0800)]
sunxi: rsb: Enable R_PIO clock before configuring external pins
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.
Why this was working before is uncertain. Maybe the state was left
from a previous boot sequence, or RSB just happened to be the default
configuration. However with some A33 chips, SPL failed to configure
the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
board.
Reordering the calls fixed this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 23 Jun 2015 11:57:23 +0000 (19:57 +0800)]
sunxi: hardware-feature-specific function index defines for PORT F UART0
Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function
index defines") renamed all GPIO index defines, but missed the PORT F
UART0 setup functions.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Sanchayan Maity [Mon, 8 Jun 2015 07:10:41 +0000 (12:40 +0530)]
colibri_vf: Increase console IO buffer size to 1024
Increase console IO buffer size to 1024 from the previous value of 256.
The previous value was too short for editing environment variables like
ubiboot from the console.
Jagan Teki [Sat, 27 Jun 2015 10:37:54 +0000 (16:07 +0530)]
spi: Kconfig: Add TEGRA20_SLINK entry
Added TEGRA20_SLINK entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
Jagan Teki [Sat, 27 Jun 2015 10:34:05 +0000 (16:04 +0530)]
spi: Kconfig: Add TEGRA20_SFLASH entry
Added TEGRA20_SFLASH entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
Jagan Teki [Sat, 27 Jun 2015 10:27:53 +0000 (15:57 +0530)]
spi: Kconfig: Add TEGRA114_SPI entry
Added TEGRA114_SPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
Masahiro Yamada [Tue, 30 Jun 2015 09:27:00 +0000 (18:27 +0900)]
ARM: dts: UniPhier: sync device trees with the Linux kernel
This makes code diff much easier.
Device trees describe hardware attributes, which are independent
of software architecture. It generally makes sense to synchronize
them beyond software projects.
Jagan Teki [Fri, 26 Jun 2015 19:21:37 +0000 (00:51 +0530)]
spi: xilinx_spi: Add asm/io.h include file
This patch includes asm/io.h for readl and writel calls.
build errors:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe':
drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration]
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com>
Jagan Teki [Fri, 26 Jun 2015 19:21:34 +0000 (00:51 +0530)]
spi: zynq_spi: Add fdt support in driver
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
Jagan Teki [Fri, 26 Jun 2015 19:21:31 +0000 (00:51 +0530)]
dm: spi: zynq_spi: Convert to driver model
This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz -> frequency
- req_hz -> freq
- base -> regs
Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
Alexey Brodkin [Mon, 18 May 2015 13:56:26 +0000 (16:56 +0300)]
arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.:
a) Use the same functions for all cache ops (D$ Inv/Flush)
b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.
[2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.
[3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).
arc: implement slave cores kick-start for Linux kernel
With new SMP-enabled CPUs with ARC HS38 cores and corresponding support
in Linux kernel it's required to add basic SMP support in U-Boot.
Currently we assume the one and only core starts execution after
power-on. So most of things in U-Boot is handled in UP mode.
But when U-Boot is used for loading and starting Linux kernel right
before jumping to kernel's entry point U-Boot:
[1] Sets all slave cores to jump to the same address [kernel's entry
point]
[2] Really starts all slav cores
In ARC's implemetation of SMP in Linux kernel all cores are supposed to
run the same start-up code. But only core with ID 0 (master core)
processes further while others are looping waiting for master core to
complete some initialization.
That means it's safe to un-pause slave cores and let them execute kernel
- they will wait for master anyway.
spi, sf: Use offset and size in sf cmd from mtdpartition
With this patch, it is possible to get the offset and size information
from the mtdpartiton setting in "mtdparts", similiar to the
"nand" commandos.
=> sf
sf - SPI flash sub-system
Usage:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
and chip select
sf read addr offset|partition len - read `len' bytes starting at
`offset' to memory at `addr'
sf write addr offset|partition len - write `len' bytes from memory
at `addr' to flash at `offset'
sf erase offset|partition [+]len - erase `len' bytes from `offset'
`+len' round up `len' to block size
sf update addr offset|partition len - erase and write `len' bytes from memory
at `addr' to flash at `offset'
=>
for example "env" is defined in mtdparts:
=> sf read 13000000 env
device 0 offset 0xd0000, size 0x10000
SF: 65536 bytes @ 0xd0000 Read: OK
zynq-uboot> mtdparts add nor0 0x10000@0x0 env
zynq-uboot> sf erase env 0x10000
SF: 65536 bytes @ 0x0 Erased: OK
zynq-uboot> sf write 0x100 env
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Written: OK
zynq-uboot> sf read 0x40000 env
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Read: OK
Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Jagannadh Teki <jteki@openedev.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
mtd, nand: Move common functions from cmd_nand.c to common place
Move common functions from cmd_nand.c (for calculating offset
and size from cmdline paramter) to common place, so they could
used from other commands which use mtd partitions.
For onenand the arg_off_size() is left in common/cmd_onenand.c.
It should use now the common arg_off() function, but as I could
not test onenand I let it there ...
Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Changes from Heiko Schocher against this patch:
- Remove compile error if not defining CONFIG_SPI_FLASH_MTD:
LD drivers/mtd/spi/built-in.o
drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1
make: *** [drivers/mtd/spi] Fehler 2
- Add a README entry.
- Add correct writebufsize, to fit with Linux v3.14
MTD, UBI/UBIFS sync.
Note (From Jagan): For testing raw mtd parition erase/read/write operations
using cmd_sf, sf_mtd should be required to register the spi flash device to
MTD layer but the sf_mtd_info ops were not required until and unless if we
use any flash filesystem layer say for example UBI. Due to this the foot-print
got increased ~290bytes in non-UBI case here that should be acceptible.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Jagannadh Teki <jteki@openedev.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Haikun Wang [Sat, 27 Jun 2015 16:21:05 +0000 (21:51 +0530)]
defconfig: ls1021a: Add OF_CONTROL and DM support
PI and QSPI only work when boot from QSPI on ls1021a.
This patch only enable options in qspi boot defconfig.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Tested-by: Haikun Wang <haikun.wang@freescale.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Haikun Wang [Fri, 26 Jun 2015 11:30:41 +0000 (19:30 +0800)]
dm: ls1021aqds: dts: Use "spi_dataflash" driver instead of "spi_flash_std" for DSPI flash
The type of DSPI flash on ls1021aqds is AT45DB021, it has specail
commands and page-size.
Use the special spi flash driver instead of "spi_flash_std" driver.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Tested-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
Haikun Wang [Fri, 26 Jun 2015 11:30:27 +0000 (19:30 +0800)]
dm: sf: Add Atmel DataFlash spi flash driver
Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Example:
=> sf probe 1:0
SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 Bytes, total 264 KiB, revision d
=> sf erase 0 42000
SF: 270336 bytes @ 0x0 Erased: OK
=> mw.l 8200000045444342 20000
=> sf write 82000000 0 42000
SF: 270336 bytes @ 0x0 Written: OK
=> sf read 83000000 0 42000
SF: 270336 bytes @ 0x0 Read: OK
=> cmp.b 8200000083000000 42000
Total of 270336 byte(s) were the same
Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Tested-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chakra Divi <cdivi@openedev.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Kevin Smith [Mon, 18 May 2015 16:09:46 +0000 (16:09 +0000)]
db-88f6820-gp.h: Load data blobs into lower memory
By default on this platform, u-boot loads data into high memory
in the range of 0x7Fxxxxxx, which generates a data abort when the
kernel tries to read it. Config the u-boot environment to load
the device tree and initrd image into lower memory to make them
accessible to the kernel.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de>
Peng Fan [Thu, 11 Jun 2015 10:30:37 +0000 (18:30 +0800)]
imx: mx6 introuduce macro is_mx6dqp
Add a new revision CHIP_REV_2_0.
Introudce macro is_mx6dqp, dqp means Dual/Quad Plus.
Since Dual/Quad Plus use same cpu type with Dual/Quad, but different
revision(Major Lower), we use this macro for Dual/Quad Plus.
Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan [Thu, 11 Jun 2015 10:30:35 +0000 (18:30 +0800)]
imx: mx6 correct is_soc_rev usage
is_soc_rev should return a bool value, so use "==", but not "-",
change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0).
This patch also add space between "&" for cpu_type(rev) macro.
projects / u-boot / log