Jagan Teki [Fri, 24 Feb 2017 10:15:22 +0000 (15:45 +0530)]
imx6: icorem6_rqs: Update SPL board boot order for eMMC
SPL mmc device index is get based on the boot device, like
- BOOT_DEVICE_MMC1 for mmc device 0
- BOOT_DEVICE_MMC2 for mmc device 1
Currently BOOT_DEVICE_MMC1 is setting both SD/eSD and MMC/eMMC
boot devices in i.MX, So u-boot is loading from mmc device 0 even
"if the board booting from SD/eSD or MMC/eMMC"
So, this patch set BOOT_DEVICE_MMC2 for MMC/eMMC so for MMC/eMMC
the u-boot is loading from mmc device 1 and the board file need to
take care if the board have different mmc device order intialization.
Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Fri, 24 Feb 2017 10:15:20 +0000 (15:45 +0530)]
i.MX6UL: isiot: Switch the mmc env based on devno
Add board_mmc_get_env_dev
Switch the mmc env based on the mmc devno, instead of separately
defining a config item in include/configs using board_mmc_get_env_dev
- devno 0: sd/esd
- devno 1: mmc/emmc
Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Fri, 24 Feb 2017 10:15:19 +0000 (15:45 +0530)]
i.MX6UL: isiot: Add mmc_late_init
Let the runtime code can set the mmcdev and mmcroot based
on the devno using mmc_get_env_dev instead of defining
separately in build-time configs using mmc_late_init func.
Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Fri, 24 Feb 2017 10:15:18 +0000 (15:45 +0530)]
i.MX6UL: isiot: Add modeboot env via board_late_init
Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Fri, 24 Feb 2017 10:15:16 +0000 (15:45 +0530)]
imx6: isiotmx6ul: Update SPL board boot order for eMMC
SPL mmc device index is get based on the boot device, like
- BOOT_DEVICE_MMC1 for mmc device 0
- BOOT_DEVICE_MMC2 for mmc device 1
Currently BOOT_DEVICE_MMC1 is setting both SD/eSD and MMC/eMMC
boot devices in i.MX, So u-boot is loading from mmc device 0 even
"if the board booting from SD/eSD or MMC/eMMC"
So, this patch set BOOT_DEVICE_MMC2 for MMC/eMMC so for MMC/eMMC
the u-boot is loading from mmc device 1 and the board file need to
take care if the board have different mmc device order intialization.
Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Fri, 24 Feb 2017 10:15:13 +0000 (15:45 +0530)]
imx: spl: Update NAND bootmode detection bit
BOOT_CFG1[7:4] the NAND boot mode selection is done
only when BOOT_CFG1[7] is 1 hence update the NAND
boot mode detection bit case. This information available
on Table 8-11. NAND Boot eFUSE Descriptions, from IMX6DQRM.
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@openedev.com>
Jagan Teki [Fri, 24 Feb 2017 10:15:12 +0000 (15:45 +0530)]
imx6: Add imx6_src_get_boot_mode
For i.MX6, the bootmode determine code is part of spl_boot_device,
but there is might be a possibility for other part the code need to
check the desired boot mode for adding new functionalities like
modeboot env variable, or changing boot order etc.
So introduced imx6_src_get_boot_mode which actually reading the
boot mode register for desired modes.
More cleanup will be add in future patches.
Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
Jagan Teki [Fri, 24 Feb 2017 10:02:53 +0000 (15:32 +0530)]
configs: imx6: Don't define USDHC2_BASE_ADDR
USDHC base address will assigned by SPL using fsl_esdhc_initialize
and u-boot with devicetree, hence no remove base address assignment
in config files.
Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Peng Fan [Wed, 22 Feb 2017 08:21:52 +0000 (16:21 +0800)]
serial: lpuart: add i.MX7ULP support
Add i.MX7ULP support.
The buadrate calculation on i.MX7ULP is different,so add a new setbrg
function for i.MX7ULP.
Add a enum lpuart_devtype for runtime check for different platforms.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
Peng Fan [Wed, 22 Feb 2017 08:21:51 +0000 (16:21 +0800)]
serial: lpuart: restructure lpuart driver
Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg base and flags.
For 32Bit register access, use lpuart_read32/lpuart_write32 which handles
big/little endian.
For 8Bit register access, still use the orignal code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
Ye Li [Wed, 22 Feb 2017 08:21:47 +0000 (16:21 +0800)]
mx7ulp: Add iomux pins header file
Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins
to add IOMUX_CONFIG_MPORTS flags.
Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not
aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address
to aligin with it.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Wed, 22 Feb 2017 08:21:46 +0000 (16:21 +0800)]
mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULP
Update the mxc_ocotp driver to support i.MX7ULP.
The read/write sequence has some changes due to
PDN and OUT_STATUS registers added and TIME register is
removed. Also update the bank size and number.
Add is_mx7ulp macro in sys_proto.h
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Peng Fan [Wed, 22 Feb 2017 08:21:45 +0000 (16:21 +0800)]
gpio: Add Rapid GPIO2P driver for i.MX7ULP
Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP.
Have added all ports on RGPIO2P_0 and RGPIO2P_1.
The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set
to y to enable the drivers.
To use the GPIO function, the IBE and OBE needs to set in IOMUXC.
We did not set the bits in driver, but leave them to IOMUXC settings
of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number
for gpio APIs access.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Peng Fan [Wed, 22 Feb 2017 08:21:43 +0000 (16:21 +0800)]
imx: mx7ulp: Add soc level initialization codes and functions
Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very early u-boot
phase.
Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
is hard coded to a fixed value. This may change in future.
Reuse some code in imx-common.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Wed, 22 Feb 2017 08:21:42 +0000 (16:21 +0800)]
imx: mx7ulp: Add clock framework and functions
Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set
clock source, divider, clock rate and parent source.
Users need to include pcc.h to use the APIs to for peripherals clock. Each
peripheral clock is defined in enum pcc_clk type.
SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD
enablement and settings, and all SCG clock initialization. User need use enum
scg_clk to access each clock source.
In clock.c, we initialize necessary clocks at u-boot s_init and implement the
clock functions used by driver modules to operate clocks dynamically.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Wed, 22 Feb 2017 08:21:41 +0000 (16:21 +0800)]
imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1
Add a new driver under ULP directory to support its IOMUXC
controllers. The ULP has two IOMUXC, the IOMUXC0 is used
for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as
the default IOMUX in this driver. Any pins in IOMUXC0 needs
to configure with IOMUX_CONFIG_MPORTS in its mux_mode field.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Jernej Skrabec [Wed, 8 Mar 2017 23:34:38 +0000 (00:34 +0100)]
rockchip: video: Remove CSC initialization (HDMI)
Despite the comment in the code, CSC unit is never used. According to
the only public description of DW HDMI controller (i.MX6 manual), CSC
unit is bypassed in MC_FLOWCTRL register and then actually powered
down in MC_CLKDIS register.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Thu, 23 Feb 2017 16:30:40 +0000 (17:30 +0100)]
rockchip: rk3188: drop CONFIG_SYS_NO_FLASH
Commit e856bdcfb492 ("flash: complete CONFIG_SYS_NO_FLASH move with renaming")
obsoleted the CONFIG_SYS_NO_FLASH option, which still is in our
rk3188_common.h header, resulting in warnings like
The following new ad-hoc CONFIG options were detected:
CONFIG_SYS_NO_FLASH
So also drop it from the rk3188 header.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:56 +0000 (15:37 +0800)]
rockchip: rk3328: add defconfig for evb-rk3328
Enable board config for evb-rk3328.
SDcard and eMMC boot is OK in this initial version,
USB and EMAC function is not available now, will comes later.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:55 +0000 (15:37 +0800)]
rockchip: rk3328: add evb-rk3328 support
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:54 +0000 (15:37 +0800)]
rockchip: rk3328: add sysreset driver
Add rk3328 sysreset driver.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:53 +0000 (15:37 +0800)]
rockchip: rk3328: add pinctrl driver
Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:51 +0000 (15:37 +0800)]
rockchip: rk3328: add soc basic support
RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU.
It supports two USB2.0 EHCI ports. Other interfaces are very
much like RK3288, the DRAM are 32bit width address and support
address from 0 to 4GB-16MB range.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 07:37:50 +0000 (15:37 +0800)]
rockchip: rk3328: add device tree file
Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Wed, 22 Feb 2017 08:56:38 +0000 (16:56 +0800)]
rockchip: config: rk3399: enable SPL config for evb-rk3399
Enable all the CONFIGs which need by SPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Drop CONFIG_ROCKCHIP_DWMMC for now due to build error:
Move changes to arch/arm/mach-rockchip/Kconfig to this patch: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 23 Feb 2017 08:09:05 +0000 (16:09 +0800)]
rockchip: arm64: rk3399: add SPL support
Add SPL support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Drop Kconfig changes to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Wed, 22 Feb 2017 08:56:36 +0000 (16:56 +0800)]
rockchip: dts: rk3399: update for spl require driver
Add syscon and dmc node, and 'u-boot,dm-pre-reloc' option for
required driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Mon, 20 Feb 2017 03:08:16 +0000 (11:08 +0800)]
rockchip: tinker: configs: use correct mmc instance as boot target device
We are using wrong mmc instance as boot target device now. below Jaehoon Chung's
patch use mmc alias which correct it. That make tinker board can not find mmc
device. So give it correct mmc device instance.
Heiko Stübner [Sat, 18 Feb 2017 18:46:38 +0000 (19:46 +0100)]
rockchip: rk3188: Add main, spl and tpl boards
The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl
the resides in the rest of the sram and loads the regular U-Boot living
in regular ram.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:37 +0000 (19:46 +0100)]
rockchip: rk3188: Add sdram driver
The sdram controller blocks are very similar to the rk3288 in utilizing
memory scheduler, Designware uPCTL and Designware PUBL blocks, only
limited to one bank instead of two.
There are some minimal differences when setting up the ram, so it gets
a separate driver for the rk3188 but reuses the driver structs, as there
is no need to define the same again.
More optimization can happen when the modelling of the controller parts
in the dts actually follow the hardware layout hopefully at some point
in the future.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:36 +0000 (19:46 +0100)]
rockchip: rk3188: Add core support
Add the core architecture code for the rk3188.
It doesn't support the SPL yet, as because of some
unknown error it doesn't start yet.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Drop these defines from rk3188_common.h
CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION
CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART: Signed-off-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Sat, 18 Feb 2017 18:46:35 +0000 (19:46 +0100)]
rockchip: rk3188: Add core devicetree files
The rk3188 shares a lot of peripherals with the rk3066 and thus
has a common include called rk3xxx.dtsi. Add both this one and
the specialized rk3188 on top of it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Bring in required device clock binding files from Linux.
The clock trees for rk3066 and rk3188 are largely similar, which makes
them share the common parts in a shared header. While we focus on rk3188
for now, bring in both headers already for completeness sake.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:27 +0000 (19:46 +0100)]
rockchip: mkimage: Allow encoding of loader code in spl images
Rockchip SoCs allow the spl code to be rc4-encoded, not only the
image header, but only newer SoCs allow this encoding to be disabled.
The rk3188 is not part of those and requires its boot code to be
rc4-encoded with the regular key. So add the ability to do this
encoding via a setting on a per-soc basis when building spl images.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:26 +0000 (19:46 +0100)]
rockchip: Move bootrom-related declarations to a header
So far spl-boards have declared the back_to_brom() function as simple
extern in the files themself. That doesn't scale well if every boards
defines this on its own.
Therefore move the declarations to a bootrom header.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:25 +0000 (19:46 +0100)]
rockchip: Move bootrom helper compilation to a hidden option
Right now the ROCKCHIP_SPL_BACK_TO_BROM option both triggers
compilation of the bootrom hook-code as well as enabling the
behaviour of loading the full U-Boot via the boot.
New added socs may always need the bootrom code, while still
being able to decide between loading U-Boot regularly or via
the bootrom separately.
So move the compilation of the bootrom code to a hidden option
that gets selected by ROCKCHIP_SPL_BACK_TO_BROM, but can also
be selected by other parts.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stübner [Sat, 18 Feb 2017 18:46:24 +0000 (19:46 +0100)]
rockchip: rk3288: sdram: style fixes from rk3188 sdram review
The sdram IP blocks used on rk3066, rk3188 and rk3288 are very similar
and we want to unify things once all 3 work as expected.
Therefore try to keep the rk3288 sdram driver in line by applying the
general review comments received for the rk3188 variant to it as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Sat, 18 Feb 2017 18:46:22 +0000 (19:46 +0100)]
rockchip: clk: rk3288: limit gpll and cpll init to SPL build
The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Sat, 18 Feb 2017 18:46:21 +0000 (19:46 +0100)]
dm: allow limiting pre-reloc markings to spl or tpl
Right now the u-boot,dm-pre-reloc flag will make each marked node
always appear in both spl and tpl. But systems needing an additional
tpl might have special constraints for each, like the spl needing to
be very tiny.
So introduce two additional flags to mark nodes for only spl or tpl
environments and introduce a function dm_fdt_pre_reloc to automate
the necessary checks in code instances checking for pre-relocation
flags.
The behaviour of the original flag stays untouched and still marks
a node for both spl and tpl.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 13 Feb 2017 09:38:59 +0000 (17:38 +0800)]
rockchip: arm64: rk3399: syscon addition for rk3399
rk3399 has different syscon registers which may used in spl,
add to support rk3399 spl.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 13 Feb 2017 09:38:58 +0000 (17:38 +0800)]
rockchip: pinctrl: rk3399: add the of-platdata support
Do not use the API which of-platdata not support.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 13 Feb 2017 09:38:57 +0000 (17:38 +0800)]
rockchip: sdhci: rk3399: update driver to support of-platdata
Change some API in order to enable of-platdata.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag and fix pmuclk_init() build warning: Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 13 Feb 2017 09:38:55 +0000 (17:38 +0800)]
rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h
rk3399 grf register bit defenitions should locate in header
file, so that not only pinctrl can use it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Eddie Cai [Wed, 15 Mar 2017 14:43:28 +0000 (08:43 -0600)]
spl: Add spl_early_init()
At present malloc_base/_limit/_ptr are not initialised in spl_init() when
we call spl_init() in board_init_f(). This is due to a recent change aimed
at avoiding overwriting the malloc area set up on some boards by
spl_relocate_stack_gd().
However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
skip setting up the memory area in spl_init() which is obviously wrong.
To fix this, add a new function spl_early_init() which can be called in
board_init_f().
Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit) Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Rewrote spl_{,early_}init() to avoid duplicate code:
Rewrite/expand commit message: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Eddie Cai <eddie.cai.linux@gmail.com>
Masahiro Yamada [Thu, 9 Mar 2017 07:28:25 +0000 (16:28 +0900)]
arm64: booti: allow to place kernel image anywhere in physical memory
At first, the ARM64 Linux booting requirement recommended that the
kernel image be placed text_offset bytes from 2MB aligned base near
the start of usable system RAM because memory below that base address
was unusable at that time.
This requirement was relaxed by Linux commit a7f8de168ace ("arm64:
allow kernel Image to be loaded anywhere in physical memory").
Since then, the bit 3 of the flags field indicates the tolerance
of the kernel physical placement. If this bit is set, the 2MB
aligned base may be anywhere in physical memory. For details, see
Documentation/arm64/booting.txt of Linux.
The booti command should be also relaxed. If the bit 3 is set,
images->ep is respected, and the image is placed at the nearest
bootable location. Otherwise, it is relocated to the start of the
system RAM to keep the original behavior.
Another wrinkle we need to take care of is the unknown endianness of
text_offset for a kernel older than commit a2c1d73b94ed (i.e. v3.16).
We can detect this based on the image_size field. If the field is
zero, just use a fixed offset 0x80000.
Masahiro Yamada [Mon, 13 Mar 2017 08:43:16 +0000 (17:43 +0900)]
tools: fix cross-compiling tools when HOSTCC is overridden
Richard reported U-Boot tools issues in OpenEmbedded/Yocto project.
OE needs to be able to change the default compiler. If we pass in
HOSTCC through the make command, it overwrites all HOSTCC instances,
including ones in tools/Makefile and tools/env/Makefile, which breaks
"make cross_tools" and "make env", respectively.
Add "override" directives to avoid overriding HOSTCC instances that
really need to point to the cross-compiler.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Richard Purdie <richard.purdie@linuxfoundation.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Ladislav Michl [Sat, 18 Feb 2017 23:24:49 +0000 (00:24 +0100)]
igep00x0: fixup FDT according to detected flash type
Leave only detected flash type enabled in FTD as otherwise GPMC CS is
claimed (and never freed) by Linux, causing 'concurent' flash type
not to be probed.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Ladislav Michl [Sat, 18 Feb 2017 23:23:39 +0000 (00:23 +0100)]
igep00x0: disable environment
ISEE's U-Boot and Linux are using 1bit ECC scheme, while we
switched to 8bit ECC to fullfill flash specification requirements.
However when trying to run U-Boot on board with 1bit ECC'd data
on flash, UBI code takes several minutes to pass scan as reading
of every block ends with ecc error (which is also printed on
console).
So, until proper solution is developed, disable environment
alltogether.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Patrice Chotard [Tue, 21 Feb 2017 12:37:12 +0000 (13:37 +0100)]
board: Add STMicroelectronics STiH410-B2260 support
This is a 96Board compliant board based on STiH410 SoC:
- 1GB DDR
- On-Board USB combo WiFi/Bluetooth RTL8723BU
with PCB soldered antenna
- Ethernet 1000-BaseT
- SATA
- HDMI
- 2 x USB2.0 type A
- 1 x USB2.0 type micro-AB
- SD card slot
- High speed connector (SD/I2C/USB interfaces)
- Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces)
Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log