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7 years agodm: video: Add color ANSI escape sequence support
Rob Clark [Wed, 13 Sep 2017 22:12:22 +0000 (18:12 -0400)]
dm: video: Add color ANSI escape sequence support

Note that this doesn't differentiate (due to lack of information in
video_priv) between different possible component orders for 32bpp.
But the main user at this point is efi_loader, and GOP expects xBGR
so any video drivers that this is incorrect for already have problems.
(Also, conveniently, this matches what simple-framebuffer bindings
expect for kernels that use the simple-framebuffer DT binding to
take over the bootloader display.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
7 years agodm: video: Add basic ANSI escape sequence support
Rob Clark [Wed, 13 Sep 2017 22:12:21 +0000 (18:12 -0400)]
dm: video: Add basic ANSI escape sequence support

Really just the subset that is needed by efi_console.  Perhaps more will
be added later, for example color support would be useful to implement
efi_cout_set_attribute().

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: video: Fix cache flushes
Rob Clark [Wed, 13 Sep 2017 22:12:20 +0000 (18:12 -0400)]
dm: video: Fix cache flushes

Content can come to screen via putc() and we cannot always rely on
updates ending with a puts().  This is the case with efi_console output
to vidconsole.  Fixes corruption with Shell.efi.

Signed-off-by: Rob Clark <robdclark@gmail.com>
7 years agoboard: at91sam9x5ek: Convert to CONFIG_DM_VIDEO
Wenyou Yang [Mon, 18 Sep 2017 07:26:01 +0000 (15:26 +0800)]
board: at91sam9x5ek: Convert to CONFIG_DM_VIDEO

Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: sama5d4_xplained: Convert to CONFIG_DM_VIDEO
Wenyou Yang [Mon, 18 Sep 2017 07:26:00 +0000 (15:26 +0800)]
board: sama5d4_xplained: Convert to CONFIG_DM_VIDEO

Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: sama5d4ek: Convert to CONFIG_DM_VIDEO
Wenyou Yang [Mon, 18 Sep 2017 07:25:59 +0000 (15:25 +0800)]
board: sama5d4ek: Convert to CONFIG_DM_VIDEO

Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: sama5d3xek: Convert to CONFIG_DM_VIDEO
Wenyou Yang [Mon, 18 Sep 2017 07:25:58 +0000 (15:25 +0800)]
board: sama5d3xek: Convert to CONFIG_DM_VIDEO

Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: sama5d2_xplained: Convert to CONFIG_DM_VIDEO
Wenyou Yang [Mon, 18 Sep 2017 07:25:57 +0000 (15:25 +0800)]
board: sama5d2_xplained: Convert to CONFIG_DM_VIDEO

Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoMerge git://git.denx.de/u-boot-mmc
Tom Rini [Fri, 29 Sep 2017 03:31:11 +0000 (23:31 -0400)]
Merge git://git.denx.de/u-boot-mmc

7 years agommc: sdhci-cadence: set timing mode register depending on frequency
Masahiro Yamada [Thu, 28 Sep 2017 12:13:10 +0000 (21:13 +0900)]
mmc: sdhci-cadence: set timing mode register depending on frequency

The MMC framework in U-Boot does not support a systematic API for
timing switch like mmc_set_timing() in Linux.

U-Boot just provides a hook to change the clock frequency via
mmc_set_clock().  It is up to drivers if additional register
settings are needed.

This driver needs to set a correct timing mode into a register when
it migrates to a different speed mode.  Only increasing clock frequency
could result in setup/hold timing violation.

The timing mode should be decided by checking MMC_TIMING_* like
drivers/mmc/host/sdhci-cadence.c in Linux, but "timing" is not
supported by U-Boot for now.  Just use mmc->clock to decide the
timing mode.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agospl: spl_mmc: add __maybe_unused to mmc_load_image_raw_sector()
Seung-Woo Kim [Tue, 19 Sep 2017 04:29:45 +0000 (13:29 +0900)]
spl: spl_mmc: add __maybe_unused to mmc_load_image_raw_sector()

If there are no CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR and CONFIG_SPL_OS_BOOT,
there is unused-function build warning. Add __maybe_unused macro
to remove the warning.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
7 years agommc: uniphier-sd: Add vqmmc regulator support
Marek Vasut [Fri, 15 Sep 2017 19:10:54 +0000 (21:10 +0200)]
mmc: uniphier-sd: Add vqmmc regulator support

Add initial support for setting the vqmmc regulator. Since we do not
support 1V8 modes, set the regulator to 3V3 and enable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agommc: uniphier-sd: Update the file to match V3 patchset
Marek Vasut [Tue, 26 Sep 2017 18:05:34 +0000 (20:05 +0200)]
mmc: uniphier-sd: Update the file to match V3 patchset

Old version of the uniphier-sd 64bit IO support patchset V1 was
applied by the maintainer, update the uniphier-sd.c with the
changes from the V3 of the patchset.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoMerge git://git.denx.de/u-boot-nds32
Tom Rini [Thu, 28 Sep 2017 13:03:05 +0000 (09:03 -0400)]
Merge git://git.denx.de/u-boot-nds32

7 years agommc: Add MMC support for stm32h7 Socs
Patrice Chotard [Mon, 4 Sep 2017 15:56:22 +0000 (17:56 +0200)]
mmc: Add MMC support for stm32h7 Socs

This patch adds SD/MMC support for STM32H7 SoCs.

Here is an extraction of SDMMC main features, embedded in
STM32H7 SoCs.
The SD/MMC block include the following:
 _ Full compliance with MultiMediaCard System Specification
   Version 4.51. Card support for three different databus modes:
   1-bit (default), 4-bit and 8-bit.
 _ Full compatibility with previous versions of MultiMediaCards
   (backward compatibility).
 _ Full compliance with SD memory card specifications version 4.1.
   (SDR104 SDMMC_CK speed limited to maximum allowed IO speed,
    SPI mode and UHS-II mode not supported).
 _ Full compliance with SDIO card specification version 4.0.
   Card support for two different databus modes: 1-bit (default)
   and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO
   speed, SPI mode and UHS-II mode not supported).
 _ Data transfer up to 208 Mbyte/s for the 8 bit mode.
   (depending maximum allowed IO speed).
 _ Data and command output enable signals to control external
   bidirectional drivers.

The current version of the SDMMC supports only one SD/SDIO/MMC card
at any one time and a stack of MMC Version 4.51 or previous.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agonds32: Fix io.h warning message about readb
rick [Thu, 21 Sep 2017 02:14:56 +0000 (10:14 +0800)]
nds32: Fix io.h warning message about readb

It is caused from asm/io.h declare different input type.

Signed-off-by: rick <rick@andestech.com>
7 years agoMerge git://git.denx.de/u-boot-usb
Tom Rini [Wed, 27 Sep 2017 13:39:48 +0000 (09:39 -0400)]
Merge git://git.denx.de/u-boot-usb

7 years agousb: dwc2: Align size of invalidating dcache before starting DMA
Seung-Woo Kim [Mon, 31 Jul 2017 09:08:10 +0000 (18:08 +0900)]
usb: dwc2: Align size of invalidating dcache before starting DMA

During using dwc2 usb gadget, if usb message size is too small,
following cache misaligned warning is shown:

   CACHE: Misaligned operation at range [bfdbcb00bfdbcb04]

Align size of invalidating dcache before starting DMA to remove the
warning.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
7 years agousb: kbd: Set a default polling mechanism for USB keyboard
Bin Meng [Wed, 13 Sep 2017 08:19:43 +0000 (01:19 -0700)]
usb: kbd: Set a default polling mechanism for USB keyboard

The choice of "USB keyboard polling" cannot be optional as without
one mechanism being set, it just doesn't work. Set the default one
to CONFIG_SYS_USB_EVENT_POLL.

Fixes: ecad7051 ("configs: Migrate all of the existing USB symbols, except fastboot")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7 years agousb: host: ehci-generic: convert to livetree
Philipp Tomsich [Tue, 12 Sep 2017 15:32:28 +0000 (17:32 +0200)]
usb: host: ehci-generic: convert to livetree

Update the generic EHCI driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agousb: dwc2: convert to livetree
Philipp Tomsich [Tue, 12 Sep 2017 15:32:27 +0000 (17:32 +0200)]
usb: dwc2: convert to livetree

Update the DWC2 USB driver to support a live tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: xhci: Convert to livetree
Philipp Tomsich [Tue, 12 Sep 2017 15:32:25 +0000 (17:32 +0200)]
rockchip: xhci: Convert to livetree

Update the Rockchip xhci wrapper driver to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agodm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled
Bin Meng [Thu, 7 Sep 2017 13:13:21 +0000 (06:13 -0700)]
dm: usb: storage: Fix broken read/write when both EHCD and xHCD are enabled

When EHCD and xHCD are enabled at the same time, USB storage device
driver will fail to read/write from/to the storage device attached
to the xHCI interface, due to its transfer blocks exceeds the xHCD
driver limitation.

With driver model, we have an API to get the controller's maximum
transfer size and we can use that to determine the storage driver's
capability of read/write.

Note: the non-DM version driver is still broken with xHCD and the
intent here is not to fix the non-DM one, since the xHCD itself is
already broken in places like 3.0 hub support, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7 years agousb: storage: Refactor to use max_xfer_blk from struct us_data
Bin Meng [Thu, 7 Sep 2017 13:13:20 +0000 (06:13 -0700)]
usb: storage: Refactor to use max_xfer_blk from struct us_data

This adds a new memeber max_xfer_blk in struct us_data to record
the maximum number of transfer blocks for the storage device.

It is set per HCD setting, and so far is to 65535 for EHCD and 20
for everything else.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7 years agodm: usb: ehci: Implement get_max_xfer_size() operation
Bin Meng [Thu, 7 Sep 2017 13:13:19 +0000 (06:13 -0700)]
dm: usb: ehci: Implement get_max_xfer_size() operation

EHCD can handle any transfer length as long as there is enough free
heap space left, hence set the theoretical max number SIZE_MAX.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7 years agodm: usb: xhci: Implement get_max_xfer_size() operation
Bin Meng [Thu, 7 Sep 2017 13:13:18 +0000 (06:13 -0700)]
dm: usb: xhci: Implement get_max_xfer_size() operation

xHCD allocates one segment which includes 64 TRBs for each endpoint
and the last TRB in this segment is configured as a link TRB to form
a TRB ring. Each TRB can transfer up to 64K bytes, however data
buffers referenced by transfer TRBs shall not span 64KB boundaries.
Hence the maximum number of TRBs we can use in one transfer is 62.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7 years agodm: usb: Add a new USB controller operation 'get_max_xfer_size'
Bin Meng [Thu, 7 Sep 2017 13:13:17 +0000 (06:13 -0700)]
dm: usb: Add a new USB controller operation 'get_max_xfer_size'

The HCD may have limitation on the maximum bytes to be transferred
in a USB transfer. USB class driver needs to be aware of this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7 years agousb: xhci: Set number of event segments and entries to 1
Marek Vasut [Tue, 12 Sep 2017 21:02:08 +0000 (23:02 +0200)]
usb: xhci: Set number of event segments and entries to 1

The Linux kernel driver sets the number of event segments and entries
to 1 , while the initial import of the xhci code set that values to 3
for reasons unknown. While most controllers are fine with more event
segments with more entries, there are standard-conformant controllers
(ie. Renesas RCar xHCI) which only support 1 event segment.

Set the number of event segments and event entries back to 1 to allow
such controllers to work with U-Boot xHCI stack. Note that the Renesas
controller correctly indicates ERST Max = 1 in HCSPARAMS2[7:4] .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
7 years agoMerge git://www.denx.de/git/u-boot-cfi-flash
Tom Rini [Tue, 26 Sep 2017 23:38:04 +0000 (19:38 -0400)]
Merge git://www.denx.de/git/u-boot-cfi-flash

7 years agoGPT: incomplete initialization in allocate_disk_part
Heinrich Schuchardt [Thu, 21 Sep 2017 17:03:06 +0000 (19:03 +0200)]
GPT: incomplete initialization in allocate_disk_part

memset(newpart, '\0', sizeof(newpart));
only initializes the firest 4 or 8 bytes of *newpart and not the whole
structure disk_part.

We should use sizeof(struct disk_part).

Instead of malloc and memset we can use calloc.

Identified by cppcheck.

Fixes: 09a49930e41 GPT: read partition table from device into a data structure
Reported-by: Coverity (CID: 167228)
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoMerge git://www.denx.de/git/u-boot-marvell
Tom Rini [Tue, 26 Sep 2017 12:26:57 +0000 (08:26 -0400)]
Merge git://www.denx.de/git/u-boot-marvell

7 years agomtd: cfi: Add support for status register polling
Marek Vasut [Tue, 12 Sep 2017 17:09:31 +0000 (19:09 +0200)]
mtd: cfi: Add support for status register polling

The status register is optional in the AMD command sets, but it's
presence can be checked by reading out CFI table entry 0xc bit 0.
If the register is present, prefer using it's bit 7 to determine
if the flash is busy over reading the flash ; this is needed ie.
on Hyperflash memories.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agomtd: cfi: Zap cfi_flash_base in DM case
Marek Vasut [Tue, 12 Sep 2017 17:09:08 +0000 (19:09 +0200)]
mtd: cfi: Zap cfi_flash_base in DM case

Embed the flash base into struct flash_info instead of having ad-hoc
static array in the code. This does not only remove static variable,
but also allows CFI-like controllers, ie. HyperFlash ones, to use most
of the CFI flash code by populating the flash_info with matching base
address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm: mvebu: clearfog: document boot from UART
Baruch Siach [Sun, 24 Sep 2017 12:50:18 +0000 (15:50 +0300)]
arm: mvebu: clearfog: document boot from UART

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm: mvebu: fix boot from UART on ClearFog Base
Baruch Siach [Sun, 24 Sep 2017 12:50:17 +0000 (15:50 +0300)]
arm: mvebu: fix boot from UART on ClearFog Base

The ClearFog Base boot from UART when setting the DIP switches to 01001.
Unfortunately, the SPL code sometimes fails to detect the UART boot
method at run-time. Add an alternative SAR UART boot value to fix this.

Note that this alternative value is not documented (Armada 38x Hardware
Specifications, Table 48). But experimentations showed it on the
ClearFog Base.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoARM: mvebu: handle unused DRAM banks with ECC enabled
Chris Packham [Fri, 22 Sep 2017 16:50:31 +0000 (04:50 +1200)]
ARM: mvebu: handle unused DRAM banks with ECC enabled

dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not
work because mvebu_sdram_bs() returns 0 and the code was subtracting 1
before checking the size. Remove the -1 from the bank size and the +1
from the total which will skip unused banks and still calculate the
correct size. Put the -1 where it is needed for scrubbing via the xor
engine.

Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoARM: mvebu: add SAR frequency values for 1.8/2.0GHz
Chris Packham [Tue, 5 Sep 2017 05:03:26 +0000 (17:03 +1200)]
ARM: mvebu: add SAR frequency values for 1.8/2.0GHz

The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
variants to the sar_freq_tab.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoARM: mvebu: add additional information to board_add_ram_info()
Joshua Scott [Mon, 4 Sep 2017 05:38:32 +0000 (17:38 +1200)]
ARM: mvebu: add additional information to board_add_ram_info()

Display more information about the current RAM configuration. With these
changes the output on a 88F6820 board is

  SoC:   MV88F6820-A0 at 1600 MHz
  DRAM:  2 GiB (800 MHz, 32-bit, ECC not enabled)

Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoARM: mvebu: Add SoC IDs for Marvell's integrated CPUs
Chris Packham [Mon, 4 Sep 2017 05:38:31 +0000 (17:38 +1200)]
ARM: mvebu: Add SoC IDs for Marvell's integrated CPUs

These SoCs are network packet processors (switch chips) with integrated
ARMv7 cores. They share a great deal of commonality with the Armada-XP
CPUs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoarm: mvebu: Remove theadorable_defconfig
Stefan Roese [Wed, 30 Aug 2017 07:55:01 +0000 (09:55 +0200)]
arm: mvebu: Remove theadorable_defconfig

Currently, we support 2 "theadorable" MVEBU build targets. One with a
stripped down configuration (theadorable) and one with a full blown
configuration (theadorable_debug), including PCI, ethernet etc. When
we introduced these configs, the plan was to remove the debug version
at some point. But now it seems better to keep the full-blown version
and remove the "non-debug" version instead.

At a later stage, I will rename the remaining "theadorable_debug"
target into a more fitting one.

Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoARM: mvebu: Convert CONFIG_MVNETA to Kconfig
Chris Packham [Mon, 21 Aug 2017 08:17:03 +0000 (20:17 +1200)]
ARM: mvebu: Convert CONFIG_MVNETA to Kconfig

This converts the following to Kconfig:
   CONFIG_MVNETA

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
7 years agoMerge git://git.denx.de/u-boot-spi
Tom Rini [Mon, 25 Sep 2017 21:28:31 +0000 (17:28 -0400)]
Merge git://git.denx.de/u-boot-spi

7 years agoMerge git://git.denx.de/u-boot-mmc
Tom Rini [Mon, 25 Sep 2017 21:28:16 +0000 (17:28 -0400)]
Merge git://git.denx.de/u-boot-mmc

7 years agospi: fsl_qspi: Copy 16 byte aligned data in TX FIFO
Suresh Gupta [Mon, 5 Jun 2017 09:07:20 +0000 (14:37 +0530)]
spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agoFix s25fl256s position in spi_flash_ids list
Vsevolod Gribov [Fri, 15 Sep 2017 14:21:07 +0000 (17:21 +0300)]
Fix s25fl256s position in spi_flash_ids list

Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID.
As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot
incorrectly detects FS flash as FL. Thus its better to compare with
S25FS256S first.

Signed-off-by: Vsevolod Gribov <vgribov@larch-networks.com>
[Added S-o-b]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agosf: Fix S25FL116K entry
Marek Vasut [Thu, 14 Sep 2017 21:15:10 +0000 (23:15 +0200)]
sf: Fix S25FL116K entry

The flash chip is 2 MiB , organized as 32 x 64 kiB sectors .
Rectify the entry to match the datasheet, reality and Linux SNOR IDs.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agomtd/spi: Add MT35XU512ABA1G12 NOR flash support
Yogesh Gaur [Thu, 31 Aug 2017 04:56:31 +0000 (10:26 +0530)]
mtd/spi: Add MT35XU512ABA1G12 NOR flash support

Add MT35XU512ABA1G12 parameters to NOR flash parameters array.

The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agospi: fsl_qspi: Add controller busy check before new spi operation
Suresh Gupta [Wed, 30 Aug 2017 14:36:33 +0000 (20:06 +0530)]
spi: fsl_qspi: Add controller busy check before new spi operation

It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agospi: mxc_spi: support driver model
Peng Fan [Wed, 9 Aug 2017 05:09:33 +0000 (13:09 +0800)]
spi: mxc_spi: support driver model

Add driver model support for mxc spi driver.
Most functions are restructured to be reused by DM and non-DM.
Tested on mx6slevk/mx6qsabresd board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
7 years agotools/mkimage: Make the path to the dtc binary that mkimage calls configurable
Tom Rini [Sun, 24 Sep 2017 03:14:33 +0000 (23:14 -0400)]
tools/mkimage: Make the path to the dtc binary that mkimage calls configurable

In some cases, such as FreeBSD, the path to an alternative dtc needs to
be used.  Rather than override the one given in the Makefile on the
command line, make this part of the build configuration.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agodtc: Switch to building and using our own dtc unless provided
Tom Rini [Sat, 23 Sep 2017 17:00:57 +0000 (13:00 -0400)]
dtc: Switch to building and using our own dtc unless provided

This makes us act like the Linux Kernel does and allow for dtc to be
provided externally but otherwise we use the version of dtc that is
included in the sources.  This in turn means that we can drop the
checkdtc logic.  We select DTC in the cases where we will need the dtc
tool provided.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoscripts/dtc: Update to upstream version v1.4.4-50-gfe50bd1ecc1d
Tom Rini [Sat, 23 Sep 2017 21:31:59 +0000 (17:31 -0400)]
scripts/dtc: Update to upstream version v1.4.4-50-gfe50bd1ecc1d

This adds the following commits from upstream:

fe50bd1ecc1d fdtget: Split out cell list display into a new function
62d812308d11 README: Add a note about test_tree1.dts
5bed86aee9e8 pylibfdt: Add support for fdt_subnode_offset()
46f31b65b3b3 pylibfdt: Add support for fdt_node_offset_by_phandle()
a3ae43723687 pylibfdt: Add support for fdt_parent_offset()
a198af80344c pylibfdt: Add support for fdt_get_phandle()
b9eba92ea50f tests: Return a failure code when any tests fail
155faf6cc209 pylibfdt: Use local pylibfdt module
50e5cd07f325 pylibfdt: Add a test for use of uint32_t
ab78860f09f5 pylibfdt: Add stdint include to fix uint32_t
36f511fb1113 tests: Add stacked overlay tests on fdtoverlay
1bb00655d3e5 fdt: Allow stacked overlays phandle references
a33c2247ac8d Introduce fdt_setprop_placeholder() method
0016f8c2aa32 dtc: change default phandles to ePAPR style instead of both
e3b9a9588a35 tests: fdtoverlay unit test
42409146f2db fdtoverlay: A tool that applies overlays
aae22722fc8d manual: Document missing options
13ce6e1c2fc4 dtc: fix sprintf() format string error, again
d990b8013889 Makefile: Fix build on MSYS2 and Cygwin
51f56dedf8ea Clean up shared library compile/link options
21a2bc896e3d Suppress expected error message in fdtdump test
2a42b14d0d03 dtc: check.c fix compile error
a10cb3c818d3 Fix get_node_by_path string equality check
548aea2c436a fdtdump: Discourage use of fdtdump
c2258841a785 fdtdump: Fix over-zealous version check
9067ee4be0e6 Fix a few whitespace and style nits
e56f2b07be38 pylibfdt: Use setup.py to build the swig file
896f1c133265 pylibfdt: Use Makefile constructs to implement NO_PYTHON
90db6d9989ca pylibfdt: Allow setup.py to operate stand-alone
e20d9658cd8f Add Coverity Scan support
b04a2cf08862 pylibfdt: Fix code style in setup.py
1c5170d3a466 pylibfdt: Rename libfdt.swig to libfdt.i
580a9f6c2880 Add a libfdt function to write a property placeholder
ab15256d8d02 pylibfdt: Use the call function to simplify the Makefile
9f2e3a3a1f19 pylibfdt: Use the correct libfdt version in the module
e91c652af215 pylibfdt: Enable installation of Python module
8a892fd85d94 pylibfdt: Allow building to be disabled
741cdff85d3e .travis.yml: Add builds with and without Python library prerequisites
14c4171f4f9a pylibfdt: Use package_dir to set the package directory
89a5062ab231 pylibfdt: Use environment to pass C flags and files
4e0e0d049757 pylibfdt: Allow pkg-config to be supplied in the environment
6afd7d9688f5 Correct typo: s/pylibgfdt/pylibfdt/
756ffc4f52f6 Build pylibfdt as part of the normal build process
8cb3896358e9 Adjust libfdt.h to work with swig
b40aa8359aff Mention pylibfdt in the documentation
12cfb740cc76 Add tests for pylibfdt
50f250701631 Add an initial Python library for libfdt
cdbb2b6c7a3a checks: Warn on node name unit-addresses with '0x' or leading 0s
4c15d5da17cc checks: Add bus checks for simple-bus buses
33c3985226d3 checks: Add bus checks for PCI buses

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoscripts/dtc: Update to upstream version v1.4.4
Tom Rini [Sat, 23 Sep 2017 21:30:53 +0000 (17:30 -0400)]
scripts/dtc: Update to upstream version v1.4.4

This adds the following commits from upstream:

558cd81bdd43 dtc: Bump version to v1.4.4
c17a811c62eb fdtput: Remove star from value_len documentation
194d5caaefcb fdtget: Use @return to document the return value
d922ecdd017b tests: Make realloc_fdt() really allocate *fdt
921cc17fec29 libfdt: overlay: Check the value of the right variable
9ffdf60bf463 dtc: Simplify asm_emit_string() implementation
881012e44386 libfdt: Change names of sparse helper macros
bad5b28049e5 Fix assorted sparse warnings
672ac09ea04d Clean up gcc attributes
49300f2ade6a dtc: Don't abuse struct fdt_reserve_entry

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoscripts/dtc: Update to upstream version v1.4.3
Tom Rini [Sat, 23 Sep 2017 16:52:44 +0000 (12:52 -0400)]
scripts/dtc: Update to upstream version v1.4.3

Using the update-dtc-source.sh script from Linux v4.14-rc1 import the
portions of dtc that we require.  We bring in update-dtc-source.sh and
scripts/dtc/Makefile from Linux v4.14-rc1.  Rework DTC_FLAGS handling to
not require a test.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoMerge git://git.denx.de/u-boot-socfpga
Tom Rini [Sat, 23 Sep 2017 21:32:53 +0000 (17:32 -0400)]
Merge git://git.denx.de/u-boot-socfpga

7 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Sat, 23 Sep 2017 13:43:09 +0000 (09:43 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

7 years agoarm: socfpga: Configuration for EFI boot on DE0-nano-SoC
Frank Kunz [Tue, 8 Aug 2017 16:18:29 +0000 (18:18 +0200)]
arm: socfpga: Configuration for EFI boot on DE0-nano-SoC

For EFI boot GPT partition table support is needed as well
as the part command and also the SPL needs to fallback to
other boot methods after parse the SPL header.

Signed-off-by: Frank Kunz <mailinglists@kunz-im-inter.net>
7 years agoARM: socfpga: fix duplicate const specifier warning
Masahiro Yamada [Tue, 12 Sep 2017 08:23:39 +0000 (17:23 +0900)]
ARM: socfpga: fix duplicate const specifier warning

GCC 7.1 warns:
duplicate ‘const’ declaration specifier [-Wduplicate-decl-specifier]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: socfpga: remove unneeded NAND config options
Masahiro Yamada [Sat, 2 Sep 2017 01:53:11 +0000 (10:53 +0900)]
ARM: socfpga: remove unneeded NAND config options

CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the
NAND initialization process is driven by the driver itself.
CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoarmv8: ls1046ardb: disable PPA loading during SPL stage for SD boot
Yangbo Lu [Mon, 18 Sep 2017 06:58:49 +0000 (14:58 +0800)]
armv8: ls1046ardb: disable PPA loading during SPL stage for SD boot

PPA loading during SPL stage is not required for nornal
SD boot scenario.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043ardb: disable PPA loading during SPL stage for SD boot
Yangbo Lu [Mon, 18 Sep 2017 06:58:37 +0000 (14:58 +0800)]
armv8: ls1043ardb: disable PPA loading during SPL stage for SD boot

PPA loading during SPL stage is not required for nornal
SD boot scenario.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: ls1043a: disable IFC in SPL only when QSPI is used
Yangbo Lu [Fri, 15 Sep 2017 01:51:58 +0000 (09:51 +0800)]
armv8: ls1043a: disable IFC in SPL only when QSPI is used

Current u-boot disables IFC support for SD boot on all ls1043a
boards. Actually IFC only conflicts with QSPI on ls1043a hardware.
Only when QSPI is used, IFC should be disabled. Otherwise,
the u-boot with ls1043aqds_sdcard_ifc_defconfig would not work.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoboard/ls2080ardb: Update board env based on SoC
Priyanka Jain [Fri, 15 Sep 2017 04:49:48 +0000 (10:19 +0530)]
board/ls2080ardb: Update board env based on SoC

As per current implementation, default value of board env is
based on board filename i.e ls2080ardb.

With distro support changes, this env is used to decide upon
kernel dtb which is different for other SoCs (ls2088a, ls2081a)
combination supported with this board.

Add support to modify board env at runtime based on SoC type

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoboard/ls2080ardb: Add mcmemsize variable in default env
Priyanka Jain [Tue, 29 Aug 2017 09:50:37 +0000 (15:20 +0530)]
board/ls2080ardb: Add mcmemsize variable in default env

For most of ls2080ardb use-cases, mc private DRAM block is required
to be of 1.75GB.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[YS: this reservation needs to be reduced if memory is not enough]
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2C
Sriram Dash [Mon, 4 Sep 2017 10:15:02 +0000 (15:45 +0530)]
armv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2C

I2C code is put under CONFIG_SYS_I2C.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC
Sriram Dash [Mon, 4 Sep 2017 10:14:05 +0000 (15:44 +0530)]
armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC

IFC code is put under CONFIG_FSL_IFC

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agopci: layerscape: Fixup iommu-map for LS208xA
Bharat Bhushan [Thu, 31 Aug 2017 07:56:46 +0000 (13:26 +0530)]
pci: layerscape: Fixup iommu-map for LS208xA

Commit 0aaa1a9 added support for LS208xA devices but fixing
iommu-map property is missing. This patch adds support for
fixing iommu-map.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoboard/ls2081ardb: Update QSPI flash type from n25q512a to s25fs512s
Santan Kumar [Fri, 18 Aug 2017 09:50:32 +0000 (15:20 +0530)]
board/ls2081ardb: Update QSPI flash type from n25q512a to s25fs512s

As per updated board design, different QSPI flash
is connected on boards, hence change QSPI flash type
from Micron n25q512a device to spansion s25fs512s
device in dts and config.

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoboard/ls2080ardb: Remove CONFIG_DISPLAY_BOARDINFO_LATE
Santan Kumar [Fri, 18 Aug 2017 09:50:31 +0000 (15:20 +0530)]
board/ls2080ardb: Remove CONFIG_DISPLAY_BOARDINFO_LATE

CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay
the prints of boardinfo late in cycle during uboot boot.
This feature is not required in case of QSPI_BOOT.

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv8: fsl-layerscape: Put SATA code under SATA configs
Ashish Kumar [Fri, 18 Aug 2017 05:24:35 +0000 (10:54 +0530)]
armv8: fsl-layerscape: Put SATA code under SATA configs

It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
7 years agoarmv7: ls1021a: Fix marco CONFIG_LS102XA
York Sun [Thu, 14 Sep 2017 19:49:57 +0000 (12:49 -0700)]
armv7: ls1021a: Fix marco CONFIG_LS102XA

Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A
to CONFIG_LS102XA.

Signed-off-by: York Sun <york.sun@nxp.com>
7 years agoregulator: pbias: Add PBIAS regulator for proper voltage switching on MMC1
Jean-Jacques Hiblot [Thu, 21 Sep 2017 15:03:10 +0000 (17:03 +0200)]
regulator: pbias: Add PBIAS regulator for proper voltage switching on MMC1

In the TI SOCs a PBIAS cell exists to provide a bias voltage to the MMC1
IO cells. Without this bias voltage these I/O cells can not function
properly. The PBIAS cell is controlled by software.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: core: Add functions to get strings and the string count from a stringlist
Jean-Jacques Hiblot [Thu, 21 Sep 2017 15:03:09 +0000 (17:03 +0200)]
dm: core: Add functions to get strings and the string count from a stringlist

dev_read_string_count() is used to get the number of strings in a
stringlist.
dev_read_string_index() is used to get a string in the stringlist based on
its position in the list.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
7 years agommc: uniphier-sd: Add support for R8A7795 and R7A7796
Marek Vasut [Fri, 21 Jul 2017 21:24:36 +0000 (23:24 +0200)]
mmc: uniphier-sd: Add support for R8A7795 and R7A7796

Add OF match entries and quirks for Renesas RCar Gen3 controllers
into the driver. The IP this driver handles is in fact Matsushita
one and in used both in Socionext and Renesas chips.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
7 years agommc: uniphier-sd: Add support for quirks
Marek Vasut [Fri, 21 Jul 2017 21:24:35 +0000 (23:24 +0200)]
mmc: uniphier-sd: Add support for quirks

Check if the OF match has any associated data and if so, use those
data as the controller quirks, otherwise fallback to the old method
of reading the controller version register to figure out the quirks.
This allows us to supply controller quirks on controllers which ie.
do not have version register.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
7 years agommc: uniphier-sd: Add support for 64bit FIFO
Marek Vasut [Fri, 21 Jul 2017 21:24:34 +0000 (23:24 +0200)]
mmc: uniphier-sd: Add support for 64bit FIFO

The Renesas RCar Gen3 contains the same controller, originally
Matsushita. This patch adds support for handling of the 64bit
FIFO on this controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
7 years agommc: uniphier-sd: Add support for 64bit controller
Marek Vasut [Fri, 21 Jul 2017 21:24:33 +0000 (23:24 +0200)]
mmc: uniphier-sd: Add support for 64bit controller

The Renesas RCar Gen3 contains the same controller, originally
Matsushita, yet the register addresses are shifted by 1 to the
left. The whole controller is also 64bit, including the data
FIFOs and RSP registers. This patch adds support for handling
the register IO by shifting the register offset by 1 in the IO
accessor functions.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
7 years agommc: uniphier-sd: Factor out register IO
Marek Vasut [Fri, 21 Jul 2017 21:24:32 +0000 (23:24 +0200)]
mmc: uniphier-sd: Factor out register IO

This patch prepares the driver to support controller(s) with registers
at locations shifted by constant. Pull out the readl()/writel() from
the driver into separate functions, where the adjustment of the register
offset can be easily contained.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
7 years agoTravis-CI: Checkout only v1.4.3 of dtc
Tom Rini [Sun, 17 Sep 2017 13:42:25 +0000 (09:42 -0400)]
Travis-CI: Checkout only v1.4.3 of dtc

Our minimum DTC version is 1.4.3, so check that out.

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agonet/tftp: fix build if CMD_BOOTEFI is not set
Jörg Krause [Fri, 15 Sep 2017 20:16:48 +0000 (22:16 +0200)]
net/tftp: fix build if CMD_BOOTEFI is not set

Fixes:
net/tftp.c:811: undefined reference to `efi_set_bootdev'

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7 years agoMakefile: Update minimum dtc version to 1.4.3
Tom Rini [Fri, 15 Sep 2017 17:15:25 +0000 (13:15 -0400)]
Makefile: Update minimum dtc version to 1.4.3

With support for overlays and calling the -@ flag to dtc we need to have
at least 1.4.3 available now.

Cc: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agospl: Fix compiling warning on gunzip argument
York Sun [Fri, 15 Sep 2017 15:21:13 +0000 (08:21 -0700)]
spl: Fix compiling warning on gunzip argument

common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’
from incompatible pointer type [-Wincompatible-pointer-types]
       src, &length))

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
CC: Jean-Jacques Hiblot <jjhiblot@ti.com>
7 years agoarm: am33xx: Make pin multiplexing functions optional
Felix Brack [Thu, 14 Sep 2017 12:37:08 +0000 (14:37 +0200)]
arm: am33xx: Make pin multiplexing functions optional

This patch provides default implementations of the two functions
set_uart_mux_conf and set_mux_conf_regs. Hence boards not using
them do not need to provide their distinct empty definitions.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoboard: Add stm32h7 SoC, discovery and evaluation boards support
Patrice Chotard [Wed, 13 Sep 2017 16:00:12 +0000 (18:00 +0200)]
board: Add stm32h7 SoC, discovery and evaluation boards support

This patch adds support for stm32h7 soc family, stm32h743
discovery and evaluation boards.

For more information about STM32H7 series, please visit:
http://www.st.com/en/microcontrollers/stm32h7-series.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: DTS: stm32: adapt stm32h7 dts files for U-boot
Patrice Chotard [Wed, 13 Sep 2017 16:00:11 +0000 (18:00 +0200)]
ARM: DTS: stm32: adapt stm32h7 dts files for U-boot

This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :

_ Add RCC clock driver node and update all clocks phandle
  accordingly.

  By default, on kernel side, all clocks was temporarly
  configured as a phandle to timer_clk waiting for a RCC
  clock driver to be available.
  On U-boot side, we now have a dedicated RCC clock driver, we
  can configured all clocks as phandle to this driver.

  All this binding update will be available soon in a kernel tag,
  as all the bindings have been acked by Rob Herring [1].

  [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

_ Align STM32H7 serial compatible string with the one which will be
  available in next kernel tag. The bindings has been acked by
  Rob Herring [2].
  This compatible string will be usefull to add stm32h7 specific
  feature for this serial driver.

  [2] https://lkml.org/lkml/2017/7/17/739

_ Add gpio compatible and aliases for stm32h743

_ Add FMC sdram node with associated new bindings value to
  manage second bank (ie bank 1).

_ Add missing HSI and CSI oscillators nodes needed
  by STM32H7 RCC clock driver.

  Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)

  These clocks can be used as clocksource in some configuration.
  By default, HSE is selected as clock source.

_ Set HSE to 25Mhz for stm32h743i-disco and eval board

  By default, the external oscillator frequency is defined at
  25 Mhz in SoC stm32h743.dtsi file.
  It has been set at 125 Mhz in kernel DT temporarly waiting for
  RCC clock driver becomes available.

  As in U-boot we got a RCC clock driver, the real value of HSE
  clock can be used.

_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
  pwrcfg and gpio nodes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: DTS: stm32: add stm32h743i-eval files
Patrice Chotard [Wed, 13 Sep 2017 16:00:10 +0000 (18:00 +0200)]
ARM: DTS: stm32: add stm32h743i-eval files

This file is imported from linux kernel v4.13

Add device tree support for STM32H743 evaluation board.
This board offers :
  _ STM32H743XIH6 microcontroller with 2 Mbytes of
    Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
  _ 5.7” 640x480 TFT color LCD with touch screen
  _ Ethernet compliant with IEEE-802.3-2002
  _ USB OTG HS and FS
  _ I2 C compatible serial interface
  _ RTC with rechargeable backup battery
  _ SAI Audio DAC
  _ ST-MEMS digital microphones
  _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
  _ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash
  _ 1-Gbit Twin Quad-SPI NOR Flash
  _ Potentiometer
  _ 4 colored user LEDs
  _ Reset, wakeup, tamper or key buttons
  _ Joystick with 4-direction control and selector
  _ Board connectors :
     Power jack
     3 USB with Micro-AB
     RS-232 communications
     Ethernet RJ45
     FD-CAN compliant connection
     Stereo headset jack including analog microphone input
     2 audio jacks for external speakers
     microSD™ card
     JTAG/SWD and ETM trace
   _ Expansion connectors:
     Extension connectors and memory connectors for daughterboard
     or wire-wrap board
   _ Flexible power-supply options: ST-LINK USB VBUS or external
     sources
   _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
     capability: mass storage, virtual COM port and debug port

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: DTS: stm32: add stm32h743i-disco files
Patrice Chotard [Wed, 13 Sep 2017 16:00:09 +0000 (18:00 +0200)]
ARM: DTS: stm32: add stm32h743i-disco files

All these files are imported from linux kernel v4.13

Add device tree support for STM32H743 SoC and discovery
board. This board offers :
  _ STM32H743XIH6 microcontroller with 2 Mbytes of
    Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
  _ 5.7” 640x480 TFT color LCD with touch screen
  _ Ethernet compliant with IEEE-802.3-2002
  _ USB OTG HS
  _ I2 C compatible serial interface
  _ ST-MEMS digital microphones
  _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
  _ 8Mx32bit SDRAM
  _ 1-Gbit Twin Quad-SPI NOR Flash
  _ Reset, wakeup, or key buttons
  _ Joystick with 4-direction control and selector
  _ Board connectors :
1 USB with Micro-AB
Ethernet RJ45
Stereo headset jack including analog microphone input
microSD™ card
RCA connector
JTAG/SWD and ETM trace
   _ Expansion connectors:
Arduino Uno compatible Connectors
2 x PIO connectors (PMOD and PMOD+)
   _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
     capability: mass storage, virtual COM port and debug port

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: misc: add stm32 rcc driver
Christophe Kerello [Wed, 13 Sep 2017 16:00:08 +0000 (18:00 +0200)]
dm: misc: add stm32 rcc driver

This patch adds the support of reset and clock control
block (rcc) found on STM32 SoCs.
This driver is similar to a MFD linux driver.

This driver supports currently STM32H7 only.
STM32F4 and STM32F7 will be migrated to this rcc MFD driver
in the future to uniformize all STM32 SoCs already upstreamed.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: reset: add stm32 reset driver
Patrice Chotard [Wed, 13 Sep 2017 16:00:07 +0000 (18:00 +0200)]
dm: reset: add stm32 reset driver

This driver is adapted from linux drivers/reset/reset-stm32.c
It's compatible with STM32 F4/F7/H7 SoCs.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

To add support for each SoC family, a SoC's specific
include/dt-binfings/mfd/stm32xx-rcc.h file must be added.

This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
Other SoCs support will be added in the future.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: clk: add clk driver support for stm32h7 SoCs
Patrice Chotard [Wed, 13 Sep 2017 16:00:06 +0000 (18:00 +0200)]
dm: clk: add clk driver support for stm32h7 SoCs

This driver implements basic clock setup, only clock gating
is implemented.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].

[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoserial: stm32x7: add STM32H7 support
Patrice Chotard [Wed, 13 Sep 2017 16:00:05 +0000 (18:00 +0200)]
serial: stm32x7: add STM32H7 support

STM32F7 and STM32H7 shares the same UART block, add
STM32H7 compatible string.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agopinctrl: stm32: add stm32h743-pinctrl compatible
Patrice Chotard [Wed, 13 Sep 2017 16:00:04 +0000 (18:00 +0200)]
pinctrl: stm32: add stm32h743-pinctrl compatible

STM32H7 SoCs uses the same pinctrl block as found into
STM32F7 SoCs

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
7 years agospl: stash bootstage info before jump to next stage
Kever Yang [Wed, 13 Sep 2017 10:24:24 +0000 (18:24 +0800)]
spl: stash bootstage info before jump to next stage

Since we may jump to next stage like ATF/OP-TEE instead of U-Boot,
we need to stash the bootstage info before it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoboard: STiH410-B2260: add fastboot support
Patrice Chotard [Tue, 5 Sep 2017 09:04:27 +0000 (11:04 +0200)]
board: STiH410-B2260: add fastboot support

Add usb_gadget_handle_interrupts(), board_usb_init(),
board_usb_cleanup() and g_dnl_board_usb_cable_connected()
callbacks needed for FASTBOOT support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: dts: STiH410: update ehci and ohci compatible
Patrice Chotard [Tue, 5 Sep 2017 09:04:26 +0000 (11:04 +0200)]
ARM: dts: STiH410: update ehci and ohci compatible

Update ehci and ohci node's compatible string in order to
use ehci-generic and ohci-generic drivers.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: dts: STiH410: set DWC3 dual role mode to peripheral
Patrice Chotard [Tue, 5 Sep 2017 09:04:25 +0000 (11:04 +0200)]
ARM: dts: STiH410: set DWC3 dual role mode to peripheral

On STi 96boards, configure by default the micro USB connector
(managed by DWC3 hardware block) in peripheral mode.
This will allow to use fastboot feature.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: dwc3: Add dwc3 glue driver support for STi
Patrice Chotard [Tue, 5 Sep 2017 09:04:24 +0000 (11:04 +0200)]
usb: dwc3: Add dwc3 glue driver support for STi

This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.

Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSTiH410-B2260: enable USB, fastboot, reset, PHY related flags
Patrice Chotard [Tue, 5 Sep 2017 09:04:23 +0000 (11:04 +0200)]
STiH410-B2260: enable USB, fastboot, reset, PHY related flags

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoSTiH410-B2260: enable USB Host Networking
Patrice Chotard [Tue, 5 Sep 2017 09:04:22 +0000 (11:04 +0200)]
STiH410-B2260: enable USB Host Networking

Enable USB Host Networking support by enabling Ethernet/USB
adaptors support and by enabling some BOOTP flags

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agousb: phy: Add STi USB2 PHY
Patrice Chotard [Tue, 5 Sep 2017 09:04:21 +0000 (11:04 +0200)]
usb: phy: Add STi USB2 PHY

This is the generic phy driver for the picoPHY ports
used by USB2/1.1 controllers. It is found on STiH407 SoC
family from STMicroelectronics.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>