Luca Ceresoli [Mon, 12 Mar 2018 16:18:38 +0000 (17:18 +0100)]
arm64: zynqmp: Enable booting to ATF
U-Boot is now able to boot to ARM Trusted Firmware (ATF). The boot
flow is SPL(EL3) loads ATF and full u-boot and jump to ATF(EL3) which
pass control to full u-boot(EL2). This has been tested on zcu106, so
enable it in this defconfig.
To generate an image that triggers this booting flow, you need to pass
'-O arm-trusted-firmware' to mkimage.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: phy: xilinx_phy: Read phytype using property xlnx,phy-type
This patch reads phytype from property "xlnx,phy-type" instead
od simply looking for "phy-type". This is to be inline with
Linux and also fixes the issue of detecting it wrongly in
u-boot.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vipul Kumar [Sat, 10 Mar 2018 12:22:23 +0000 (17:52 +0530)]
nand: arasan_nfc: Fixed NAND write issue
In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFFFF and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0xFFFF0000 and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0xFFFF.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is delay needed after PCFG_PROGB change if
AES key source is efuse. This fixes the issue of
encrypted bitstream loading with AES efuse as key
source.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM: dts: zynq: Add generic compatible string for I2C EEPROM
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 27 Mar 2018 12:31:42 +0000 (14:31 +0200)]
arm: zynq: Remove 0x prefixes from cc108
The patch fixing issues reported by DTC:
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x400000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x800000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xc00000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xd00000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xf00000 unit name should not have
leading "0x"
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mario Six [Wed, 28 Mar 2018 12:39:18 +0000 (14:39 +0200)]
cmd: Add command for calculating binary operations
This patch adds a command that enables the calculation of bit operations
(AND, OR, XOR) on binary data from the command line. Memory locations as
well as the contents of environment variables are eligible as sources
and destination of the binary data used in the operations.
The possible applications are manifold: Setting specific bits in
registers using the regular read-OR-write pattern, masking out bits in
bit values, implementation of simple OTP encryption using the XOR
operation, etc.
Michal Simek [Mon, 26 Mar 2018 14:31:27 +0000 (16:31 +0200)]
image: fit: Show information about OS type in firwmare case too
SPL ATF implementation requires FIT image with partitions where the one
is Firmware/ATF and another one Firmware/U-Boot. OS field is used for
recording that difference that's why make sense to show values there for
Firmware types.
Michal Simek [Mon, 26 Mar 2018 14:31:26 +0000 (16:31 +0200)]
image: fit: Show firmware configuration property if present
SPL ATF support requires to have firmware property which should be also
listed by mkimage -l when images is created.
The patch is also using this macro in spl_fit to match keyword.
When image is created:
Default Configuration: 'config'
Configuration 0 (config)
Description: ATF with full u-boot
Kernel: unavailable
Firmware: atf
FDT: dtb
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Vignesh R [Mon, 26 Mar 2018 07:57:02 +0000 (13:27 +0530)]
ARM: dts: Add new "generic" am4372 device tree file.
With U-boot runtime board detect for DTB selection a "default" dtb needs
to be created. This will be used temporarily until the "proper" dtb is
selected.
Also, add -u-boot.dtsi for AM437x SK and IDK to enable I2C for
board detection via DM_I2C.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Vignesh R [Mon, 26 Mar 2018 07:57:01 +0000 (13:27 +0530)]
board: ti: am43xx: Define embedded_dtb_select for runtime DTB selection in U-boot
AM437x QSPI boot is a single stage boot and hence needs runtime DTB
selection to support AM437x-SK and AM437x-IDK with DM enabled. This is
required to move am43xx_evm_qspiboot_defconfig to use DM/DT.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Sjoerd Simons [Thu, 22 Mar 2018 21:53:50 +0000 (22:53 +0100)]
env: Properly check for BLK support
Use CONFIG_IS_ENABLED to see if CONFIG_BLK is enabled. Otherwise
SPL compilation breaks on boards which do have CONFIG_BLK enabled but
not DM_MMC for the SPL as follows:
env/mmc.c: In function ‘init_mmc_for_env’:
env/mmc.c:164:6: warning: implicit declaration of function ‘blk_get_from_parent’; did you mean ‘efi_get_ram_base’? [-Wimplicit-function-declaration]
if (blk_get_from_parent(mmc->dev, &dev))
^~~~~~~~~~~~~~~~~~~
efi_get_ram_base
env/mmc.c:164:29: error: ‘struct mmc’ has no member named ‘dev’
if (blk_get_from_parent(mmc->dev, &dev))
^~
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
Chris Packham [Wed, 21 Mar 2018 02:40:37 +0000 (15:40 +1300)]
rtc: rx8025: remove redundant code in rtc_reset
As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the rx8025 implementation of
rtc_reset() does not need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Wed, 21 Mar 2018 02:40:36 +0000 (15:40 +1300)]
rtc: rs5c372: remove redundant code in rtc_reset
As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the rs5c372 implementation of
rtc_reset() does not need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Wed, 21 Mar 2018 02:40:35 +0000 (15:40 +1300)]
rtc: mx27rtc: remove redundant code in rtc_reset
As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the mx27rtc implementation of
rtc_reset() can be an empty stub function.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Wed, 21 Mar 2018 02:40:34 +0000 (15:40 +1300)]
rtc: ds1374: remove redundant code in rtc_reset
As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the ds1374 implementation of
rtc_reset() doesn't need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Wed, 21 Mar 2018 02:40:33 +0000 (15:40 +1300)]
rtc: ds1307: remove redundant code in rtc_reset
As of commit 1a1fa2406689 ("rtc: Set valid date after reset") the
command "date reset" will set the date/time to 2000-01-01 0:00:00 after
calling rtc_reset(). This means that the ds1307 implementation of
rtc_reset() doesn't need to call rtc_set().
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
The section header address is a VMA whereas the address found in
the program header is a physical one. With this change it is
possible to load and start a vx7 intel generic based image.
$ readelf -l /tmp/vx7
Elf file type is EXEC (Executable file)
Entry point 0x408000
There are 2 program headers, starting at offset 52
$ readelf -S /tmp/vx7
There are 13 section headers, starting at offset 0x588af8:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text.locore PROGBITS 00408000 001000 00011e 00 AX 0 0 16
[ 2] .data.locore PROGBITS 00409000 002000 003000 00 WA 0 0 4096
[ 3] .text PROGBITS e040c000 005000 4802a0 00 WAX 0 0 32
[ 4] .eh_frame PROGBITS e088c2a0 4852a0 0a1ed0 00 A 0 0 4
[ 5] .wrs_build_vars PROGBITS e092e170 527170 000190 00 Ax 0 0 1
[ 6] .data PROGBITS e092f000 528000 060a70 00 WA 0 0 4096
[ 7] .tls_data PROGBITS e098fa70 588a70 000004 00 A 0 0 4
[ 8] .tls_vars PROGBITS e098fa78 588a78 00000c 00 WA 0 0 4
[ 9] .bss NOBITS e098faa0 588a84 0491d0 00 WA 0 0 32
[10] .shstrtab STRTAB 00000000 588a84 000074 00 0 0 1
[11] .symtab SYMTAB 00000000 588d00 056ee0 10 12 9758 4
[12] .strtab STRTAB 00000000 5dfbe0 05f48a 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings)
I (info), L (link order), G (group), T (TLS), E (exclude), x (unknown)
O (extra OS processing required) o (OS specific), p (processor specific)
For completeness here are the same information for an old vx5 based image. After
this change it is possible to boot vx5 and vx7 (intel generic) images.
$ readelf -l /tmp/vx5
Elf file type is EXEC (Executable file)
Entry point 0x308000
There are 1 program headers, starting at offset 52
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000060 0x00308000 0x00308000 0x3513a0 0x757860 RWE 0x20
Section to Segment mapping:
Segment Sections...
00 .text .data .bss
[christian@chgm-pc ~]$ readelf -S /tmp/vx5
There are 12 section headers, starting at offset 0x356580:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 00308000 000060 319b10 00 WAX 0 0 32
[ 2] .data PROGBITS 00621b20 319b80 037880 00 WA 0 0 32
[ 3] .bss NOBITS 006593a0 351400 4064c0 00 WA 0 0 16
[ 4] .debug_aranges PROGBITS 00000000 351400 000060 00 0 0 1
[ 5] .debug_pubnames PROGBITS 00000000 351460 00018b 00 0 0 1
[ 6] .debug_info PROGBITS 00000000 3515eb 003429 00 0 0 1
[ 7] .debug_abbrev PROGBITS 00000000 354a14 000454 00 0 0 1
[ 8] .debug_line PROGBITS 00000000 354e68 0016a4 00 0 0 1
[ 9] .shstrtab STRTAB 00000000 35650c 000071 00 0 0 1
[10] .symtab SYMTAB 00000000 356760 0440e0 10 11 8574 4
[11] .strtab STRTAB 00000000 39a840 03e66c 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings)
I (info), L (link order), G (group), T (TLS), E (exclude), x (unknown)
O (extra OS processing required) o (OS specific), p (processor specific)
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Patrick Delaunay [Tue, 20 Mar 2018 10:41:26 +0000 (11:41 +0100)]
stm32mp1: change STGEN clock source to HSE
No more use static frequency HSI = 64MHz for STGEN clock
but HSE (with higher accurency) by default.
Need to remove CONFIG_SYS_HZ_CLOCK as arch timer frequency
is provided at boot by BootRom and cp15 cntfrq and modified
during clock tree initialization if needed.
When HSI is no more used by any device, this internal
oscillator can be switched off to reduce consumption.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 20 Mar 2018 10:41:25 +0000 (11:41 +0100)]
clock: stm32mp1: add stgen clock source change support
The STGEN is the clock source for the Cortex A7 arch timer.
So after modification of its frequency, CP15 cntfreq is updated
and a new timer init is performed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 20 Mar 2018 10:41:23 +0000 (11:41 +0100)]
arm: timer: get frequency for arch timer armv7 in cp15 cntfrq
Manage dynamic value for armv7 arch clock timer,
when CONFIG_SYS_HZ_CLOCK is not defined.
Get frequency from CP15 cntfrq information, initialized for example
by first boot stage, clock driver or by BootRom.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Rasmus Villemoes [Tue, 20 Mar 2018 10:38:45 +0000 (11:38 +0100)]
Allow providing default environment from file
Modifying the default environment via CONFIG_EXTRA_ENV_SETTINGS is
somewhat inflexible, partly because the cpp language does not allow
appending to an existing macro. This prevents reuse of "environment
fragments" for different boards, which in turn makes maintaining that
environment consistently tedious and error-prone.
This implements a Kconfig option for allowing one to define the entire
default environment in an external file, which can then, for example, be
generated programmatically as part of a Yocto recipe, or simply be kept
in version control separately from the U-boot repository.
on eMMC:
The 2 boot partitions are used for SPL (2 copy)
boot1: SPL
boot2: SPL#2
The user partition use gpt partitioning
1: U-Boot
2: bootable partition
This patch select the correct SPL partition
(3 for SDCARD on mmc0 and 1 for eMMC on mmc1)
according the BootRom information saved in TAMP register
and based on configuration flasg:
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
=> for BOOT_DEVICE_MMC1 or mmc 0 in U-Boot
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 (new)
=> for BOOT_DEVICE_MMC2 or mmc 1 in U-Boot
And the correct boot_targets is selected according the environment
variables boot_device and boot_instance, with preboot command,
to search the bootable partition with kernel on this device
(generic distro support).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 20 Mar 2018 09:54:52 +0000 (10:54 +0100)]
stm32mp1: add eMMC support for ED1
Add command GPT support
Add EMMC boot support
Add the 2 other SDMMC instances for ED1:
- SDMMC2 = mmc 1, eMMC on the ED1 board
- SDMMC3 = extension connector, deactivated by default
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 20 Mar 2018 09:54:51 +0000 (10:54 +0100)]
spl: spl_mmc: provide one weak function spl_boot_partition
The spl_boot_partition function has been added in order to have
the possibility to boot on a same binary from different mmc devices
with different partitions.
By default keep the current behavior, SPL use the partition defined
by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
Klaus Goger [Mon, 19 Mar 2018 19:32:05 +0000 (20:32 +0100)]
rtc: rewrite isl1208 to support DM
Adds devicemodel support to the ISL1208 driver.
This patch drops the non-dm API as no board was using it anyway.
Also add it to Kconfig.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Hauke Mehrtens [Sun, 18 Mar 2018 15:03:47 +0000 (16:03 +0100)]
tools/mxsimage: Support building with LibreSSL
The mxsimage utility fails to compile against LibreSSL version < 2.7.0
because LibreSSL says it is OpenSSL 2.0, but it does not support the
complete OpenSSL 1.1 interface.
LibreSSL defines OPENSSL_VERSION_NUMBER with 0x20000000L and therefor
claims to have an API compatible with OpenSSL 2.0, but it implements
EVP_MD_CTX_new(), EVP_MD_CTX_free() and EVP_CIPHER_CTX_reset() only
starting with version 2.7.0, which is not yet released. OpenSSL
implements this function since version 1.1.0.
This commit will activate the compatibility code meant for
OpenSSL < 1.1.0 also for LibreSSL version < 2.7.0.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Jonathan Gray <jsg@jsg.id.au>
Russ Dill [Tue, 20 Mar 2018 06:53:00 +0000 (12:23 +0530)]
ARM: am33xx: Inhibit re-initialization of DDR during RTC-only
This inhibits the re-inititialization of DDR during an RTC-only resume. If
this is not done, an L3 NOC error is produced as the DDR gets accessed
before the re-init has time to complete. Tested on AM437x GP EVM.
Dave Gerlach [Sat, 17 Mar 2018 07:54:30 +0000 (13:24 +0530)]
am43xx: Do not allow EMIF to control DDR_RESET in rtconly config
Prevent EMIF control of DDR_RESET line on DDR3 am43xx platforms for
am43xx_evm_rtconly_config. Without this DDR is unstable and can become
corrupted after multiple iterations of RTC+DDR mode.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[j-keerthy@ti.com Ported to latest master branch] Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Tero Kristo [Sat, 17 Mar 2018 08:02:52 +0000 (13:32 +0530)]
ARM: AM43xx: Add support for RTC only + DDR in self-refresh mode
Kernel stores information to the RTC_SCRATCH0 and RTC_SCRATCH1 registers
for wakeup from RTC-only mode with DDR in self-refresh. Parse these
registers during SPL boot and jump to the kernel resume vector if the
device is waking up from RTC-only modewith DDR in Self-refresh.
The RTC scratch register layout used is:
SCRATCH0 : bits00-31 : kernel resume address
SCRATCH1 : bits00-15 : RTC magic value used to detect valid config
SCRATCH1 : bits16-31 : board type information populated by bootloader
During the normal boot path the SCRATCH1 : bits16-31 are updated with
the eeprom read board type data. In the rtc_only boot path the rtc
scratchpad register is read and the board type is determined and
correspondingly ddr dpll parameters are set. This is done so as to avoid
costly i2c read to eeprom.
RTC-only +DRR in self-refresh mode support is currently only enabled for
am43xx_evm_rtconly_config.
This is not to be used with epos evm builds.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[j-keerthy@ti.com Rebased to latest u-boot master branch] Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Jason Kridner [Wed, 7 Mar 2018 10:40:43 +0000 (05:40 -0500)]
Handle NETCONSOLE and SPL enabled
NETCONSOLE isn't compiled in with SPL, so the include file needs to recognize that.
Signed-off-by: Jason Kridner <jdk@ti.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Jason Kridner [Wed, 7 Mar 2018 10:40:41 +0000 (05:40 -0500)]
Add support for BeagleBoard.org PocketBeagle
Texas Instruments AM3358 based low-cost board using Octavo Systems OSD3358 SIP
with built-in TPS65217 PMIC and 512MB DDR3. Board features small 35mm x
55mm size, high-speed USB OTG, microSD and 72 0.1" expansion header
pins with 2xSPI, 2xI2C, 2xUART, USB, 8xADC, up-to-44 GPIO, PRU pins and much more.
https://beagleboard.org/pocket
This was tested using the am335x_evm_usbspl_defconfig.
Note that MII pins are enabled despite not having Ethernet on this
board. This avoids an issue where otherwise many timeout errors would be
generated. See https://e2e.ti.com/support/arm/sitara_arm/f/791/t/298976
for some related discussion.
Signed-off-by: Jason Kridner <jdk@ti.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
projects / u-boot / log