Max Krummenacher [Mon, 30 May 2016 14:28:28 +0000 (16:28 +0200)]
nand: fix nand torture to use changed mtd api
The mtd subsystem deprecated and renamed the direct use of the mtd_info
struct's functionpointers. Instead the corresponding mtd_xxx function
should be used.
Scott Wood [Mon, 30 May 2016 18:57:58 +0000 (13:57 -0500)]
mtd: nand: Sync with Linux v4.6
Updates the NAND code to match Linux v4.6. The previous sync was from
Linux v4.1 in commit d3963721d93fafa.
Note that none of the individual NAND drivers tracked Linux closely
enough to be synced themselves, other than manually applying a few
cross-tree changes.
Signed-off-by: Scott Wood <oss@buserror.net> Tested-by: Heiko Schocher <hs@denx.de>
Scott Wood [Mon, 30 May 2016 18:57:57 +0000 (13:57 -0500)]
mtd: nand: Add page argument to write_page() etc.
This change is part of the Linux 4.6 sync. It is being done before the
main sync patch in order to make it easier to address the issue across
all NAND drivers (many/most of which do not closely track their Linux
counterparts) separately from other merge issues.
Scott Wood [Mon, 30 May 2016 18:57:56 +0000 (13:57 -0500)]
mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data
These functions are part of the Linux 4.6 sync. They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.
Scott Wood [Mon, 30 May 2016 18:57:55 +0000 (13:57 -0500)]
nand: Embed mtd_info in struct nand_chip
nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.
This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip. It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].
Scott Wood [Mon, 30 May 2016 18:57:53 +0000 (13:57 -0500)]
mtd: nand: Remove docg4 driver and palmtreo680 flashing tool
Commit ad4f54ea86b ("arm: Remove palmtreo680 board") removed the only
user of the docg4 driver and the palmtreo680 image flashing tool. This
patch removes them.
Signed-off-by: Scott Wood <oss@buserror.net> Cc: Mike Dunn <mikedunn@newsguy.com> Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Mon, 30 May 2016 18:57:52 +0000 (13:57 -0500)]
mtd: nand: Remove jz4740 driver
This driver is not used by anyone, remove it.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Scott Wood <oss@buserror.net> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Scott Wood <oss@buserror.net>
Correct the nand ecc initialization code
This fixes the issue of incorrect nand ecc
init if no device is found in ecc_matrix then
it endsup ecc init with junk initialization
instead of the most suited one.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Wed, 25 May 2016 08:15:00 +0000 (16:15 +0800)]
driver/ddr/fsl: Check condition for erratum A-009803
Add condition of checking the enabled of address parity
for erratum A-009803, if parity is not enabled, the
workaround of erratum A-009803 should not be applied.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
pcie/layerscape: fix bug in bus number computation when setting msi-map
When multiple PCI cards are present in an ls2080a board, the second
card does not get its msi-map set up properly due to a bug in
computing the bus number.
The bus number returned by PCI_BDF() is not the actual PCI bus
number, but instead represents a global u-boot PCI bus number. A
given bus number is relative to hose->first_busno, so that has to be
subtracted from the PCI device id.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Acked-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Thu, 19 May 2016 04:11:19 +0000 (21:11 -0700)]
drivers/ddr/fsl: Fix timing_cfg_2 register
Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.
Yangbo Lu [Thu, 12 May 2016 11:12:58 +0000 (19:12 +0800)]
mmc: fsl_esdhc: fix check_and_invalidate_dcache_range function
In function check_and_invalidate_dcache_range(), there are incorrect
start address and end address of the dcache range calculated for
Layerscape platforms. This patch is to fix this issue.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Wed, 4 May 2016 02:20:21 +0000 (10:20 +0800)]
drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Stephen Warren [Fri, 3 Jun 2016 19:05:11 +0000 (13:05 -0600)]
arm: lib: fix push/pop-section directives
With the existing code, function symbols are defined in .text, and the
body is defined in .text.xxx. This causes (at least some version of) the
linker not to emit the function body into the final binary, since it's
part of a different section to the symbols being referenced. This of
course causes a wide variety of failures.
This change moves the push/pop-section directives before the function
symbols, and after any relate ENDPROC macro invocations, so that symbols
and bodies are all in the "pushed" sections, and thus the function bodies
are emitted into the binary.
This solves (at least) the boot problems currently seen on Tegra systems
that use SPL (i.e. all ARMv7 Tegras).
Fixes: 13b0a91a6d48 ("arm: lib: Split asm symbols into different .text subsections") Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Lokesh Vutla [Thu, 26 May 2016 13:35:44 +0000 (19:05 +0530)]
ARM: k2g: Configure reset mux to device reset
BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.
Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.
Right now to give a default watchdog behaviour "Device reset" is
being selected.
Keerthy [Tue, 24 May 2016 06:15:06 +0000 (11:45 +0530)]
arm: am57xx: Fix omap_vcores assignment for am572x-idk
Currently omap_vcores is wrongly assigned a default value of
beagle_x15_volts. Hence populating a new structure for am572x-idk
and assigning it to omap_vcores in the vcores_init function.
Fixes: c020d355c45ed40fe12a ("board: ti: am57xx: Add support for am572x idk in SPL") Reported-by: Suman Anna <s-anna@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
Keerthy [Tue, 24 May 2016 06:15:05 +0000 (11:45 +0530)]
arm: omap: Introduce vcores_init function
The pmic registers for variants of am57xx boards are different
hence we need to assign them carefully based on the board type.
Add a function to assign omap_vcores after the board detection.
Anna, Suman [Mon, 23 May 2016 18:32:17 +0000 (13:32 -0500)]
ARM: DRA7: Add macros for voltage values for all OPPs
Define specific macros for the voltage values for all voltage
domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH.
No separate macros are defined for VD_MPU and VD_CORE at OPP_OD
and OPP_HIGH as these use the same values as OPP_NOM.
The current macros will be used as common macros that can be
redefined appropriately based on a selected OPP configuration
at build time.
Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Anna, Suman [Mon, 23 May 2016 18:32:16 +0000 (13:32 -0500)]
ARM: DRA7: Consolidate voltage macros across different SoCs
The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.
This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.
Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Anna, Suman [Mon, 23 May 2016 18:32:15 +0000 (13:32 -0500)]
ARM: DRA7: Define common macros for efuse register offsets
Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.
Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Anna, Suman [Mon, 23 May 2016 18:32:14 +0000 (13:32 -0500)]
ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values
The current OPP_NOM voltage values defined for the MPU and CORE
voltage domains are based on the initial DRA75x_74x_SR1.1_DM data
manual. As per this DM, the PMIC boot voltage can be set to either
1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE.
While the current values are correct, the latter set of values
are the values that are common across all DRA75x, DRA72x SoCs and
for all current Silicon revisions. So, update both the MPU and CORE
OPP_NOM voltages to 1.15V.
The macros are also slightly reorganized so that both the MPU and
CORE voltage domain values are defined together.
Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Roger Quadros [Mon, 23 May 2016 14:37:48 +0000 (17:37 +0300)]
ARM: AM57xx: AM43xx: Fix USB host
CONFIG_USB_XHCI_OMAP can be set for host mode without setting
CONFIG_USB_DWC3 which is meant for gadget mode only.
board_usb_init() was not being defined for CONFIG_USB_XHCI_OMAP
resulting in a data abort on usb start.
Define board_usb_init() for CONFIG_USB_XHCI_OMAP case. Move
gadget specific handling to within CONFIG_USB_DWC3.
Fixes: 6f1af1e358b7 ("board: ti: invoke clock API to enable and disable clocks") Signed-off-by: Roger Quadros <rogerq@ti.com>
Roger Quadros [Mon, 23 May 2016 14:37:47 +0000 (17:37 +0300)]
ARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAP
CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.
Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks" Signed-off-by: Roger Quadros <rogerq@ti.com>
Marek Vasut [Thu, 26 May 2016 16:01:47 +0000 (18:01 +0200)]
lib: Enable private libgcc by default
This patch decouples U-Boot binary from the toolchain on systems where
private libgcc is available. Instead of pulling in functions provided
by the libgcc from the toolchain, U-Boot will use it's own set of libgcc
functions. These functions are usually imported from Linux kernel, which
also uses it's own libgcc functions instead of the ones provided by the
toolchain.
This patch solves a rather common problem. The toolchain can usually
generate code for many variants of target architecture and often even
different endianness. The libgcc on the other hand is usually compiled
for one particular configuration and the functions provided by it may
or may not be suited for use in U-Boot. This can manifest in two ways,
either the U-Boot fails to compile altogether and linker will complain
or, in the much worse case, the resulting U-Boot will build, but will
misbehave in very subtle and hard to debug ways.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:46 +0000 (18:01 +0200)]
arm: lib: Split asm symbols into different .text subsections
Split each symbol in lib1funcs into different .text.foo section instead
of placing all of them into plain .text . This allows the linker to collect
and discard unused assembler symbols.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:45 +0000 (18:01 +0200)]
arm: lib: Import Thumb1 functions
Import functions into lib1funcs.S which are required for Thumb1
build. These functions come from gcc 5.3.1 release.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:44 +0000 (18:01 +0200)]
arm: lib: import muldi3.S from Linux
Import muldi3.S from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This file implements __aeabi_lmul and it's alias __muldi3, which
is needed when doing Thumb1 builds.
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:43 +0000 (18:01 +0200)]
arm: lib: Repair Warning: conditional infixes are deprecated in unified syntax
Fix the following warning when building for thumb2 target by tweaking the
instruction syntax:
Warning: conditional infixes are deprecated in unified syntax
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:42 +0000 (18:01 +0200)]
arm: lib: Import __do_div64 from Linux
Import __do_div64 from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326
on arm32. This function is for some toolchains, which generate _udivmoddi4()
for 64 bit division.
Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro.
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:41 +0000 (18:01 +0200)]
arm: lib: Fix uldivmod.S build on Thumb2
This assembler source won't build in Thumb2 mode, so fix it adding
the necessary Thumb2 conditional macros from unified.h .
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Sync the libgcc 32bit division and modulo operations with Linux 4.4.6 ,
commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . The functions in these
four files are present in lib1funcs.S in Linux, so replace these files
with lib1funcs.S from Linux.
Since we do not support stack unwinding, instead of importing the whole
asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro
in lib1funcs.S . Moreover, to make all of the functions available, define
CONFIG_AEABI , which is safe, because U-Boot is always compiled with ARM
EABI.
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:39 +0000 (18:01 +0200)]
arm: lib: Sync libgcc shift operations
Sync the libgcc shift operations with Linux kernel 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . Syncing these three
files is easy, as there is almost no change in them, except the
addition of Thumb support.
This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED
which is necessary for correct build of these files both in ARM and
Thumb mode, just like Linux does.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:38 +0000 (18:01 +0200)]
arm: lib: Drop underscore from private libgcc filenames
Drop the underscore from the filenames of files implementing libgcc
routines. There is no functional change. This change is done to make
sync with Linux kernel easier.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:37 +0000 (18:01 +0200)]
arm: include: Import unified.h from Linux kernel
Import unified.h from Linux kernel 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains
macros used in libgcc functions in Linux kernel on ARM and will be
needed for the libgcc sync.
Since unified.h defines the W(instr) macro, we must drop this from
the macro from memcpy.S , otherwise this triggers a warning about
symbol redefinition. In order to keep the changes to unified.h to
the minimum, tweak arch/arm/lib/Makefile such that it defines the
CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all
of the assembler files. This is mandatory.
Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and
only if Thumb2 build is enabled. This macro is checked by unified.h
and toggles between ARM and Thumb2 variant of the instructions in the
assembler source files.
Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the
new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between
more optimal and more dense codepaths which work on armv5 and newer
and less optimal codepaths which work on armv4 and possible armv3m.
Tegra2 needs the same special handling as it does in arch/arm/Makefile
to cater for the arm720t boot core.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 26 May 2016 16:01:36 +0000 (18:01 +0200)]
arm: config: Introduce CONFIG_SYS_ARM_ARCH
Introduce new helper Kconfig option, which is automatically set to
the version of ARM architecture for which the U-Boot is built. This
is useful when selecting tuning options in the libgcc imported from
Linux kernel.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Tue, 31 May 2016 21:12:47 +0000 (23:12 +0200)]
ARM: omap: Enable tiny printf on omap3_logic
Enable support for tiny printf on the omap3_logic board to trim down
the SPL size. This makes the SPL actually build again and fit into
the SRAM.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: lesne@alse-fr.com Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Tue, 31 May 2016 22:00:02 +0000 (00:00 +0200)]
mips: wdr4300: Move the CONFIG_USE_PRIVATE_LIBGCC to Kconfig
This fixes the last remaining libgcc warning, where the symbol was
defined twice.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Wed, 25 May 2016 00:13:16 +0000 (02:13 +0200)]
serial: 16550: Drop OMAP1510 support
The CONFIG_OMAP1510 is no longer defined, so remove this dead code.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Nishanth Menon <nm@ti.com>
Marek Vasut [Wed, 25 May 2016 00:13:03 +0000 (02:13 +0200)]
serial: 16550: Make serial_io/out_shift available to debug mode
The ns16550 driver needs serial_in_shift() and serial_out_shift()
when compiled in debug UART mode, so shift the DM_SERIAL check a
little to make these functions available.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 25 May 2016 00:12:32 +0000 (02:12 +0200)]
gpio: mxs: Remove netdev.h
The MXS certainly does not support any sort of networking in GPIO code,
remove the netdev.h header.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Sylvain Lesne [Wed, 1 Jun 2016 09:14:54 +0000 (11:14 +0200)]
arm: socfpga: improve raw MMC SPL boot
Before this patch, when booting from MMC (no filesystem), the SPL
loaded U-Boot from a fixed offset.
It will now load U-Boot from an offset of 256kB (which is 4 times the
padded SPL image) in the third partition.
This behaviour is similar to what the vendor SPL (based on
U-Boot 2013.01) does, and allows to directly 'dd' the
u-boot-with-spl.sfp file to the A2 partition.
Marek Vasut [Mon, 30 May 2016 15:10:53 +0000 (17:10 +0200)]
spl: Remove bogus GD_FLG_SPL_INIT check
Remove the check for GD_FLG_SPL_INIT in spl_relocate_stack_gd().
The check will always fail. This is because spl_relocate_stack_gd()
is called from ARM's crt0.S and it is called before board_init_r().
The board_init_r() calls spl_init(), which sets the GD_FLG_SPL_INIT
flag.
Note that reserving the malloc area in RAM is not a problem even
if the GD_FLG_SPL_INIT flag is not set.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Tue, 1 Dec 2015 17:09:52 +0000 (18:09 +0100)]
arm: socfpga: Add samtec VIN|ING board
Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensor
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
---
V2: Update the defconfig as per Tom's request
Stephen Warren [Thu, 12 May 2016 19:32:56 +0000 (13:32 -0600)]
ARM: tegra: add p2771-0000 board support
P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B
port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion
headers.
Currently, due to U-Boot's level of support for Tegra186, the only
features supported by U-Boot are the console UART and the on-board eMMC.
Additional features will be added over time.
U-Boot has so far been tested by replacing the kernel image on the device
with a U-Boot binary. It is anticipated that U-Boot will eventually
replace the CCPLEX bootloader binary, as on previous chips. This hasn't
yet been tested.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 12 May 2016 19:32:55 +0000 (13:32 -0600)]
ARM: tegra: add core Tegra186 support
This adds the bare minimum code to support Tegra186, with UART and eMMC
working.
The empty gpio.h is required because <asm/gpio.h> includes it. A future
cleanup round may be able to solve this for all Tegra generations at once.
mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but
instead to defer everything to mach-tegra/tegra186/Makefile. This allows
the SoC code to pick-and-choose which of the C files in the "common"
mach-tegra/ directory to compile in based on the SoC's needs. Most of the
code is not valid for Tegra186, and this approach removes the need for
mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach
may be applied to all other Tegra SoCs in a future cleanup round.
board186.c is introduced to replace board.c and board2.c. These files
currently contain a slew of SoC- and board-specific code that is not
valid for Tegra186. This approach avoids adding yet more ifdefs to those
files. A future cleanup round may refactor most of board*.c into board-/
SoC-specific functions files thus allowing the top-level functions like
board_init_early_f to be shared again.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 12 May 2016 18:11:23 +0000 (12:11 -0600)]
mmc: tegra: add basic Tegra186 support
Tegra186's MMC controller needs to be explicitly identified. Add another
compatible value for it.
Tegra186 will use an entirely different clock/reset control mechanism to
existing chips, and will use standard clock/reset APIs rather than the
existing Tegra-specific custom APIs. The driver support for that isn't
ready yet, so simply disable all clock/reset usage if compiling for
Tegra186. This must happen at compile time rather than run-time since the
custom APIs won't even be compiled in on Tegra186. In the long term, the
plan would be to convert the existing custom APIs to standard APIs and get
rid of the ifdefs completely.
The system's main eMMC will work without any clock/reset support, since
the firmware will have already initialized the controller in order to
load U-Boot. Hence the driver is useful even in this apparently crippled
state.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 25 May 2016 20:38:51 +0000 (14:38 -0600)]
gpio: add Tegra186 GPIO driver
Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.
The DT binding is already present in the Linux kernel (in linux-next via
the Tegra tree so far).
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> # v1 Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 12 May 2016 18:07:41 +0000 (12:07 -0600)]
ARM: tegra: convert CONFIG_TEGRA_GPIO to Kconfig
Future chips will contain different GPIO HW. This change will enable
future SoC support to select the appropriate GPIO driver for their HW,
in a future-looking fashion, using Kconfig.
TEGRA_GPIO is not simply selected by TEGRA_COMMON (even though all
current Tegra chips used this GPIO HW) to simplify the later addition
of support for Tegra SoCs that use different GPIO HW.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 12 May 2016 18:07:40 +0000 (12:07 -0600)]
ARM: tegra: fix naming in GPIO DT binding header
According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs,
not into /banks/. Fix <dt-bindings/gpio/tegra-gpio.h> to correctly reflect
this naming convention. While this seems like silly churn, it will become
slightly more important once we introduce the GPIO binding for upcoming
Tegra chips. This mirrors an identical commit in the Linux kernel.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Thu, 12 May 2016 18:07:39 +0000 (12:07 -0600)]
ARM: tegra: use DT bindings for GPIO naming
There are currently many places that define the list of all Tegra GPIOs;
the DT binding header and custom Tegra-specific header file gpio.h. Fix
the redundancy by replacing everything with the DT binding header file.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Andreas Fenkart [Tue, 31 May 2016 07:21:56 +0000 (09:21 +0200)]
tools/env: allow to pass NULL for environment options
If users of the library are happy with the default, e.g. config file
name. They can pass NULL as the opts pointer. This simplifies the
transition of existing library users.
FIXES a compile error. since common_args has been removed by
a previous patch
Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
Since commit 56adbb387273 ("image.h: Tighten up content using handy
CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux
because the commit changed the logic of macros it touched. Now,
IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all
the boards.
As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and
IS_ENABLED() as well) can only take a macro that is either defined
as 1 or undefined. This is met for boolean options defined in
Kconfig. On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and
CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in
arch/*/include/asm/config.h . This kind of clean-up is welcome,
but the options should be moved to Kconfig beforehand.
Moreover, CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) looks weird.
It should be either CONFIG_IS_ENABLED(CRC32_SUPPORT) or
IS_ENABLED(CONFIG_SPL_CRC32_SUPPORT). But, I see no define for
CONFIG_SPL_CRC32_SUPPORT anywhere. Likewise for the other three.
The logic of IMAGE_OF_BOARD_SETUP and IMAGE_OF_SYSTEM_SETUP were
also changed for SPL. This can be a problem for boards defining
CONFIG_SPL_OF_LIBFDT. I guess it should have been changed to
IS_ENABLED(CONFIG_OF_BOARD_SETUP).
In the first place, if we replace the references in C code,
the macros IMAGE_* will go away.
Paul Burton [Fri, 27 May 2016 13:28:06 +0000 (14:28 +0100)]
MIPS: Abstract cache op loops with a macro
The various cache maintenance routines perform a number of loops over
cache lines. Rather than duplicate the code for performing such loops,
abstract it out into a new cache_loop macro which performs an arbitrary
number of cache ops on a range of addresses. This reduces duplication in
the existing L1 cache maintenance code & will allow for not adding
further duplication when introducing L2 cache support.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 27 May 2016 13:28:05 +0000 (14:28 +0100)]
MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Paul Burton [Fri, 27 May 2016 13:28:04 +0000 (14:28 +0100)]
MIPS: Move cache sizes to Kconfig
Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Those wrappers for linker symbols were once used in the MIPS
specific board.c implementation. Since the migration to generic
board.c, those wrappers are dead code and can be removed.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Marek Vasut [Tue, 24 May 2016 21:29:09 +0000 (23:29 +0200)]
net: Add ag7xxx driver for Atheros MIPS
Add ethernet driver for the AR933x and AR934x Atheros MIPS machines.
The driver could be easily extended to other WiSoCs.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Wills Wang <wills.wang@live.com>
[fixed Kconfig dependency] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Provide a default linker script for SPL binaries. Start address
and size of text section and BSS section are configurable. All
sections are arranged in a way that only relevant sections are
kept in the code section for maximum size reduction. All other
sections are kept but moved outside the code section to help
with debugging.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
Paul Burton [Thu, 26 May 2016 13:49:36 +0000 (14:49 +0100)]
malta: Allow MIPS64 builds
Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
projects / u-boot / log