Nikolay Dimitrov [Fri, 12 Dec 2014 18:01:23 +0000 (20:01 +0200)]
Fix hash verification
Fix issue in parse_verify_sum() which swaps handling of env-var and *address.
Move hash_command() argc check earlier.
Cosmetic change on do_hash() variable declaration.
Improved help message for "hash" command.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Reviewed-by: Simon Glass <sjg@chromium.org>
Alexey Brodkin [Sat, 27 Dec 2014 22:35:57 +0000 (01:35 +0300)]
initcall: add explicit hint if initcall was relocated
Commit "initcall: Improve debugging support" makes sense and indeed
simplifies process of matching initcalls executed with static
disassembly.
Until you are debugging relocation functionality.
Existign output may make you think that at some point execution somehow
returned back to non-relocated area. And there're many reasons/problems
that may provoke this behavior.
Note "unexpected" jump from 0x8f... area to 0x81... area.
Without explanation this raises many questions: execution jumped in
relocated area right as expected and then for some reason returned back?
But I hope comment in brackets will save some time for those curious
developers who are careful enough to catch "unexpected jump to pre-reloc
area" or those unlucky ones who'll have to deal with relocation
debugging.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com>
Masahiro Yamada [Thu, 25 Dec 2014 02:09:44 +0000 (11:09 +0900)]
scripts: fix binutils-version.sh
The current binutils-version.sh expects the version string at the end
of the first line. It turned out to not work with Linaro toolchain:
It has "Linaro 2014.09" at the back.
To fix this issue, let's parse the word right after the close
parenthesis.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reported-by: York Sun <yorksun@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com>
Stephen Warren [Wed, 24 Dec 2014 03:01:44 +0000 (20:01 -0700)]
ARM: rpi: consolidate board rev error checking
Create a fake model table entry with default values, so we can error
check the board rev value once when querying it from the firmware, rather
than error-checking for invalid board rev values every time the model
table is used.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Stephen Warren [Sat, 6 Dec 2014 03:56:46 +0000 (20:56 -0700)]
ARM: rpi: only set usbethaddr on relevant systems
Model A and CM RPis don't have an on-board USB Ethernet device. Hence,
there's no point setting $usbethaddr based on the device fuses. Use the
model detection code to gate this. Note that the fuses are actually
programmed even on those devices though.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Linus Walleij [Mon, 15 Dec 2014 10:06:05 +0000 (11:06 +0100)]
arm: semihosting: get rid of forward declarations
By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions follow at the end.
Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 15 Dec 2014 10:05:56 +0000 (11:05 +0100)]
arm: semihosting: fix up compile bugs
There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.
The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and interface, and voila:
the code now works again.
Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09.
Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Suggested-by: Mark Hambleton <mark.hambleton@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 15 Dec 2014 10:05:43 +0000 (11:05 +0100)]
arm: semihosting: staticize internal functions
The semihosting code exposes internal file handle handling
functions to read(), open(), close() and get the length of
a certain file handle.
However the code using it is only interested in either
reading and entire named file into memory or getting the
file length of a file referred by name. No file handles
are used.
Thus make the file handle code internal to this file by
removing these functions from the semihosting header file
and staticize them.
This gives us some freedom to rearrange the semihosting
code without affecting the external interface.
Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jan Luebbe [Sun, 14 Dec 2014 15:34:49 +0000 (16:34 +0100)]
arm: mxs: olinuxino: move DRAM config tuning to SPL
The weak mxs_adjust_memory_params function is called from spl_mem_init.c,
so it must be linked into the SPL to have an effect. Move it from
mx23_olinuxino.c to spl_boot.c.
This change was verified by reading back the register values.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Sun, 23 Nov 2014 03:52:20 +0000 (11:52 +0800)]
imx:mx6 fix return value of mxc_get_clock
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0xffffffff', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.
Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Simon Glass [Wed, 17 Dec 2014 03:21:02 +0000 (20:21 -0700)]
x86: Add a script to process Intel microcode files
Intel delivers microcode updates in a microcode.dat file which must be
split up into individual files for each CPU. Add a tool which performs
this task. It can list available microcode updates for each model and
produce a new microcode update in U-Boot's .dtsi format.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Wed, 17 Dec 2014 07:50:49 +0000 (15:50 +0800)]
x86: Clean up the FSP support codes
This is the follow-on patch to clean up the FSP support codes:
- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
stackless environment
- Add comments to mention init(¶ms) in fsp_init() cannot
be removed
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Dec 2014 07:50:48 +0000 (15:50 +0800)]
x86: Add a README.x86 for U-Boot on x86 support
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
(Use 'Link' as the name for the Chromebook Pixel consistently)
Bin Meng [Wed, 17 Dec 2014 07:50:46 +0000 (15:50 +0800)]
x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Dec 2014 07:50:45 +0000 (15:50 +0800)]
x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Dec 2014 07:50:44 +0000 (15:50 +0800)]
x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Dec 2014 07:50:38 +0000 (15:50 +0800)]
x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 17 Dec 2014 07:50:37 +0000 (15:50 +0800)]
x86: Convert microcode format to device-tree-only
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 16 Dec 2014 05:02:41 +0000 (22:02 -0700)]
x86: Correct problems in the microcode loading
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.
Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.
Simon Glass [Tue, 16 Dec 2014 05:02:38 +0000 (22:02 -0700)]
x86: ifdtool: Add support for early microcode access
Some Intel CPUs use an 'FSP' binary blob which provides an inflexible
means of starting up the CPU. One result is that microcode updates can only
be done before RAM is available and therefore parsing of the device tree
is impracticle.
Worse, the addess of the microcode update must be stored in ROM since a
pointer to its start address and size is passed to the 'FSP' blob. It is
not possible to perform any calculations to obtain the address and size.
To work around this, ifdtool is enhanced to work out the address and size of
the first microcode update it finds in the supplied device tree. It then
writes these into the correct place in the ROM. U-Boot can then start up
the FSP correctly.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Steve Rae [Fri, 12 Dec 2014 23:51:54 +0000 (15:51 -0800)]
fastboot: handle flash write to GPT partitions
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Additionally, prepare and write the Backup GUID Partition Table.
Signed-off-by: Steve Rae <srae@broadcom.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[Test HW: Exynos4412 - Trats2]
dfu: dfu_get_buf: check the value of env dfu_bufsiz before use
In function dfu_get_buf(), the size of allocated buffer could
be defined by the env variable. The size from this variable
was passed for memalign() without checking its value.
And the the memalign will return non null pointer for size 0.
This could possibly cause data abort, so now the value of var
is checked before use. And if this variable is set to 0 then
the default size will be used.
This commit also changes the base passed to simple_strtoul()
to 0. Now decimal and hex values can be used for the variable
dfu_bufsiz.
gadget: f_thor: check pointers before use in download_tail()
Some pointers in function download_tail() were not checked
before the use. This could possibly cause the data abort.
To avoid this, check if the pointers are not null is added.
dfu: mmc: check if mmc device exists in mmc_block_op()
The function mmc_block_op() is the last function before
the physicall data write, but the mmc device pointer is not
checked. If mmc device not exists, then data abort will occur.
To avoid this, first the mmc device pointer is checked.
Rob Herring [Wed, 10 Dec 2014 20:43:04 +0000 (14:43 -0600)]
fastboot: add support for continue command
The fastboot continue command is defined to exit fastboot and continue
autoboot. This commit implements the continue command and the exiting of
fastboot only. Subsequent u-boot commands can be processed after exiting
fastboot. Autoboot should implement a boot script such as "fastboot; mmc
read <...>; bootm" to fully implement the fastboot continue function.
Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
Bo Shen [Mon, 15 Dec 2014 10:12:47 +0000 (18:12 +0800)]
USB: gadget: atmel_usba_udc: fix transfer hang issue
When receive data, the RXRDY in status register set by hardware
after a new packet has been stored in the endpoint FIFO. After,
we copy from FIFO, we clear it, make the FIFO can be accessed
again.
In the receive_data() function, this bit RXRDY has been cleared.
So, after the receive_data() function return, this bit should
not be cleared again, or else it will cause the accessing FIFO
corrupt, which will make the data loss.
Pavel Machek [Thu, 11 Dec 2014 17:06:31 +0000 (18:06 +0100)]
arm: socfpga: board: Repair Micrel PHY tuning
Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Tom Rini <trini@ti.com> Cc: Pavel Machek <pavel@denx.de>
gaurav rana [Thu, 4 Dec 2014 07:30:41 +0000 (13:00 +0530)]
crypto/fsl: Fix RNG instantiation failure.
Corrected the order of arguments in memset in run_descriptor
function. Wrong order of argumnets led to improper initialization
of members of struct type result. This resulted in RNG instantiation
error.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Wed, 3 Dec 2014 07:27:03 +0000 (15:27 +0800)]
net/fm: update ft_fixup_port to differentiate dual-role mac
we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Tue, 2 Dec 2014 19:21:09 +0000 (11:21 -0800)]
powerpc/mpc85xx: Fix DDR TLB mapping leftover
Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.
Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de> CC: Scott Wood <scottwood@freescale.com>
York Sun [Tue, 2 Dec 2014 19:18:09 +0000 (11:18 -0800)]
driver/ddr/fsl: Fix MRC_CYC calculation for DDR3
For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.
Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)
The generic asmlinkage is defined in <linux/linkage.h>. If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:32 +0000 (21:05 +0800)]
x86: Add a simple command to show FSP HOB information
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.
Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:31 +0000 (21:05 +0800)]
x86: Support Intel FSP initialization path in start.S
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.
The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:28 +0000 (21:05 +0800)]
x86: Initial import from Intel FSP release for Queensbay platform
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.
Bin Meng [Fri, 12 Dec 2014 13:05:25 +0000 (21:05 +0800)]
x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:23 +0000 (21:05 +0800)]
x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:22 +0000 (21:05 +0800)]
x86: Clean up asm-offsets
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:21 +0000 (21:05 +0800)]
x86: Refactor u-boot.rom build rules
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:20 +0000 (21:05 +0800)]
tools/ifdtool: Support writing multiple files (-w) simultaneously
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:19 +0000 (21:05 +0800)]
x86: Make ROM_SIZE configurable in Kconfig
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log