]> git.sur5r.net Git - u-boot/log
u-boot
9 years agosun6i: dram: Do not try to initialize a second dram chan on A31s
Hans de Goede [Sat, 15 Nov 2014 22:18:18 +0000 (23:18 +0100)]
sun6i: dram: Do not try to initialize a second dram chan on A31s

The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosun6i: Add sunxi_get_ss_bonding_id() function
Hans de Goede [Sat, 15 Nov 2014 21:55:53 +0000 (22:55 +0100)]
sun6i: Add sunxi_get_ss_bonding_id() function

Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between
the A31s and the A31.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agosun6i: Make dram clk and zq value Kconfig options
Hans de Goede [Sat, 15 Nov 2014 18:46:39 +0000 (19:46 +0100)]
sun6i: Make dram clk and zq value Kconfig options

It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.

Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Tue, 13 Jan 2015 18:39:25 +0000 (13:39 -0500)]
Merge git://git.denx.de/u-boot-x86

9 years agox86: Remove CONFIG_DISPLAY_CPUINFO in chromebook_link.h
Bin Meng [Tue, 6 Jan 2015 06:35:38 +0000 (14:35 +0800)]
x86: Remove CONFIG_DISPLAY_CPUINFO in chromebook_link.h

CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Update README.x86 for coreboot support
Bin Meng [Tue, 6 Jan 2015 14:14:24 +0000 (22:14 +0800)]
x86: Update README.x86 for coreboot support

Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Configure pci memory regions
Bin Meng [Tue, 6 Jan 2015 14:14:23 +0000 (22:14 +0800)]
x86: coreboot: Configure pci memory regions

Configure coreboot pci memory regions so that pci device drivers
could work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Wrap cros_ec initialization
Bin Meng [Tue, 6 Jan 2015 14:14:22 +0000 (22:14 +0800)]
x86: coreboot: Wrap cros_ec initialization

cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Make chromebook_link the default board for coreboot
Bin Meng [Tue, 6 Jan 2015 14:14:21 +0000 (22:14 +0800)]
x86: Make chromebook_link the default board for coreboot

Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.

Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.

To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove include/configs/coreboot.h
Bin Meng [Tue, 6 Jan 2015 14:14:20 +0000 (22:14 +0800)]
x86: Remove include/configs/coreboot.h

Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Move CONFIG_SYS_CAR_xxx to Kconfig
Bin Meng [Tue, 6 Jan 2015 14:14:19 +0000 (22:14 +0800)]
x86: Move CONFIG_SYS_CAR_xxx to Kconfig

Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
Bin Meng [Tue, 6 Jan 2015 14:14:18 +0000 (22:14 +0800)]
x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig

There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
Bin Meng [Tue, 6 Jan 2015 14:14:17 +0000 (22:14 +0800)]
x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable

In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want to make these two options configurable
so that we can easily change them during 'make menuconfig' so that
the generated U-Boot image for coreboot is board configuration aware.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
Bin Meng [Tue, 6 Jan 2015 14:14:16 +0000 (22:14 +0800)]
x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected

When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Bin Meng [Tue, 6 Jan 2015 14:14:15 +0000 (22:14 +0800)]
x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig

Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Allow a hardcoded TSC frequency provided by Kconfig
Bin Meng [Tue, 6 Jan 2015 14:14:14 +0000 (22:14 +0800)]
x86: Allow a hardcoded TSC frequency provided by Kconfig

By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.

Normally the bypass should be turned on in a simulation environment
like qemu.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Set up timer base correctly
Bin Meng [Tue, 6 Jan 2015 14:14:13 +0000 (22:14 +0800)]
x86: coreboot: Set up timer base correctly

If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.

Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: fsp: Drop get_hob_type() and get_hob_length()
Bin Meng [Tue, 6 Jan 2015 06:04:36 +0000 (14:04 +0800)]
x86: fsp: Drop get_hob_type() and get_hob_length()

These two are not worth having separate inline functions as they are
really simple, so drop them.

Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add an 'mtrr' command to list and adjust MTRRs
Simon Glass [Thu, 1 Jan 2015 23:18:15 +0000 (16:18 -0700)]
x86: Add an 'mtrr' command to list and adjust MTRRs

It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.

Update the documentation to list some of the available commands.

This does not support fixed MTRRs as yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: ivybridge: Update microcode early in boot
Simon Glass [Thu, 1 Jan 2015 23:18:14 +0000 (16:18 -0700)]
x86: ivybridge: Update microcode early in boot

At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.

For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Disable CAR before relocation on platforms that need it
Simon Glass [Thu, 1 Jan 2015 23:18:13 +0000 (16:18 -0700)]
x86: Disable CAR before relocation on platforms that need it

For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: ivybridge: Add a way to turn off the CAR
Simon Glass [Thu, 1 Jan 2015 23:18:12 +0000 (16:18 -0700)]
x86: ivybridge: Add a way to turn off the CAR

Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Commit the current MTRRs before relocation
Simon Glass [Thu, 1 Jan 2015 23:18:11 +0000 (16:18 -0700)]
x86: Commit the current MTRRs before relocation

Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: ivybridge: Request MTRRs for DRAM regions
Simon Glass [Thu, 1 Jan 2015 23:18:10 +0000 (16:18 -0700)]
x86: ivybridge: Request MTRRs for DRAM regions

We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.

We set RAM as cacheable (with write-back) and registers as non-cacheable.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: board_f: Adjust x86 boot order for performance
Simon Glass [Thu, 1 Jan 2015 23:18:09 +0000 (16:18 -0700)]
x86: board_f: Adjust x86 boot order for performance

For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: ivybridge: Set up an MTRR for the video frame buffer
Simon Glass [Thu, 1 Jan 2015 23:18:08 +0000 (16:18 -0700)]
x86: ivybridge: Set up an MTRR for the video frame buffer

Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add support for MTRRs
Simon Glass [Thu, 1 Jan 2015 23:18:07 +0000 (16:18 -0700)]
x86: Add support for MTRRs

Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: ivybridge: Drop support for ROM caching
Simon Glass [Thu, 1 Jan 2015 23:18:06 +0000 (16:18 -0700)]
x86: ivybridge: Drop support for ROM caching

This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: pci: Display vesa modes in hex
Simon Glass [Thu, 1 Jan 2015 23:18:05 +0000 (16:18 -0700)]
x86: pci: Display vesa modes in hex

The hex value is more commonly understood, so use that instead of decimal.
Add a 0x prefix to avoid confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: Tidy up VESA mode numbers
Simon Glass [Thu, 1 Jan 2015 23:18:04 +0000 (16:18 -0700)]
x86: Tidy up VESA mode numbers

There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Use cache, don't clear the display in video BIOS
Simon Glass [Thu, 1 Jan 2015 23:18:03 +0000 (16:18 -0700)]
x86: Use cache, don't clear the display in video BIOS

There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: ivybridge: Only run the Video BIOS when video is enabled
Simon Glass [Thu, 1 Jan 2015 23:18:02 +0000 (16:18 -0700)]
x86: ivybridge: Only run the Video BIOS when video is enabled

This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.

We could add a command to run the video BIOS later when needed, but this is
not considered at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: video: Add debug option to time the BIOS copy
Simon Glass [Thu, 1 Jan 2015 23:18:01 +0000 (16:18 -0700)]
x86: video: Add debug option to time the BIOS copy

This can be very slow - typically 80ms even on a fast machine since it uses
the SPI flash to read the data. Add an option to display the time taken.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: pci: Don't return a vesa mode when there is not video
Simon Glass [Thu, 1 Jan 2015 23:18:00 +0000 (16:18 -0700)]
x86: pci: Don't return a vesa mode when there is not video

If the video has not been set up, we should not return a success code. This
can be detected by seeing if any of the variables are non-zero.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: video: Add a debug() to display the frame buffer address
Simon Glass [Thu, 1 Jan 2015 23:17:59 +0000 (16:17 -0700)]
x86: video: Add a debug() to display the frame buffer address

Provide a way to display this address when booting.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Correct ifdtool microcode calculation
Simon Glass [Thu, 1 Jan 2015 23:17:56 +0000 (16:17 -0700)]
x86: Correct ifdtool microcode calculation

This currently assumes that U-Boot resides at the start of ROM. Update
it to remove this assumption.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: Drop RAMTOP Kconfig
Simon Glass [Thu, 1 Jan 2015 23:17:55 +0000 (16:17 -0700)]
x86: Drop RAMTOP Kconfig

We don't need this in U-Boot since we calculate it based on available memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: Correct XIP_ROM_SIZE
Simon Glass [Thu, 1 Jan 2015 23:17:54 +0000 (16:17 -0700)]
x86: Correct XIP_ROM_SIZE

This should default to the size of the ROM for faster execution before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: crownbay: Add pci devices in the dts file
Bin Meng [Wed, 31 Dec 2014 08:05:14 +0000 (16:05 +0800)]
x86: crownbay: Add pci devices in the dts file

The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.

Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Use ePAPR defined properties for x86-uart
Bin Meng [Wed, 31 Dec 2014 08:05:13 +0000 (16:05 +0800)]
x86: Use ePAPR defined properties for x86-uart

Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoserial: ns16550: Support ns16550 compatible pci uart devices
Bin Meng [Wed, 31 Dec 2014 08:05:12 +0000 (16:05 +0800)]
serial: ns16550: Support ns16550 compatible pci uart devices

There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.

Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agofdt: Add several apis to decode pci device node
Bin Meng [Wed, 31 Dec 2014 08:05:11 +0000 (16:05 +0800)]
fdt: Add several apis to decode pci device node

This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)

9 years agoPM9G45 adding generic board support
Georgi Botev [Tue, 13 Jan 2015 10:30:17 +0000 (12:30 +0200)]
PM9G45 adding generic board support

Signed-off-by: Georgi Botev <botev@ronetix.at>
9 years agoPM9261 adding generic board support
Georgi Botev [Tue, 13 Jan 2015 10:15:55 +0000 (12:15 +0200)]
PM9261 adding generic board support

Signed-off-by: Georgi Botev <botev@ronetix.at>
9 years agoPM9263 adding generic board support
Georgi Botev [Tue, 13 Jan 2015 10:07:21 +0000 (12:07 +0200)]
PM9263 adding generic board support

Signed-off-by: Georgi Botev <botev@ronetix.at>
9 years agoppc4xx: switch VOM405 to generic board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:35 +0000 (22:47 +0100)]
ppc4xx: switch VOM405 to generic board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: switch PMC405DE to generic board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:34 +0000 (22:47 +0100)]
ppc4xx: switch PMC405DE to generic board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: switch PLU405 to generic board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:33 +0000 (22:47 +0100)]
ppc4xx: switch PLU405 to generic board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: switch CPCI2DP to generic board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:32 +0000 (22:47 +0100)]
ppc4xx: switch CPCI2DP to generic board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: cleanup CPCI4052 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:31 +0000 (22:47 +0100)]
ppc4xx: cleanup CPCI4052 board

- remove some obsolete code
- switch to generic board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove some CPCI405 variants
Matthias Fuchs [Mon, 12 Jan 2015 21:47:30 +0000 (22:47 +0100)]
ppc4xx: remove some CPCI405 variants

only keep CPCI4052

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove G2000 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:29 +0000 (22:47 +0100)]
ppc4xx: remove G2000 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove WUH405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:28 +0000 (22:47 +0100)]
ppc4xx: remove WUH405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove VOH405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:27 +0000 (22:47 +0100)]
ppc4xx: remove VOH405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove PMC405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:26 +0000 (22:47 +0100)]
ppc4xx: remove PMC405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove PCI405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:25 +0000 (22:47 +0100)]
ppc4xx: remove PCI405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove OCRTC board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:24 +0000 (22:47 +0100)]
ppc4xx: remove OCRTC board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove HUB405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:23 +0000 (22:47 +0100)]
ppc4xx: remove HUB405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove HH405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:22 +0000 (22:47 +0100)]
ppc4xx: remove HH405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove DU440 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:21 +0000 (22:47 +0100)]
ppc4xx: remove DU440 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove DU405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:20 +0000 (22:47 +0100)]
ppc4xx: remove DU405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove DP405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:19 +0000 (22:47 +0100)]
ppc4xx: remove DP405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove CPCIISER4 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:18 +0000 (22:47 +0100)]
ppc4xx: remove CPCIISER4 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove CMS700 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:17 +0000 (22:47 +0100)]
ppc4xx: remove CMS700 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove ASH405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:16 +0000 (22:47 +0100)]
ppc4xx: remove ASH405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppc4xx: remove AR405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:15 +0000 (22:47 +0100)]
ppc4xx: remove AR405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agoppx4xx: remove APC405 board
Matthias Fuchs [Mon, 12 Jan 2015 21:47:14 +0000 (22:47 +0100)]
ppx4xx: remove APC405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
9 years agom68k: remove TASREG board
Matthias Fuchs [Mon, 12 Jan 2015 21:33:38 +0000 (22:33 +0100)]
m68k: remove TASREG board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Stefan Roese <sr@denx.de>
9 years agox86: Simplify the fsp hob access functions
Bin Meng [Tue, 30 Dec 2014 08:02:05 +0000 (16:02 +0800)]
x86: Simplify the fsp hob access functions

Remove the troublesome union hob_pointers so that some annoying casts
are no longer needed in those hob access routines. This also improves
the readability.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agopci: Make pci apis usable before relocation
Bin Meng [Tue, 30 Dec 2014 14:53:21 +0000 (22:53 +0800)]
pci: Make pci apis usable before relocation

Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.

Some variables are declared as static so change them to be either
stack variable or global data member so that they can be used before
relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which
just affects some print format.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Support pci bus scan in the early phase
Bin Meng [Tue, 30 Dec 2014 14:53:20 +0000 (22:53 +0800)]
x86: Support pci bus scan in the early phase

On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c
Bin Meng [Tue, 30 Dec 2014 14:53:19 +0000 (22:53 +0800)]
x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c

arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Clean up the board dts files
Bin Meng [Wed, 24 Dec 2014 05:06:39 +0000 (13:06 +0800)]
x86: Clean up the board dts files

This commits cleans up the board dts files.

- Correct the serial port register size to 8
- Remove the misleading status = "disabled" statement in the
  serial.dtsi
- Move the inclusion of skeleton.dtsi from serial.dtsi to board
  dts files
- Let the board dts file define stdout-path in the chosen node
- Remove device nodes in board dts files thar are duplicated to
  skeleton.dtsi

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Rename coreboot.dsti to serial.dtsi
Bin Meng [Wed, 24 Dec 2014 05:06:38 +0000 (13:06 +0800)]
x86: Rename coreboot.dsti to serial.dtsi

The name of coreboot.dtsi is misleading, as it actually describes
the legacy serial port device node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove alex.dts in arch/x86/dts
Bin Meng [Wed, 24 Dec 2014 05:06:37 +0000 (13:06 +0800)]
x86: Remove alex.dts in arch/x86/dts

No board is using alex.dts, so remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoPrepare v2015.01 v2015.01
Tom Rini [Mon, 12 Jan 2015 14:39:08 +0000 (09:39 -0500)]
Prepare v2015.01

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoNokia RX-51: Do not call secure PPA routine on non secure devices
Pali Rohár [Thu, 8 Jan 2015 09:11:40 +0000 (10:11 +0100)]
Nokia RX-51: Do not call secure PPA routine on non secure devices

Since commit 41623c91b09a0c865fab41acdaff30f060f29ad6 u-boot running in qemu is
crashing in function do_omap3_emu_romcode_call(). RX-51 board uses this function
for Cortex-A8 errata 430973 workaround (Set IBE bit in ACR) which is needed only
on real secure device and not in qemu.

This board patch just disable calling secure PPA routine on non secure devices.
Qemu implements GP device and with this patch u-boot is working in qemu again.

Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
9 years agopowerpc: xes: Add maintainer
Peter Tyser [Fri, 9 Jan 2015 21:42:51 +0000 (15:42 -0600)]
powerpc: xes: Add maintainer

Add Peter Tyser as the maintainer of Extreme Engineering Solutions products.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
9 years agopowerpc: xes: Convert to generic board
John Schmoller [Fri, 9 Jan 2015 21:42:50 +0000 (15:42 -0600)]
powerpc: xes: Convert to generic board

Convert Extreme Engineering Solutions products to use generic board
support.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
9 years agoARM: remove redudant information from Kconfig files
Masahiro Yamada [Fri, 19 Dec 2014 05:27:13 +0000 (14:27 +0900)]
ARM: remove redudant information from Kconfig files

- "string" type for SYS_* is defined in arch/Kconfig
 - SYS_CPU "armv7" has been replaced with "select CPU_V7"
 - SYS_SOC "tegra124" is already defined in tegra124/Kconfig

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
9 years agoomap: beagle_x15: add MAINTAINERS
Masahiro Yamada [Fri, 19 Dec 2014 05:20:58 +0000 (14:20 +0900)]
omap: beagle_x15: add MAINTAINERS

Commit 1e4ad74b875f (beagle_x15: add board support for Beagle x15)
missed to add board/ti/beagle_x15/MAINTAINERS.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Felipe Balbi <balbi@ti.com>
9 years agostv0991: record defconfig ownership in MAINTAINERS
Masahiro Yamada [Fri, 19 Dec 2014 05:19:07 +0000 (14:19 +0900)]
stv0991: record defconfig ownership in MAINTAINERS

This commit fixes warnings reported by tools/genboardscfg.py.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
9 years agoARM: kirkwood: dns325: Add generic board support
Stefan Herbrechtsmeier [Sun, 28 Dec 2014 13:09:51 +0000 (14:09 +0100)]
ARM: kirkwood: dns325: Add generic board support

Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
9 years agoChange e-mail address of Stefan Herbrechtsmeier
Stefan Herbrechtsmeier [Sun, 28 Dec 2014 13:09:50 +0000 (14:09 +0100)]
Change e-mail address of Stefan Herbrechtsmeier

Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
9 years agocommon/board_f.c: fix compile error when tracing disabled
Kevin Hilman [Mon, 15 Dec 2014 20:07:52 +0000 (12:07 -0800)]
common/board_f.c: fix compile error when tracing disabled

When CONFIG_TRACE is disabled, linking fails with:

common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to `trace_early_init'

To fix, wrap trace init calls with #ifdef CONFIG_TRACE.

While at it, remove the static inline version of the init call from
trace.h as suggested by Simon Glass, since it doesnt work.

Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agotools/kwbimage.c: fix parser error handling
Andreas Bießmann [Fri, 24 Oct 2014 21:25:52 +0000 (23:25 +0200)]
tools/kwbimage.c: fix parser error handling

The two error checks for image_boot_mode_id and image_nand_ecc_mode_id where
wrong and would never fail, fix that!

This was detected by Apple's clang compiler:
---8<---
  HOSTCC  tools/kwbimage.o
tools/kwbimage.c:553:20: warning: comparison of unsigned expression < 0 is always false [-Wtautological-compare]
                if (el->bootfrom < 0) {
                    ~~~~~~~~~~~~ ^ ~
tools/kwbimage.c:571:23: warning: comparison of unsigned expression < 0 is always false [-Wtautological-compare]
                if (el->nandeccmode < 0) {
                    ~~~~~~~~~~~~~~~ ^ ~
2 warnings generated.
--->8---

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-By: Jeroen Hofstee <jeroen@myspectrum.nl>
9 years agoARM: atmel: sama5d3xek: fix the LCD parameters
Bo Shen [Thu, 8 Jan 2015 07:20:13 +0000 (15:20 +0800)]
ARM: atmel: sama5d3xek: fix the LCD parameters

Remove unused vsync parameter, and correct the include file.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
9 years agoARM: atmel: sama5d4xek: fix the LCD parameters
Bo Shen [Thu, 8 Jan 2015 07:20:12 +0000 (15:20 +0800)]
ARM: atmel: sama5d4xek: fix the LCD parameters

Remove unused vsync parameter, and correct the include file.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
9 years agoARM: atmel: sama5d4 xplained: fix the LCD parameters
Bo Shen [Thu, 8 Jan 2015 07:20:11 +0000 (15:20 +0800)]
ARM: atmel: sama5d4 xplained: fix the LCD parameters

Correct the LCD pixel clock, remove unused vsync parameter,
and also correct the include file.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
9 years agofix: tools: kwbimage.c: Initialize headersz to suppress warning
Łukasz Majewski [Fri, 21 Nov 2014 08:22:43 +0000 (09:22 +0100)]
fix: tools: kwbimage.c: Initialize headersz to suppress warning

When building with my toolchain (4.8.2):
CROSS_COMPILE=/home/lukma/work/ptxdist/toolchains/arm/OSELAS.Toolchain-2013.12.0/arm-v7a-linux-gnueabi/gcc-4.8.2-glibc-2.18-binutils-2.24-kernel-3.12-sanitized/bin/arm-v7a-linux-gnueabi-

I see following WARNING:
tools/kwbimage.c: In function "kwbimage_set_header":
tools/kwbimage.c:803:8: warning: "headersz" may be used uninitialized in this function [-Wmaybe-uninitialized]
  memcpy(ptr, image, headersz);
        ^
This fix aims to suppress it.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
9 years agoMerge git://git.denx.de/u-boot-nand-flash
Tom Rini [Sat, 10 Jan 2015 18:27:27 +0000 (13:27 -0500)]
Merge git://git.denx.de/u-boot-nand-flash

9 years agoarc: introduce "mdbtrick" target
Alexey Brodkin [Mon, 29 Dec 2014 12:42:57 +0000 (15:42 +0300)]
arc: introduce "mdbtrick" target

MetaWare debugger (MDB) is still used as a primary tool for interaction
with target via JTAG. Moreover some very advanced features are not yet
implemented in GDB for ARC (and not sure if they will be implemnted
sometime soon given complexity and rare need for those features for
common user).

So if we're talking about development process when U-Boot is loaded in
target memory not by low-level boot-loader but manually through JTAG
chances are high developer uses MDB for it.

But MDB doesn't support PIE (position-independent executable) - it will
refuse to even start - that means no chance to load elf contents on
target.
Then the only way to load U-Boot in MDB is to fake it by:
  1. Reset PIE flag in ELF header
     This is simpe - on attempt to open elf MDB checks header and if it
doesn't match its expectation refuces to use provided elf.
  2. Strip all debug information from elf
     If (1) is done then MDB will open elf but on parsing of elf's debug
info it will refuse to process due to debug info it cannot understand
(symbols with PIE relocation).

Even though it could be done manually (I got it documented quite a while
ago here http://www.denx.de/wiki/U-Boot/ARCNotes) having this automated
way is very convenient. User may build U-Boot that will be loaded on
target via MDB saying "make mdbtrick".

Then if we now apply the manipulation MDB will happily start and will
load all required sections into the target.

Indeed there will be no source-level debug info available. But still MDB
will do its work on showing disassembly, global symbols, registers,
accessing low-level debug facilities etc.

As a summary - this is a pretty dirty hack but it simplifies life a lot
for us ARc developers.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
9 years agomtd: nand: do not scan BBT after scrub
Masahiro Yamada [Fri, 26 Dec 2014 13:20:58 +0000 (22:20 +0900)]
mtd: nand: do not scan BBT after scrub

Currently, "nand scrub" runs chip->scan_bbt at the end of
nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set.

It violates the intention of NAND_SKIP_BBTSCAN.

Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that
chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set.

Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt()
right after scrub.  We can be lazier here because the BBT is scanned
at the next call of nand_block_checkbad().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
9 years agomtd: nand: Mark the BBT as scanned prior to calling scan_bbt again
Masahiro Yamada [Fri, 26 Dec 2014 13:20:57 +0000 (22:20 +0900)]
mtd: nand: Mark the BBT as scanned prior to calling scan_bbt again

Commit 35c204d8a9d0 (nand: reinstate lazy bad block scanning)
broke NAND_BBT_USE_FLASH feature.

Its git-log claimed that it reinstated the change as by commit
fb49454b1b6c ("nand: reinstate lazy bad block scanning"), but it moved
"chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);".

It causes recursion if scan_bbt does not find a flash based BBT
and tries to write one, and the attempt to erase the BBT area
causes a bad block check.

Reinstate commit ff49ea8977b5 (NAND: Mark the BBT as scanned prior to
calling scan_bbt.).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rostislav Lisovy <lisovy@merica.cz>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
9 years agomtd: nand: revive "nand scrub" command
Masahiro Yamada [Tue, 16 Dec 2014 06:36:33 +0000 (15:36 +0900)]
mtd: nand: revive "nand scrub" command

Since commit ff94bc40af34 (mtd, ubi, ubifs: resync with Linux-3.14),
the "nand scrub" command has not been working.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
9 years agoarm: vf610: fix boot from SD-card
Stefan Agner [Thu, 8 Jan 2015 17:18:25 +0000 (18:18 +0100)]
arm: vf610: fix boot from SD-card

Boot from SD-card (and probably also from NAND) was broken since
commit d6d07a9bec ("arm: vf610: add NAND support for vf610twr").
It looks like the increased size of U-Boot lead to a situation
where the boot ROM overwrote its own stack/heap while loading
U-Boot from the SD-card to the SRAM. However, U-Boot worked fine
when loaded through USB serial loader directly into SRAM. It
looks like loading from SD-card uses other stack/heap location
then the serial loader (or maybe no stack or heap at all).
This fix moves U-Boot to gfxRAM, which is 512kB in size and is not
used by the boot ROM nor the SD-card loader of it.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
9 years agoarm: build arch memset/memcpy in Thumb2 mode
Stefan Agner [Thu, 18 Dec 2014 17:10:33 +0000 (18:10 +0100)]
arm: build arch memset/memcpy in Thumb2 mode

Resynchronize memcpy/memset with kernel 3.17 and build them in
Thumb2 mode (unified syntax). Those assembler files can be built
and linked in ARM mode too, however when calling them from Thumb2
built code, the stack got corrupted and the copy did not succeed
(the exact details have not been traced back). However, the Linux
kernel builds those files in Thumb2 mode. Hence U-Boot should
build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set.

To build the files without warning, some assembler instructions
had to be replaced with their UAL compliant variant (thanks
Jeroen for this input).

To build the file in Thumb2 mode the implicit-it=always option need
to be set to generate Thumb2 compliant IT instructions where needed.
We add this option to the general AFLAGS when building for Thumb2.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Thu, 8 Jan 2015 18:50:38 +0000 (13:50 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

9 years agomx25: Fix boot hang by avoiding vector relocation
Fabio Estevam [Tue, 6 Jan 2015 15:06:48 +0000 (13:06 -0200)]
mx25: Fix boot hang by avoiding vector relocation

Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx25pdk
hangs like this:

CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Reset cause: WDOG
Board: MX25PDK
I2C:   ready
DRAM:  64 MiB
(hangs)

Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX25 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.

This allows mx25 to boot again.

Acked-By: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoimx:mx6sxsabresd support qspi AHB read
Peng Fan [Thu, 8 Jan 2015 02:40:21 +0000 (10:40 +0800)]
imx:mx6sxsabresd support qspi AHB read

Add CONFIG_SYS_FSL_QSPI_AHB in header file to enable AHB in driver.
In order to count the time, add CONFIG_CMD_TIME.

Using AHB read can improve the the read speed about 30%.

AHB read:
=> time sf read 0x8f800000 0 100000
SF: 1048576 bytes @ 0x0 Read: OK
time: 0.174 seconds

=> time sf read 0x8f800000 1000000 100000
SF: 1048576 bytes @ 0x1000000 Read: OK
time: 0.174 seconds

IP read:
=> time sf read 0x8f800000 0 100000
SF: 1048576 bytes @ 0x0 Read: OK
time: 0.227 seconds

=> time sf read 0x8f800000 1000000 100000
SF: 1048576 bytes @ 0x1000000 Read: OK
time: 0.227 seconds

Note:
Quad read is not supported in driver, now. In my side, using AHB and Quad read
can achieve about 16MB/s. Anyway, I have plan to reimplement the driver using
DTB and DM, then make the code cleaner and more feature can be added.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>