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9 years agoARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes
Masahiro Yamada [Fri, 11 Sep 2015 11:17:40 +0000 (20:17 +0900)]
ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes

In the next commit, I will add "u-boot,dm-pre-reloc" to the "soc"
(simple-bus) nodes in UniPhier device trees.  But, before that,
CONFIG_SYS_MALLOC_F_LEN must be increased.

Adding "u-boot,dm-pre-reloc" to a simple-bus node causes it to bind
all of its child nodes.  (See simple_bus_post_bind() function)

Actually, I want only UART0 and pinctrl to be bound in SPL and before
relocation in U-boot proper.  But, with "u-boot,dm-pre-reloc" in the
simple-bus node, all the other unwanted nodes are also bound.  The
default value for CONFIG_SYS_MALLOC_F_LEN, 0x400, is not enough for
that.  Increase the pre-reloc malloc size to 0x2000, hoping the root
cause will be fixed later.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agoARM: uniphier: enable simple-bus driver for SPL
Masahiro Yamada [Fri, 11 Sep 2015 11:17:39 +0000 (20:17 +0900)]
ARM: uniphier: enable simple-bus driver for SPL

In UniPhier device trees, pinctrl device nodes are located under the
simple-bus (AMBA).

This is needed to bind pinctrl devices in SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agopinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driver
Masahiro Yamada [Fri, 11 Sep 2015 11:17:38 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driver

Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agopinctrl: uniphier: add UniPhier ProXstream2 pinctrl driver
Masahiro Yamada [Fri, 11 Sep 2015 11:17:37 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driver

Add pin configuration and pinmux support for UniPhier ProXstream2
SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agopinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driver
Masahiro Yamada [Fri, 11 Sep 2015 11:17:36 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driver

Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agopinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver
Masahiro Yamada [Fri, 11 Sep 2015 11:17:35 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driver

Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agopinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver
Masahiro Yamada [Fri, 11 Sep 2015 11:17:34 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driver

Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agopinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver
Masahiro Yamada [Fri, 11 Sep 2015 11:17:33 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driver

Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agopinctrl: uniphier: add UniPhier pinctrl core support
Masahiro Yamada [Fri, 11 Sep 2015 11:17:32 +0000 (20:17 +0900)]
pinctrl: uniphier: add UniPhier pinctrl core support

The core support for the pinctrl drivers for all the UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agopinctrl: move dm_scan_fdt_node() out of pinctrl uclass
Masahiro Yamada [Sat, 5 Sep 2015 16:44:50 +0000 (01:44 +0900)]
pinctrl: move dm_scan_fdt_node() out of pinctrl uclass

Commit c5acf4a2b3c6 ("pinctrl: Add the concept of peripheral IDs")
added some additional change that was not mentioned in the git-log.

That commit added dm_scan_fdt_node() in the pinctrl uclass binding.
It should be handled by the simple-bus driver or the low-level
driver, not by the pinctrl framework.

I guess Simon's motivation was to bind GPIO banks located under the
Rockchip pinctrl device.  It is true some chips have sub-devices
under their pinctrl devices, but it is basically SoC-specific matter.

This commit partly reverts commit c5acf4a2b3c6 to keep the only
pinctrl-generic features in the uclass.  The dm_scan_fdt_node()
should be called from the rk3288_pinctrl driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Thu, 17 Sep 2015 21:00:08 +0000 (17:00 -0400)]
Merge git://git.denx.de/u-boot-x86

9 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Thu, 17 Sep 2015 20:59:58 +0000 (16:59 -0400)]
Merge git://git.denx.de/u-boot-dm

9 years agox86: quark: Configure MTRR to enable cache
Bin Meng [Mon, 14 Sep 2015 07:07:41 +0000 (00:07 -0700)]
x86: quark: Configure MTRR to enable cache

Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.

We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.

With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agox86: doc: Add DMI to the TODO list
Bin Meng [Thu, 10 Sep 2015 06:20:30 +0000 (23:20 -0700)]
x86: doc: Add DMI to the TODO list

Desktop Management Interface (DMI) is not supported by U-Boot now.
Add it to the TODO list.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: doc: Document some porting hints about Intel Quark
Bin Meng [Thu, 10 Sep 2015 06:20:29 +0000 (23:20 -0700)]
x86: doc: Document some porting hints about Intel Quark

Document porting considerations for Intel Quark based board,
including MRC parameters and PCIe initialization.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: galileo: Add PCIe root port IRQ routing
Bin Meng [Thu, 10 Sep 2015 06:20:28 +0000 (23:20 -0700)]
x86: galileo: Add PCIe root port IRQ routing

Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: quark: Initialize thermal sensor properly
Bin Meng [Thu, 10 Sep 2015 06:20:27 +0000 (23:20 -0700)]
x86: quark: Initialize thermal sensor properly

Thermal sensor on Quark SoC needs to be properly initialized per
Quark firmware writer guide, otherwise when booting Linux kernel,
it triggers system shutdown because of wrong temperature in the
thermal sensor is detected by the kernel driver (see below):

[    5.119819] thermal_sys: Critical temperature reached(206 C),shutting down
[    5.128997] Failed to start orderly shutdown: forcing the issue
[    5.135495] Emergency Sync complete

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: quark: Lock HMBOUND register before jumping to kernel
Bin Meng [Thu, 10 Sep 2015 06:20:26 +0000 (23:20 -0700)]
x86: quark: Lock HMBOUND register before jumping to kernel

When Linux kernel boots, it hangs at:

[    0.829408] Intel Quark side-band driver registered

This happens when Quark kernel Isolated Memory Region (IMR) driver
tries to lock an IMR register to protect kernel's text and rodata
sections. However in order to have IMR function correctly, HMBOUND
register must be locked otherwise the system just hangs.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: quark: Convert to use clrbits, setbits, clrsetbits macros
Bin Meng [Thu, 10 Sep 2015 06:20:25 +0000 (23:20 -0700)]
x86: quark: Convert to use clrbits, setbits, clrsetbits macros

Change existing codes to use clrbits, setbits, clrsetbits macros.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: quark: Add clrbits, setbits, clrsetbits macros for message port access
Bin Meng [Thu, 10 Sep 2015 06:20:24 +0000 (23:20 -0700)]
x86: quark: Add clrbits, setbits, clrsetbits macros for message port access

On Intel Quark, lots of registers on the message port need be
programmed. Add handy clrbits, setbits, clrsetbits macros for
message port access.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agox86: galileo: Enable random mac address for Quark
Bin Meng [Thu, 10 Sep 2015 06:20:23 +0000 (23:20 -0700)]
x86: galileo: Enable random mac address for Quark

Not like other Intel Ethernet controllers (e.g.: E1000), Intel Quark
SoC integrated designware Ethernet controller does not have a chipset
defined way to store/restore mac address. Enable random mac address
so that we can use Ethernet even without 'ethaddr'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: quark: Add PCIe/USB static register programming after memory init
Bin Meng [Fri, 11 Sep 2015 10:24:37 +0000 (03:24 -0700)]
x86: quark: Add PCIe/USB static register programming after memory init

This adds static register programming for PCIe and USB after memory
init as required by Quark firmware writer guide. Although not doing
this did not cause any malfunction, just do it for safety.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Convert to use driver model eth on quark/galileo
Bin Meng [Fri, 11 Sep 2015 10:24:36 +0000 (03:24 -0700)]
x86: Convert to use driver model eth on quark/galileo

Convert to use DM version of Designware ethernet driver on Intel
quark/galileo.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agonet: designware: Add support to PCI designware devices
Bin Meng [Fri, 11 Sep 2015 10:24:35 +0000 (03:24 -0700)]
net: designware: Add support to PCI designware devices

The Designware ethernet controller is also seen on PCI bus, e.g.
on Intel Quark SoC. Add this support in the DM version driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodm: pci: Add an inline API to test if a device is on a PCI bus
Bin Meng [Fri, 11 Sep 2015 10:24:34 +0000 (03:24 -0700)]
dm: pci: Add an inline API to test if a device is on a PCI bus

Introduce device_is_on_pci_bus() which can be utilized by driver
to test if a device is on a PCI bus.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodts: do not cut down pinctrl-0 and pinctrl-names for SPL full-pinctrl
Masahiro Yamada [Mon, 31 Aug 2015 10:36:24 +0000 (19:36 +0900)]
dts: do not cut down pinctrl-0 and pinctrl-names for SPL full-pinctrl

These properties are necessary to use full-featured pinctrl drivers
in SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoARM: tegra114: Clear IDDQ when enabling PLLC
Thierry Reding [Tue, 8 Sep 2015 09:38:04 +0000 (11:38 +0200)]
ARM: tegra114: Clear IDDQ when enabling PLLC

Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra124: Clear IDDQ when enabling PLLC
Thierry Reding [Tue, 8 Sep 2015 09:38:03 +0000 (11:38 +0200)]
ARM: tegra124: Clear IDDQ when enabling PLLC

Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").

Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Add Tegra20 SPI device nodes
Mirza Krak [Wed, 19 Aug 2015 11:50:50 +0000 (13:50 +0200)]
ARM: tegra: Add Tegra20 SPI device nodes

Add the device tree node for the SPI controllers found on Tegra20 SOCs.

Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agop2571: Remove hard-coded counter frequency
Thierry Reding [Thu, 20 Aug 2015 09:42:23 +0000 (11:42 +0200)]
p2571: Remove hard-coded counter frequency

The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agop2371: Remove hard-coded counter frequency
Thierry Reding [Thu, 20 Aug 2015 09:42:22 +0000 (11:42 +0200)]
p2371: Remove hard-coded counter frequency

The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoe2220-1170: Remove hard-coded counter frequency
Thierry Reding [Thu, 20 Aug 2015 09:42:21 +0000 (11:42 +0200)]
e2220-1170: Remove hard-coded counter frequency

The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: clk_m is the architected timer source clock
Thierry Reding [Thu, 20 Aug 2015 09:42:20 +0000 (11:42 +0200)]
ARM: tegra: clk_m is the architected timer source clock

While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies. clk_m will be divided down
from the oscillator.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Implement clk_m
Thierry Reding [Thu, 20 Aug 2015 09:42:19 +0000 (11:42 +0200)]
ARM: tegra: Implement clk_m

On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoarmv8: Make COUNTER_FREQUENCY optional
Thierry Reding [Thu, 20 Aug 2015 09:42:18 +0000 (11:42 +0200)]
armv8: Make COUNTER_FREQUENCY optional

Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: replace V_PROMPT define with kconfig
Stephen Warren [Thu, 20 Aug 2015 23:38:42 +0000 (17:38 -0600)]
ARM: tegra: replace V_PROMPT define with kconfig

Commit 181bd9dc61d2 "kconfig: add config option for shell prompt" replaced
define V_PROMPT with Kconfig option SYS_PROMPT. This crossed with patches
adding Tegra T210 boards. Migrate the boards to the new scheme.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: fix PLLP frequency calc on T210
Stephen Warren [Wed, 19 Aug 2015 23:03:59 +0000 (17:03 -0600)]
ARM: tegra: fix PLLP frequency calc on T210

AFAIK, for all PLLs on all Tegra SoCs, the primary PLL output frequency
is (input * m) / (n * p). However, PLLP's primary output (pllP_out0) on
T210 is the VCO output, and divp is not applied. pllP_out2 does have divp
applied. All other pllP_outN are divided down from pllP_out0. We only
support pllP_out0 in U-Boot at the time of writing.

Fix clock_get_rate() to handle this special case.

This corrects the returned rate for PLLP to be 408MHz rather than 204MHz.
In turn, this causes high enough dividers to be calculated for the various
peripheral clocks that feed off of PLLP. Without this, some peripherals
failed to operate correctly. For instance, one of my SD cards worked
perfectly but an older (presumably slower) card could not be read.

Note that prior to commit 722e000ccd72 "Tegra: PLL: use per-SoC pllinfo
table instead of PLL_DIVM/N/P, etc.", the calculated PLL frequency was
816MHz since the wrong values were being extracted from the PLLP divider
register. This caused overly large peripheral dividers to be calculated,
which while wrong, didn't cause any correctness issues; things simply ran
slower than they could.

Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: fix COUNTER_FREQUENCY for T210
Stephen Warren [Wed, 19 Aug 2015 21:15:41 +0000 (15:15 -0600)]
ARM: tegra: fix COUNTER_FREQUENCY for T210

While T210 boards all have 38.4MHz crystals, per the TRM, the only
supported configuration is to divide the crystal frequency by 2 to
generate clk_m, which is what feeds the ARM generic timers amongst other
things. Fix the value of COUNTER_FREQUENCY to reflect this divide-by-2.

When I queried the 19.2 value in Tom's original T210 patches, I wasn't
aware of this extra divide-by-2, and didn't notice any effect from the
incorrect value, since its only used if U-Boot is booted in EL3, whereas
I'm booting it in EL2.

Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agotegra: Remove tegra_spl_gpio_direction_output declaration from header file
Axel Lin [Wed, 11 Mar 2015 07:16:29 +0000 (15:16 +0800)]
tegra: Remove tegra_spl_gpio_direction_output declaration from header file

This function is deleted by commit 2fccd2d96bad
"tegra: Convert tegra GPIO driver to use driver model".

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoARM: tegra: Add p2371-2180 board
Stephen Warren [Fri, 14 Aug 2015 04:34:22 +0000 (22:34 -0600)]
ARM: tegra: Add p2371-2180 board

P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and
two GPIO expansion headers.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
9 years agoMerge git://git.denx.de/u-boot-fdt
Tom Rini [Wed, 16 Sep 2015 13:53:37 +0000 (09:53 -0400)]
Merge git://git.denx.de/u-boot-fdt

9 years agokbuild: fixdep: drop meaningless hash table initialization
Masahiro Yamada [Tue, 15 Sep 2015 03:54:38 +0000 (12:54 +0900)]
kbuild: fixdep: drop meaningless hash table initialization

The clear_config() is called just once at the beginning of this
program, but the global variable hashtab[] is already zero-filled
at the start-up.

[ Linux commit: d179e22762fd38414c4108acedd5feca4cf7e0d8 ]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
9 years agoapi_storage: Fix non-first storage device enumeration
Andreas Färber [Mon, 14 Sep 2015 10:21:34 +0000 (12:21 +0200)]
api_storage: Fix non-first storage device enumeration

When enabling CONFIG_API and chain-loading GRUB2 on jetson-tk1, only the
eMMC would show up as (hd0), but not the SD card, leading to GRUB not
finding its configuration and modules, falling back to a rescue shell.

This is because enum_ended would get set for !more after returning a
cookie for the first MMC device in group 3.

Fix this by properly setting the "more" argument also in the case of the
first storage device of a group.

Signed-off-by: Andreas Färber <afaerber@suse.de>
9 years agoarm: Remove unused reference to nomadik
Stefan Roese [Mon, 14 Sep 2015 07:32:55 +0000 (09:32 +0200)]
arm: Remove unused reference to nomadik

Commit 0abdd9d0 "arm: Remove nhk8815 boards and nomadik arch" missed one
reference to this arch. Lets remove this as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
9 years agoarm: Remove unused ST-Ericsson u8500 arch
Stefan Roese [Mon, 14 Sep 2015 07:17:36 +0000 (09:17 +0200)]
arm: Remove unused ST-Ericsson u8500 arch

This arch does not seem to be supported / used at all in the current
U-Boot mainline source tree any more. So lets remove the core u8500 code
and code that was only referenced by this platform.

Please note that this patch also removes these config options:

- CONFIG_PL011_SERIAL_RLCR
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT

As they only seem to be referenced by u8500 based boards. Without any
such board in the current code, these config option don't make sense
any more. Lets remove them as well.

If someone still wants to use this platform, then please send patches
to re-enable support by adding at least one board that references this
code.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
9 years agomtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc()
Stefan Roese [Mon, 14 Sep 2015 06:47:47 +0000 (08:47 +0200)]
mtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc()

This patch addresses some comments raised by Scott in the last versions.
Here the changes in detail:

- Removed __maybe_unused as its not needed
- Added check for strength == 4 and error out for the unsupported
  ECC strength values
- Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this
  will be done in nand_scan_tail()
- Set .caclulate back to fsmc_read_hwecc() in the HW case
- Added comment that this function will only be called on SPEAr platforms,
  not supporting the BCH8 HW ECC (FSMC_VER8)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Scott Wood <scottwood@freescale.com>
9 years agoenv: import: hashtable: Free memory allocated before exiting from himport_r()
Lukasz Majewski [Sun, 13 Sep 2015 22:57:04 +0000 (00:57 +0200)]
env: import: hashtable: Free memory allocated before exiting from himport_r()

ithout this patch memory is not released on early exit.

Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
9 years agoenv: import: hashtable: Prevent buffer overrun when importing environment from file
Lukasz Majewski [Sun, 13 Sep 2015 22:57:03 +0000 (00:57 +0200)]
env: import: hashtable: Prevent buffer overrun when importing environment from file

Lets consider following scenario:
- One uses echo -n "key=value" to define environment variable in a file (single variable)
- The file content is "key=value" without any terminating byte (e.g. 0x0a or
0x0d).
- The file is loaded to u-boot non zero'ed RAM buffer (with load command).
- Then "env import -t -r $loadaddr $filesize" is executed.
- Due to lack of proper termination byte we have classical example of buffer
  overrun.

This patch prevents from this by allocating one extra byte than size and
explicitly null terminate it.

There should be no change for normal env import operation after applying
this patch.

Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
9 years agocli_simple.c: fix possible overflow when copying the string
Imran Zaman [Mon, 7 Sep 2015 08:24:08 +0000 (11:24 +0300)]
cli_simple.c: fix possible overflow when copying the string

Bigger source buffer than dest buffer could overflow when copying
strings.  Source and destination buffer sizes are same now.

Signed-off-by: Imran Zaman <imran.zaman@intel.com>
9 years agoti816x: Switch to SYS_GENERIC_BOARD
Tom Rini [Thu, 3 Sep 2015 18:54:04 +0000 (14:54 -0400)]
ti816x: Switch to SYS_GENERIC_BOARD

Tested on my TI186x rev E. (PG2.0) and take over maintainership.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agoti814x_evm: Switch to SYS_GENERIC_BOARD
Tom Rini [Thu, 3 Sep 2015 18:54:03 +0000 (14:54 -0400)]
ti814x_evm: Switch to SYS_GENERIC_BOARD

Take over maintainership as well.  Not tested as PG2.0 (which I have)
needs additional work over PG1.0 (which Matt has).

Cc: Matt Porter <mporter@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agoomap3_evm_common.h: Switch to SYS_GENERIC_BOARD
Tom Rini [Thu, 3 Sep 2015 18:54:02 +0000 (14:54 -0400)]
omap3_evm_common.h: Switch to SYS_GENERIC_BOARD

Tested on my OMAP3 uEVM.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agofdt: add new fdt address parsing functions
Stephen Warren [Thu, 6 Aug 2015 21:31:02 +0000 (15:31 -0600)]
fdt: add new fdt address parsing functions

fdtdec_get_addr_size() hard-codes the number of cells used to represent
an address or size in DT. This is incorrect in many cases depending on
the DT binding for a particular node or property (e.g. it is incorrect
for the "reg" property). In most cases, DT parsing code must use the
properties #address-cells and #size-cells to parse addres properties.

This change splits up the implementation of fdtdec_get_addr_size() so
that the core logic can be used for both hard-coded and non-hard-coded
cases. Various wrapper functions are implemented that support cases
where hard-coded cell counts should or should not be used, and where
the client does and doesn't know the parent node ID that contains the
properties #address-cells and #size-cells.

dev_get_addr() is updated to use the new functions.

Core functionality in fdtdec_get_addr_size_fixed() is widely tested via
fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and
dev_get_addr() by manually modifying the Tegra I2C driver to invoke them.

Much of the core implementation of fdtdec_get_addr_size_fixed(),
fdtdec_get_addr_size_auto_parent(), and
fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's
previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit".

Based-on-work-by: Thierry Reding <treding@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Dropped #define DEBUG at the top of fdtdec.c:
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'rmobile' of git://git.denx.de/u-boot-sh
Tom Rini [Sun, 13 Sep 2015 21:25:16 +0000 (17:25 -0400)]
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

9 years agoARM: Kirkwood: fix IDE configuration on LaCie boards
Simon Guinot [Thu, 3 Sep 2015 09:12:20 +0000 (11:12 +0200)]
ARM: Kirkwood: fix IDE configuration on LaCie boards

On the LaCie boards netspace_max_v2 and net2big_v2, two internal hard
drives are available. Additionally on the d2net_v2 board, an extra hard
drive can be plugged via eSATA.

This patch updates CONFIG_SYS_IDE_MAXBUS and CONFIG_SYS_IDE_MAXDEVICE
accordingly for this boards.

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
9 years agoarm: move edb93xx to generic board architecture
Sergey Kostanbaev [Wed, 9 Sep 2015 22:40:01 +0000 (01:40 +0300)]
arm: move edb93xx to generic board architecture

Use CONFIG_SYS_GENERIC_BOARD in EDB93XX board family

9 years agoARM: Kirkwood: enable generic board support for LaCie boards
Simon Guinot [Tue, 1 Sep 2015 17:01:02 +0000 (19:01 +0200)]
ARM: Kirkwood: enable generic board support for LaCie boards

This patch enables generic board support for the following
Kirkwood-based LaCie boards:

- Network Space v2 (Mini, Lite and Max).
- Internet Space v2.
- D2 Network v2.
- 2Big Network v2.

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agoudoo: Fix the error handling in board_eth_init()
Fabio Estevam [Fri, 11 Sep 2015 16:32:50 +0000 (13:32 -0300)]
udoo: Fix the error handling in board_eth_init()

We should not return 0 on failure, so return a negative error code
instead.

Also centralize the error path so that is easier to follow.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agotqma6_mba6: Fix the error handling in board_eth_init()
Fabio Estevam [Fri, 11 Sep 2015 16:32:49 +0000 (13:32 -0300)]
tqma6_mba6: Fix the error handling in board_eth_init()

We should not return 0 on failure, so return a negative error code
instead.

Also centralize the error path so that is easier to follow.

Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoot1200: Fix the error handling in board_eth_init()
Fabio Estevam [Fri, 11 Sep 2015 03:53:52 +0000 (00:53 -0300)]
ot1200: Fix the error handling in board_eth_init()

We should not return 0 on failure, so return a negative error code
instead.

Also centralize the error path so that is easier to follow.

Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agonitrogen6x: Fix the error handling in board_eth_init()
Fabio Estevam [Fri, 11 Sep 2015 03:53:51 +0000 (00:53 -0300)]
nitrogen6x: Fix the error handling in board_eth_init()

We should not return 0 on failure, so return a negative error code
instead.

Also centralize the error path so that is easier to follow.

Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
9 years agopcie_imx: Use 'ms' for milliseconds
Fabio Estevam [Thu, 10 Sep 2015 23:45:25 +0000 (20:45 -0300)]
pcie_imx: Use 'ms' for milliseconds

milliseconds should be written as 'ms' instead of 'mS'.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Marek Vasut <marex@denx.de>
9 years agomx6ul_14x14_evk: Use the default CONFIG_SYS_PBSIZE
Fabio Estevam [Wed, 9 Sep 2015 14:16:44 +0000 (11:16 -0300)]
mx6ul_14x14_evk: Use the default CONFIG_SYS_PBSIZE

Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into
the console and hitting enter afterwards, causes a hang in the system because
CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error
message:
"Unknown command '' - try 'help'".

Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve
this problem.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agomx6ul_14x14_evk: Remove CONFIG_FEC_DMA_MINALIGN
Fabio Estevam [Wed, 9 Sep 2015 14:16:43 +0000 (11:16 -0300)]
mx6ul_14x14_evk: Remove CONFIG_FEC_DMA_MINALIGN

CONFIG_FEC_DMA_MINALIGN is not used anywhere, so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Peng Fan <Peng.Fan@freescale.com>
9 years agomx6ul_14x14_evk: Do not undef config options
Fabio Estevam [Wed, 9 Sep 2015 14:16:42 +0000 (11:16 -0300)]
mx6ul_14x14_evk: Do not undef config options

There is no need to undef the config options.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Peng Fan <Peng.Fan@freescale.com>
9 years agomx6ul_14x14_evk: Remove unused config option
Fabio Estevam [Wed, 9 Sep 2015 14:16:41 +0000 (11:16 -0300)]
mx6ul_14x14_evk: Remove unused config option

CONFIG_ROM_UNIFIED_SECTIONS is not used anywhere, so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Peng Fan <Peng.Fan@freescale.com>
9 years agomx6ul_14x14_evk: Remove CONFIG_SYS_GENERIC_BOARD
Fabio Estevam [Wed, 9 Sep 2015 14:16:40 +0000 (11:16 -0300)]
mx6ul_14x14_evk: Remove CONFIG_SYS_GENERIC_BOARD

CONFIG_SYS_GENERIC_BOARD is selected by mx6_common.h, so there is no
need to define it locally.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Peng Fan <Peng.Fan@freescale.com>
9 years agocgtqmx6eval: Remove CONFIG_CMD_FUSE option
Fabio Estevam [Wed, 9 Sep 2015 14:16:39 +0000 (11:16 -0300)]
cgtqmx6eval: Remove CONFIG_CMD_FUSE option

CONFIG_CMD_FUSE and CONFIG_MXC_OCOTP are selected by mx6_common.h,
so there is no need to define them locally.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agomx6sxsabresd: Remove CONFIG_SPL_FAT_SUPPORT
Fabio Estevam [Tue, 8 Sep 2015 17:50:24 +0000 (14:50 -0300)]
mx6sxsabresd: Remove CONFIG_SPL_FAT_SUPPORT

If the SD card does not contain the u-boot.img then we get the
following error:

U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29)
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1

Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the
job.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agomx6slevk: Remove CONFIG_SPL_FAT_SUPPORT
Fabio Estevam [Tue, 8 Sep 2015 17:50:23 +0000 (14:50 -0300)]
mx6slevk: Remove CONFIG_SPL_FAT_SUPPORT

If the SD card does not contain the u-boot.img then we get the
following error:

U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29)
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1

Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the
job.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agomx6ul_14x14_evk: Add a README file
Fabio Estevam [Tue, 8 Sep 2015 17:43:12 +0000 (14:43 -0300)]
mx6ul_14x14_evk: Add a README file

Add a README file to help users getting started with the board.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agomx6ul_14x14_evk: Remove CONFIG_SPL_FAT_SUPPORT
Fabio Estevam [Tue, 8 Sep 2015 17:43:11 +0000 (14:43 -0300)]
mx6ul_14x14_evk: Remove CONFIG_SPL_FAT_SUPPORT

If the SD card does not contain the u-boot.img then we get the
following error:

U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29)
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1

Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the
job.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoimx-common: cpu: Do not print on invalid temperature
Fabio Estevam [Tue, 8 Sep 2015 17:43:10 +0000 (14:43 -0300)]
imx-common: cpu: Do not print on invalid temperature

It is not very useful to have the message below on every boot
(especially when we are using early silicon):

U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device

, so turn the error message into debug level.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agothermal: imx_thermal: Do not print on error
Fabio Estevam [Tue, 8 Sep 2015 17:43:09 +0000 (14:43 -0300)]
thermal: imx_thermal: Do not print on error

It is not very useful to have the message below on every boot
(especially when we are using early silicon):

U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device

, so turn the error message into debug level.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
9 years agoimx: mx6 discard 'select CPU_V7' for different targets
Peng Fan [Mon, 7 Sep 2015 06:59:49 +0000 (14:59 +0800)]
imx: mx6 discard 'select CPU_V7' for different targets

Discard the 'select CPU_V7' from Kconfig in arch/arm/cpu/armv7/mx6
for different targets, because ARCH_MX6 selects CPU_V7.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
9 years agomx6: remove SYS_SOC from board Kconfig
Peng Fan [Mon, 7 Sep 2015 06:59:48 +0000 (14:59 +0800)]
mx6: remove SYS_SOC from board Kconfig

Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: "Eric BĂ©nard" <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoarm: mx6: cm-fx6: modify device tree for old revisions of utilite
Nikita Kiryanov [Sun, 6 Sep 2015 08:48:38 +0000 (11:48 +0300)]
arm: mx6: cm-fx6: modify device tree for old revisions of utilite

Old revisions of Utilite (a miniature PC based on cm-fx6) do not have
a card detect for mmc, and thus the kernel needs to be told that
there's a persistent storage on usdhc3 to force it to probe the mmc
card.

Check the baseboard revision and modify the device tree accordingly
if needed.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agocompulab: eeprom: add support for obtaining product name
Nikita Kiryanov [Sun, 6 Sep 2015 08:48:37 +0000 (11:48 +0300)]
compulab: eeprom: add support for obtaining product name

Introduce cl_eeprom_get_product_name() for obtaining product name
from the eeprom.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agocompulab: eeprom: propagate error value in read_mac_addr()
Nikita Kiryanov [Sun, 6 Sep 2015 08:48:36 +0000 (11:48 +0300)]
compulab: eeprom: propagate error value in read_mac_addr()

cl_eeprom_read_mac_addr() doesn't differentiate between success case and
inability to access eeprom. Fix this by propagating the return value of
cl_eeprom_setup().

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agocompulab: eeprom: select i2c bus when querying for board rev
Nikita Kiryanov [Sun, 6 Sep 2015 08:48:35 +0000 (11:48 +0300)]
compulab: eeprom: select i2c bus when querying for board rev

Add support for selecting which eeprom is queried for board revision by
extending cl_eeprom_get_board_rev() to accept an i2c bus number.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agoimx: mx6ul: support mx6ul 9x9 evk board
Peng Fan [Sun, 6 Sep 2015 07:02:34 +0000 (15:02 +0800)]
imx: mx6ul: support mx6ul 9x9 evk board

This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk,
the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are:
1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC.
2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk
   supports 512MB DDR3
3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package.

This patch add the following:
1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size()
2. Introduce a macro is_mx6ul_9x9_evk using
   CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL
   part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work,
   so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with
   mx6ul_14x14_evk. And we have no way to dymaically checking this chip
   is 9x9 or 14x14.
3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations.
   POWER related configurations also effect for mx6ul_14x14_evk. But
   power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to
   do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk.
4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM
   configurations.
5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file
   according to board_rev and board_name.
6. Add TARGET_MX6UL_9X9_EVK Kconfig entry

Boot Log:
U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53)
reading u-boot.img
reading u-boot.img

U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 41C
Reset cause: POR
Board: MX6UL 9x9 EVK
I2C:   ready
DRAM:  256 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:   FEC1
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
9 years agoimx: discard duplicated MXC_OCOTP and CMD_FUSE
Peng Fan [Tue, 1 Sep 2015 03:03:15 +0000 (11:03 +0800)]
imx: discard duplicated MXC_OCOTP and CMD_FUSE

We have CONFIG_MXC_OCOTP and CONFIG_CMD_FUSE in mx6_common.h,
discard duplicated macro definitions in board header files.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
9 years agoRevert "imx: mx6: ddr correct tRFC and tXS"
Peng Fan [Tue, 1 Sep 2015 03:03:14 +0000 (11:03 +0800)]
Revert "imx: mx6: ddr correct tRFC and tXS"

This reverts commit 059323fb6a8f21637bb617919715c2427f24777c.

This commit 059323fb6a8f21637bb617919715c2427f24777c use JESD79-3E which
is not the newest spec. Should use JESD79-3F in which tRFC is 260ns for
4Gb chip.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
9 years agomxs: mxsboot: fix endianess for sd boot images
Michael Heimpold [Tue, 1 Sep 2015 21:58:44 +0000 (23:58 +0200)]
mxs: mxsboot: fix endianess for sd boot images

Running mxsboot on a big-endian system produces a sd image which
cannot be started by the i.MX28 ROM. It complains on the debug
uart as following:
0x8020a009
          0x80502008
0x8020a009
          0x80502008
...

Enforcing all fields within the BCB to little-endian make
the image bootable again.

Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoimx: mx7dsabresd: Add support for MX7D SABRESD board
Adrian Alonso [Thu, 3 Sep 2015 16:49:28 +0000 (11:49 -0500)]
imx: mx7dsabresd: Add support for MX7D SABRESD board

* Add i.MX7D SABRESD target board support with enabled modules:
  UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX.

  Build target: mx7dsabresd_config

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
9 years agoimx: imx7d: add imx-common cpu support for imx7d
Adrian Alonso [Wed, 2 Sep 2015 18:54:23 +0000 (13:54 -0500)]
imx: imx7d: add imx-common cpu support for imx7d

Add imx-common cpu support for imx7d SoC
- Update reset_cause for imx7d
- Enable watchdog driver built for imx7d

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agothermal: imx: add imx7d soc thermal support
Adrian Alonso [Wed, 2 Sep 2015 18:54:22 +0000 (13:54 -0500)]
thermal: imx: add imx7d soc thermal support

Add imx7 SoC thermal driver support

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
9 years agoarm: imx-common: init: rework wdog settings for imx6/imx7
Adrian Alonso [Wed, 2 Sep 2015 18:54:21 +0000 (13:54 -0500)]
arm: imx-common: init: rework wdog settings for imx6/imx7

Rework imx_set_wdog_powerdown to be reused by imx6 and imx7

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
9 years agoarm: imx-common: init: extend init_aips to support imx7
Adrian Alonso [Wed, 2 Sep 2015 18:54:20 +0000 (13:54 -0500)]
arm: imx-common: init: extend init_aips to support imx7

Extend init_aips to support imx7 SoC, use is_soc_type
and is_cpu_type to resolve at run time aips3 settings

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
9 years agoimx: imx7d: Add SoC system support
Adrian Alonso [Wed, 2 Sep 2015 18:54:19 +0000 (13:54 -0500)]
imx: imx7d: Add SoC system support

Add imx7d basic SoC system support
Misc arch dependent functions for system bring up

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agoimx: imx7d: clock control module support
Adrian Alonso [Wed, 2 Sep 2015 18:54:18 +0000 (13:54 -0500)]
imx: imx7d: clock control module support

* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
  root frequency generation denominated clock slices.
  Core clock slice: hihg speed clock for ARM core
  Bus clock slice: for bus clocks
  IP clock slice: Peripheral clocks
* At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
  In u-boot, we have to:
  - Configure PFD3- PFD7 for freq we needed in u-boot
  - Set clock root for peripherals (ip channel)

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agoimx: imx7d: initial arch level support
Adrian Alonso [Wed, 2 Sep 2015 18:54:17 +0000 (13:54 -0500)]
imx: imx7d: initial arch level support

* Add system arch level header files
  - imx-regs.h: iMX7D SoC system architecture registers
  - crm_regs.h: Clock control module registers
  - sys_proto.h: helper callback function for SoC setup

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
9 years agoimx: system counter driver for imx7d and mx6ul
Adrian Alonso [Wed, 2 Sep 2015 18:54:16 +0000 (13:54 -0500)]
imx: system counter driver for imx7d and mx6ul

Add system counter driver for imx7d and mx6ul
imx7 and imx6ul supports system counter timer as well as
GPT timer (arch/arm/imx-common/timer.c); The default for
imx7 is systemcounter timer.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
9 years agoarm: imx: imx-common: init: move arch init common setup
Adrian Alonso [Wed, 2 Sep 2015 18:54:15 +0000 (13:54 -0500)]
arm: imx: imx-common: init: move arch init common setup

Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
9 years agoarm: imx: common rework cache settings for imx6
Adrian Alonso [Wed, 2 Sep 2015 18:54:14 +0000 (13:54 -0500)]
arm: imx: common rework cache settings for imx6

Rework cache settings for imx6, move cache configuration
to imx-common/cache.c so it can be reused for newer SoC

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
9 years agothermal: imx_thermal: rework driver to be reused
Adrian Alonso [Wed, 2 Sep 2015 18:54:13 +0000 (13:54 -0500)]
thermal: imx_thermal: rework driver to be reused

Rework imx_thermal driver to be used across i.MX
processor that support thermal sensor

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
9 years agoimx: arch-mx6: add is_soc_type helper macro
Adrian Alonso [Wed, 2 Sep 2015 18:54:12 +0000 (13:54 -0500)]
imx: arch-mx6: add is_soc_type helper macro

Add helper macro is_soc_type to identify iMX SoC family

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
9 years agoMerge git://git.denx.de/u-boot-usb
Tom Rini [Sat, 12 Sep 2015 19:50:02 +0000 (15:50 -0400)]
Merge git://git.denx.de/u-boot-usb

9 years agoarm: socfpga: mcvevk: Update DRAM clock to 400MHz
Marek Vasut [Tue, 8 Sep 2015 17:51:05 +0000 (19:51 +0200)]
arm: socfpga: mcvevk: Update DRAM clock to 400MHz

The MCV SoM has DDR3-1600 DRAMs on it, update the DRAM speed
to 400MHz to make use of these DRAMs completely.

Signed-off-by: Marek Vasut <marex@denx.de>
9 years agousb: ci_udc: fix emissions of ZLPs
Stephen Warren [Fri, 11 Sep 2015 23:10:02 +0000 (17:10 -0600)]
usb: ci_udc: fix emissions of ZLPs

Commit 6a132416359e "ci_udc: Update the ci_udc driver to support bulk
transfers" caused the value of "len" to change without updating subsquent
users of that variable in ci_ep_submit_next_request(). This caused the
code that detects when to emit ZLPs (Zero Length Packets) never to
trigger, which in turn caused host timeouts when a ZLP was required,
which in turn broke tests/dfu/, even despite the assertion in that
commit's description that "These changes are tested for both the DFU and
lthor."

Fix this by modifying the added dtd iteration code not to modify "len",
but rather to keep state in a separate variable. Rename the variables
while we're at it so they describe their purpose better.

Fixes: 6a132416359e ("ci_udc: Update the ci_udc driver to support bulk transfers")
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>