Masahiro Yamada [Fri, 27 Jan 2017 21:53:42 +0000 (06:53 +0900)]
ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoC
The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB
memory footprint, which is significant in SPL.
There are PHY parameters for 5 boards, but they are actually not
board specific, but SoC specific. After all, we just need to have
2 patterns, for LD20 and LD21. Also, the shift values are small
enough to become "short" type instead of "int". This change will
save about 3 KB memory footprint.
Scott Wood [Thu, 26 Jan 2017 22:55:44 +0000 (16:55 -0600)]
booti: Set images.os.arch
Commit ec6617c39741adc6c549 ("armv8: Support loading 32-bit OS in AArch32
execution state") broke SMP boot by assuming that an image is 32-bit if
the arch field in the spin table != IH_ARCH_DEFAULT (i.e.
IH_ARCH_ARM64), even if the arch field also does not match IH_ARCH_ARM,
even though nothing actually set the arch field in the spin table.
Commit e2c18e40b111470f ("armv8: fsl-layerscape: SMP support for loading
32-bit OS") fixed this for bootm by setting the arch field of the spin
table based on images.os.arch, but booti remaineed broken because it did
not set images.os.arch.
Fixes: ec6617c39741adc6c549 ("armv8: Support loading 32-bit OS in AArch32 execution state") Fixes: e2c18e40b111 ("armv8: fsl-layerscape: SMP support for loading 32-bit OS") Cc: Alison Wang <alison.wang@nxp.com> Cc: Chenhui Zhao <chenhui.zhao@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Stuart Yoder <stuart.yoder@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com>
Stefan Brüns [Thu, 26 Jan 2017 20:22:36 +0000 (20:22 +0000)]
fs/fat: Fix unaligned __u16 reads for FAT12 access
Doing unaligned reads is not supported on all architectures, use
byte sized reads of the little endian buffer.
Rename off16 to off8, as it reflects the buffer offset in byte
granularity (offset is in entry, i.e. 12 bit, granularity).
Fix a regression introduced in 8d48c92b45aea91e2a2be90f2ed93677e85526f1
Alexey Brodkin [Thu, 26 Jan 2017 14:25:59 +0000 (17:25 +0300)]
buildman: Update link to the most recent prebuilt ARC toolachin
To troubleshoot unexpected bhavior during building and what's more
important during execution it is strongly recommended to use recent
ARC toolchain, and so we're now referring to arc-2016.09 which is the
latest as of today.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Michael Kurz [Sun, 22 Jan 2017 15:04:29 +0000 (16:04 +0100)]
ARM: stm32: enable support for smsc phy on stm32f746-disco board
This patch enables support for the smsc phy on the
stm32f746-disco board.
Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Series-changes 3:
- Add Acked-by tag to 'enable support for smsc phy on...'
Michael Kurz [Sun, 22 Jan 2017 15:04:26 +0000 (16:04 +0100)]
ARM: stm32: use clock setup function defined in clock.c
Use the clock setup function defined in clock.c instead of setting the
clock bits directly in the drivers.
Remove register definitions of RCC in rcc.h as these are already
defined in the struct in stm32.h
Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Michael Kurz [Sun, 22 Jan 2017 15:04:22 +0000 (16:04 +0100)]
ARM: DTS: stm32: add stm32f746 device tree pin control files
This patch adds pin control definitions for use in device tree files
The definitions are based on the stm32f746 files from current
linux kernel "include/dt-bindings/pinctrl/stm32f746-pinfunc.h".
Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Adam Ford [Fri, 20 Jan 2017 13:03:52 +0000 (14:03 +0100)]
arm: omap3: Update cpuinfo for DM3730, DM3725, AM3715, and AM3703
The check for OMAP3630/3730 only checks for 800MHz 3630/3730, but
anything else is lumped into 36XX/37XX with an assumed 1GHz speed.
Based on the DM3730 TRM bit 9 shows the MPU Frequency (800MHz/1GHZ).
This also adds the ability to distinguish between the DM3730, DM3725,
AM3715, and AM3703 and correctly display their maximum speed.
Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
There is misunderstanding in commit 8c36e99f2111 ("armv8: release
slave cores from CPU_RELEASE_ADDR"). How to bring the slave cores
into U-Boot proper is platform-specific. So, it should be cared
in SoC/board files instead of common/spl/spl.c. As you see SPL
is the acronym of Secondary Program Loader, there is generally
something that runs before SPL (the First one is usually Boot ROM).
How to wake up slave cores from the Boot ROM is really SoC specific.
So, the intention for the spin table support is to bring the slave
cores into U-Boot proper in an SoC specific manner. (this must be
done after relocation. see below.)
If you bring the slaves into SPL, it is SoC own code responsibility
to transfer them to U-Boot proper. The Spin Table defines the
interface between a boot-loader and Linux kernel. It is unrelated
to the interface between SPL and U-Boot proper.
One more thing is missing in the commit; spl_image->entry_point
points to the entry address of U-Boot *before* relocation. U-Boot
relocates itself between board_init_f() and board_init_r(). This
means the master CPU sees the different copy of the spin code than
the slave CPUs enter. The spin_table_update_dt() protects the code
*after* relocation. As a result, the slave CPUs spin in unprotected
code, which leads to unstable behavior.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Masahiro Yamada [Fri, 20 Jan 2017 09:04:43 +0000 (18:04 +0900)]
arm64: spin-table: add more information in Kconfig help
This feature seems to be sometimes misunderstood. The intention is:
[1] Bring the slaves into the U-Boot proper image, not SPL (unless
you have a special reason to do otherwise).
[2] The operation must be done in a board (SoC) specific manner
since how to wake the slaves from the Boot ROM is SoC specific.
[3] The slaves must enter U-Boot proper after U-Boot relocates
itself because the "cpu-release-addr" property points to the
relocated memory area.
[2] is already explained in the help. We can make [1] even clearer
by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing,
so I am adding it to the list. Instead, "before the master CPU
jumps to the kernel" is a matter of course, so removed.
Marcin Niestroj [Wed, 25 Jan 2017 08:53:07 +0000 (09:53 +0100)]
ARM: am335x: Add support for chiliSOM
chiliSOM is a System On Module (http://http://grinn-global.com/chilisom/).
It can't exists on its own, but will be used as part of other boards.
Hardware specification:
* TI AM335x processor
* 128M, 256M or 512M DDR3 memory
* up to 256M NAND
We place source inside arch/arm/mach-omap2/ directory and make it
possible to reuse initialization code (i.e. DDR, NAND init) for all
boards that use it.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Fri, 27 Jan 2017 16:39:20 +0000 (10:39 -0600)]
defconfig: Add a config for AM335x High Security EVM
Add a new defconfig file for the AM335x High Security EVM. This config
is specific for the case of memory device booting. Memory device booting
is handled separatly from peripheral booting on HS devices as the load
address changes.
This defconfig is the same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_ISW_ENTRY_ADDR updated for secure images.
CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_USE_TINY_PRINTF option set to 'y' to reduce SPL size
CONFIG_SPL_SYS_MALLOC_SIMPLE set to 'y' to reduce SPL size
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew F. Davis [Fri, 27 Jan 2017 16:39:19 +0000 (10:39 -0600)]
spl: Remove overwrite of relocated malloc limit
spl_init on some boards is called after stack and heap relocation, on
some platforms spl_relocate_stack_gd is called to handle setting the
limit to its value CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN when simple
SPL malloc is enabled during relocation. spl_init should then not
re-assign the old pre-relocation limit when this is defined.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
aspeed: Board init functions and common configs for ast2500 based boards
Add configuration file with parameters that are very likely to be shared by
all ast2500-based boards.
Add ast2500-board.c file with the init code that is very likely to be
shared by all ast2500-based boards. Reviewed-by: Simon Glass <sjg@chromium.org>
aspeed: Add basic ast2500-specific drivers and configuration
Clock Driver
This driver is ast2500-specific and is not compatible with earlier
versions of this chip. The differences are not that big, but they are
in somewhat random places, so making it compatible with ast2400 is not
worth the effort at the moment.
SDRAM MC driver
The driver is very ast2500-specific and is completely incompatible
with previous versions of the chip.
The memory controller is very poorly documented by Aspeed in the
datasheet, with any mention of the whole range of registers missing. The
initialization procedure has been basically taken from Aspeed SDK, where
it is implemented in assembly. Here it is rewritten in C, with very limited
understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
Add support for Watchdog Timer, which is compatible with AST2400 and
AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver
does not follow the driver model. It also uses fixed clock, so no clock
driver is needed.
Add support for timer for Aspeed ast2400/ast2500 devices.
The driver actually controls several devices, but because all devices
share the same Control Register, it is somewhat difficult to completely
decouple them. Since only one timer is needed at the moment, this should
be OK. The timer uses fixed clock, so does not rely on a clock driver.
Add sysreset driver, which uses watchdog timer to do resets and particular
watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 26 Jan 2017 01:42:38 +0000 (20:42 -0500)]
arm: Note vendor-required status of certain MACH_TYPE values
In the cases of some boards, a MACH_TYPE number is used which is either
not registered upstream or worse (for functionality) is re-using the
number of a different (or reference) platform instead. Make sure we
have a comment in these cases.
Cc: Albert ARIBAUD <albert.aribaud@3adev.fr> Cc: Walter Schweizer <swwa@users.sourceforge.net> Cc: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de>
Tom Rini [Thu, 26 Jan 2017 01:42:36 +0000 (20:42 -0500)]
arm: Clean up MACH_TYPE_xxx usage after re-sync of mach-types
With the latest mach-types values we have many instances where we no
longer need to define a value and a few cases where the name (but not
value) have changed slightly.
This is not a strict revert as it is easier to fix
board/atmark-techno/armadillo-800eva/armadillo-800eva.c to now the
correct name (same value) than to revert that change too.
Patrick Delaunay [Fri, 27 Jan 2017 10:00:42 +0000 (11:00 +0100)]
cmd, disk: convert CONFIG_PARTITION_UUIDS, CMD_PART and CMD_GPT
We convert CONFIG_PARTITION_UUIDS to Kconfig first. But in order to cleanly
update all of the config files we must also update CMD_PART and CMD_GPT to also
be in Kconfig in order to avoid complex logic elsewhere to update all of the
config files.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Ladislav Michl [Thu, 19 Jan 2017 10:45:35 +0000 (11:45 +0100)]
cmd: ubi: allow '-' to specify maximum volume size
Currently maximum volume size can be specified only if no other
arguments are used. Use '-' placeholder as volume size to allow
maximum volume size to be specified together with volume id and
type.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Stefan Roese [Fri, 9 Dec 2016 14:03:28 +0000 (15:03 +0100)]
mmc: Add Marvell Xenon SDHCI controller driver
This driver implementes platform specific code for the Xenon SDHCI
controller which is integrated in the Marvell MVEBU Armada 37xx and
Armada 7k / 8K SoCs.
History:
This driver is ported from the Marvell U-Boot version 2015.01 which is
written by Victor Gu <xigu@marvell.com> with minor changes ported from
the Linux driver which is written by Ziji Hu <huziji@marvell.com>.
Stefan Roese [Mon, 12 Dec 2016 07:24:56 +0000 (08:24 +0100)]
mmc: sdhci: Add support for optional controller specific set_ios_post()
Some SDHCI drivers might need to do some special controller configuration
after the common clock set_ios() function has been called (speed / width
configuration). This patch adds a call to the newly created function
set_ios_port() when its configured in the host driver.
This will be used by the Xenon SDHCI controller driver used on the
Marvell Armada 3700 and 7k/8k ARM64 SoCs.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Stefan Roese [Mon, 12 Dec 2016 07:34:42 +0000 (08:34 +0100)]
mmc: sdhci: Clear SDHCI_CLOCK_CONTROL before configuring the new value
This patch completely clears the SDHCI_CLOCK_CONTROL register before the
new value is configured instead of just clearing the 2 bits
SDHCI_CLOCK_CARD_EN and SDHCI_CLOCK_INT_EN. Without this change, some
clock configurations will lead to the "Internal clock never stabilised."
error message on the Xenon SDHCI controller used on the Marvell Armada
3700 and 7k/8k ARM64 SoCs.
The Linux SDHCI core driver also writes 0 to this register before
the new value is configured. So this patch simplifies the driver a bit
and brings the U-Boot driver more in-line with the Linux one.
Tony O'Brien [Fri, 6 Jan 2017 04:29:45 +0000 (17:29 +1300)]
powerpc: Enable flush and invalidate dcache by range for MPC85xx
Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-ops for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues in some drivers when the dcache was flushed. While the root
cause was under investigation, these functions were disabled in
Commit cb1629f91a for affected SoCs, including the MPC85xx, to make
the various drivers work.
On the T208x USB stopped working after v2016.07 was pulled. After
re-enabling the dcache functions for the MPC85xx it started working
again. The USB and DPPA Ethernet drivers have been seen as
operational after this change but other drivers cannot be tested.
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> Cc: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun>
Tony O'Brien [Thu, 1 Dec 2016 20:22:34 +0000 (09:22 +1300)]
mpc85xx: pcie: Implement workaround for Erratum A007815
The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers. This should be done
immediately after resetting the PCI Express controller.
Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz>
[York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
Darwin Dingel [Mon, 24 Oct 2016 20:48:01 +0000 (09:48 +1300)]
powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907
Core hang occurs when using L1 stashes. Workaround is to disable L1
stashes so software uses L2 cache for stashes instead.
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz> Cc: York Sun <york.sun@nxp.com>
[York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
Tom Rini [Mon, 23 Jan 2017 22:40:22 +0000 (17:40 -0500)]
travis-ci: Add swig and libpython-dev to the package list
As part of 1905c8fc711a we introduced failures depending on if swig and
libpython-dev are installed or not. To provide coverage for this are of
code in the future ensure we have these packages installed.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Andrew F. Davis [Mon, 23 Jan 2017 17:34:37 +0000 (11:34 -0600)]
mach-omap2: Cleanup secure boot media generation
Currently all secure media types of SPL are generated for all platforms,
all platforms do not need all types, only generate the media types valid
for each platform.
Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Tom Rini [Mon, 23 Jan 2017 00:43:11 +0000 (19:43 -0500)]
Kconfig: Migrate BOARD_LATE_INIT to a select
This option should not really be user selectable. Note that on PowerPC
we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be
conditional on that.
Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
Tuomas Tynkkynen [Sun, 22 Jan 2017 23:34:39 +0000 (01:34 +0200)]
rpi: Fix device tree path on ARM64
The directory structure of device tree files produced by the kernel's
'make dtbs_install' is different on ARM64, the RPi3 device tree file is
in a 'broadcom' subdirectory there.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Jagan Teki [Tue, 10 Jan 2017 10:18:43 +0000 (11:18 +0100)]
mmc: Print error code for mmc_complete_init failure
Print the error code for non-zero (failure case) instead
of making debug statement without any condition, this
usually gives proper clue in failure condition.
mmc: sdhci: Distinguish between base clock and maximum peripheral frequency
The sdhci controller assumes that the base clock frequency is fully supported by
the peripheral and doesn't support hardware limitations. The Linux kernel
distinguishes between base clock (max_clk) of the host controller and maximum
frequency (f_max) of the card interface. Use the same differentiation and allow
the platform to constrain the peripheral interface.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Masahiro Yamada [Sat, 21 Jan 2017 09:05:28 +0000 (18:05 +0900)]
ARM: dts: uniphier: compile only DT files that make sense
All the UniPhier DT files are compiled if CONFIG_ARCH_UNIPHIER
is enabled, but not all of them actually work. For example, when
U-Boot is compiled for ARM 32 bit, 64 bit DT files are also built,
and vice versa. Compile only the combination that makes sense.
Masahiro Yamada [Sat, 21 Jan 2017 09:05:27 +0000 (18:05 +0900)]
ARM: uniphier: add macro to generate SoC data look-up function
There are similar functions that look up SoC data by the SoC ID.
The new macro UNIPHIER_DEFINE_SOCDATA_FUNC will be helpful to
avoid the code duplication.
Masahiro Yamada [Sat, 21 Jan 2017 09:05:26 +0000 (18:05 +0900)]
ARM: uniphier: simplify SoC ID get function
Currently, uniphier_get_soc_type() converts the SoC ID (this is
read from the revision register) to an enum symbol to use it for SoC
identification. Come to think of it, there is no need for the
conversion in the first place. Using the SoC ID from the register
as-is a straightforward way.
Masahiro Yamada [Sat, 21 Jan 2017 09:05:25 +0000 (18:05 +0900)]
ARM: uniphier: replace <common.h> with <linux/delay.h> where possible
The <common.h> includes too many headers. Actually, these files
needed to include it for udelay() declaration. Now we can replace
it with <linux/delay.h> thanks to commit 5bc516ed661a ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").
Masahiro Yamada [Sat, 21 Jan 2017 09:05:24 +0000 (18:05 +0900)]
ARM: uniphier: replace <linux/err.h> with <linux/errno.h>
These files only need error number macros. Actually, IS_ERR(),
PTR_ERR(), ERR_PTR(), etc. are not useful for U-Boot. Avoid
unnecessary header includes.
Masahiro Yamada [Sat, 21 Jan 2017 09:05:23 +0000 (18:05 +0900)]
ARM: uniphier: add uniphier_v8_defconfig
This defconfig does not support SPL. If you use this, the basic
SoC initialization must be done in firmware that runs before U-Boot.
(Generally, ARM Trusted Firmware is expected to do this job).
Masahiro Yamada [Sat, 21 Jan 2017 09:05:22 +0000 (18:05 +0900)]
ARM: uniphier: make SPL optional for ARVv8 SoCs
We may want to run different firmware before running U-Boot. For
example, ARM Trusted Firmware runs before U-Boot, making U-Boot
a non-secure world boot loader. In this case, the SoC might be
initialized there, which enables us to skip SPL entirely.
This commit removes "select SPL" to make it configurable. This
also enables the Multi SoC support for the UniPhier ARMv8 SoCs.
(CONFIG_ARCH_UNIPHIER_V8_MULTI) Thanks to the driver model and
Device Tree, the U-Boot proper part is now written in a generic way.
The board/SoC parameters reside in DT. The Multi SoC support
increases the memory footprint a bit, but the U-Boot proper does
not have strict memory constraint. This will mitigate the per-SoC
(sometimes per-board) defconfig burden.
Uri Mashiach [Thu, 19 Jan 2017 08:51:45 +0000 (10:51 +0200)]
status_led: Kconfig migration
Move all of the status LED feature to drivers/led/Kconfig.
The LED status definitions were moved from the board configuration
files to the defconfig files.
TBD: Move all of the definitions in the include/status_led.h to the
relevant board's defconfig files.
Tested boards: CL-SOM-AM57x, CM-T335
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Tom Rini [Sat, 21 Jan 2017 00:55:53 +0000 (19:55 -0500)]
mx6saberesd_spl: Correct falcon mode addition
When falcon mode support was added, it was right around when SPL_OS_BOOT
was migrated to Kconfig. So first we must move the enablement to the
defconfig file. Next, it turned off EXT support rather than add the
information to allow for falcon mode from EXT. Add this information so
that the board compiles after 5d28b930f237.
Emmanuel Vadot [Thu, 19 Jan 2017 09:23:56 +0000 (10:23 +0100)]
bootm: qnx: Disable data cache before booting QNX image
Instead of disabling the data cache in the bootelf command, disabling
it in the do_bootm_qnxelf function.
Some ELF binary might want the cache enabled.
projects / u-boot / log