]> git.sur5r.net Git - u-boot/log
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8 years agox86: Add an ICH6 pin configuration driver
Simon Glass [Sat, 12 Mar 2016 05:07:13 +0000 (22:07 -0700)]
x86: Add an ICH6 pin configuration driver

Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: link: Add pin configuration to the device tree
Simon Glass [Sat, 12 Mar 2016 05:07:12 +0000 (22:07 -0700)]
x86: link: Add pin configuration to the device tree

At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.

Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Update microcode for secondary CPUs
Simon Glass [Sat, 12 Mar 2016 05:07:11 +0000 (22:07 -0700)]
x86: Update microcode for secondary CPUs

Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: ivybridge: Show microcode version for each core
Simon Glass [Sat, 12 Mar 2016 05:07:10 +0000 (22:07 -0700)]
x86: ivybridge: Show microcode version for each core

Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Record the CPU details when starting each core
Simon Glass [Sat, 12 Mar 2016 05:07:09 +0000 (22:07 -0700)]
x86: Record the CPU details when starting each core

As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Move common MRC Kconfig options to the common file
Simon Glass [Sat, 12 Mar 2016 05:07:08 +0000 (22:07 -0700)]
x86: Move common MRC Kconfig options to the common file

At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Allow I/O functions to use pointers
Simon Glass [Sat, 12 Mar 2016 05:07:07 +0000 (22:07 -0700)]
x86: Allow I/O functions to use pointers

It is common with memory-mapped I/O to use the address of a structure member
to access memory, as in:

   struct some_regs {
      u32 ctrl;
      u32 data;
   }

   struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;

   writel(1, &reg->ctrl);
   writel(2, &reg->data);

This does not currently work with inl(), outl(), etc. Add a cast to permit
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add macros to clear and set I/O bits
Simon Glass [Sat, 12 Mar 2016 05:07:06 +0000 (22:07 -0700)]
x86: Add macros to clear and set I/O bits

The clrsetbits_...() macros are useful for working with memory mapped I/O.
But they do not work with I/O space, as used on x86 machines.

Add some macros to provide similar features for I/O.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: ivybridge: Drop sandybridge_early_init()
Simon Glass [Sat, 12 Mar 2016 05:07:01 +0000 (22:07 -0700)]
x86: ivybridge: Drop sandybridge_early_init()

This function was removed in the previous clean-up. Drop it from the header
file also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Move Intel Management Engine code to a common place
Simon Glass [Sat, 12 Mar 2016 05:07:00 +0000 (22:07 -0700)]
x86: Move Intel Management Engine code to a common place

Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Rename PORT_RESET to IO_PORT_RESET
Simon Glass [Sat, 12 Mar 2016 05:06:59 +0000 (22:06 -0700)]
x86: Rename PORT_RESET to IO_PORT_RESET

This same name is used in USB. Add a prefix to distinguish it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Move common CPU code to its own place
Simon Glass [Sat, 12 Mar 2016 05:06:58 +0000 (22:06 -0700)]
x86: Move common CPU code to its own place

Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Move common LPC code to its own place
Simon Glass [Sat, 12 Mar 2016 05:06:57 +0000 (22:06 -0700)]
x86: Move common LPC code to its own place

Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add the root-complex block to common intel registers
Simon Glass [Sat, 12 Mar 2016 05:06:56 +0000 (22:06 -0700)]
x86: Add the root-complex block to common intel registers

This is similar to MCH in that it is used in various drivers. Add it to
the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Create a common header for Intel register access
Simon Glass [Sat, 12 Mar 2016 05:06:55 +0000 (22:06 -0700)]
x86: Create a common header for Intel register access

There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.

An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).

Add a new header file for these registers, and move MCH into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Move microcode code to a common location
Simon Glass [Sat, 12 Mar 2016 05:06:54 +0000 (22:06 -0700)]
x86: Move microcode code to a common location

This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Move cache-as-RAM code into a common location
Simon Glass [Sat, 12 Mar 2016 05:06:53 +0000 (22:06 -0700)]
x86: Move cache-as-RAM code into a common location

This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: cpu: Add functions to return the family and stepping
Simon Glass [Sat, 12 Mar 2016 05:06:52 +0000 (22:06 -0700)]
x86: cpu: Add functions to return the family and stepping

These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Allow use of serial soon after relocation
Simon Glass [Sat, 12 Mar 2016 05:06:51 +0000 (22:06 -0700)]
x86: Allow use of serial soon after relocation

At present on x86 machines with use cache-as-RAM, the memory goes away just
before board_init_r() is called. This means that serial drivers are
no-longer unavailable, until initr_dm() it called, etc.

Any attempt to use printf() within this period will cause a hang.

To fix this, mark the serial devices as 'unavailable' when it is no-longer
available. Bring it back when serial_initialize() is called. This means that
the debug UART will be used instead for this period.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agoinput: i8042: Make sure the keyboard is enabled
Simon Glass [Sat, 12 Mar 2016 05:06:50 +0000 (22:06 -0700)]
input: i8042: Make sure the keyboard is enabled

Add one more step into the init sequence. This fixes the keyboard on samus,
which otherwise does not work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
8 years agosyscon: Avoid returning a device on failure
Simon Glass [Sat, 12 Mar 2016 05:06:49 +0000 (22:06 -0700)]
syscon: Avoid returning a device on failure

If the device cannot be probed, syscon_get_by_driver_data() will still
return a useful value in its devp parameter. Ensure that it returns NULL
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodm: timer: Correct timer init ordering after relocation
Simon Glass [Sat, 12 Mar 2016 05:06:46 +0000 (22:06 -0700)]
dm: timer: Correct timer init ordering after relocation

Commit 1057e6c broke use of the timer with driver model. If the timer is used
before relocation, then it becomes broken after relocation. This prevents
some x86 boards from booting. Fix it.

Fixes: 1057e6c (timer: Set up the real timer after driver model is available)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add a few microcode files
Simon Glass [Mon, 7 Mar 2016 02:28:34 +0000 (19:28 -0700)]
x86: broadwell: Add a few microcode files

Add two microcode files for broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add comments to the SIPI vector
Simon Glass [Mon, 7 Mar 2016 02:28:25 +0000 (19:28 -0700)]
x86: Add comments to the SIPI vector

The Intel SIPI (start-up inter-processor interrupt) vector is the entry
point for each secondary CPU (also called an AP - applications processor).
The assembler and C code are linked, so add comments to indicate this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Tidy up mp_init to reduce duplication
Simon Glass [Mon, 7 Mar 2016 02:28:22 +0000 (19:28 -0700)]
x86: Tidy up mp_init to reduce duplication

The timeout step is always 50us. By updating apic_wait_timeout() to print
the debug messages we can simplify the code. Also tidy up a few messages and
comments while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Correct duplicate POST values
Simon Glass [Mon, 7 Mar 2016 02:28:18 +0000 (19:28 -0700)]
x86: Correct duplicate POST values

Two power-on-self-test values are the same. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add a script to aid code conversion from coreboot
Simon Glass [Mon, 7 Mar 2016 02:28:17 +0000 (19:28 -0700)]
x86: Add a script to aid code conversion from coreboot

It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: gpio: Correct GPIO setup ordering
Simon Glass [Mon, 7 Mar 2016 02:28:13 +0000 (19:28 -0700)]
x86: gpio: Correct GPIO setup ordering

The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.

Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: dts: link: Add board ID GPIOs
Simon Glass [Mon, 7 Mar 2016 02:28:12 +0000 (19:28 -0700)]
x86: dts: link: Add board ID GPIOs

At present the board ID GPIOs are hard-coded. Move them to the device tree
so that we can use general SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: dts: link: Move SPD info into the memory controller
Simon Glass [Mon, 7 Mar 2016 02:28:11 +0000 (19:28 -0700)]
x86: dts: link: Move SPD info into the memory controller

The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.

As a first step, move the information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: link: Add required GPIO properties
Simon Glass [Mon, 7 Mar 2016 02:28:10 +0000 (19:28 -0700)]
x86: link: Add required GPIO properties

In order to use GPIO phandles we need to add some GPIO properties as
specified by the GPIO bindings. Add these for link.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add some more common MSR indexes
Simon Glass [Mon, 7 Mar 2016 02:28:04 +0000 (19:28 -0700)]
x86: Add some more common MSR indexes

Many of the model-specific indexes are common to several Intel CPUs. Add
some more common ones, and remove them from the ivybridge-specific header
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: cpu: Make the vendor table const
Simon Glass [Mon, 7 Mar 2016 02:27:57 +0000 (19:27 -0700)]
x86: cpu: Make the vendor table const

This does not need to be modified at run-time, so make it const.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agomalloc_simple: Add a little more debugging
Simon Glass [Mon, 7 Mar 2016 02:27:55 +0000 (19:27 -0700)]
malloc_simple: Add a little more debugging

Output the pointer returned by each call to malloc(). This can be useful
when debugging memory problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Correct a few comments and nits
Simon Glass [Mon, 7 Mar 2016 02:27:53 +0000 (19:27 -0700)]
pci: Correct a few comments and nits

Two comments are missing a parameter and there is an extra blank line. Also
two of the region access macros are misnamed. Correct these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agopci: Add functions to update PCI configuration registers
Simon Glass [Mon, 7 Mar 2016 02:27:52 +0000 (19:27 -0700)]
pci: Add functions to update PCI configuration registers

It is common to read a config register value, clear and set some bits, then
write back the updated value. Add functions to do this in one step, for
convenience.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agogpio: Use const where possible
Simon Glass [Mon, 7 Mar 2016 02:27:51 +0000 (19:27 -0700)]
gpio: Use const where possible

Some functions do not change the struct gpio_desc parameter. Update these to
use const so this is clear.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agogpio: Add a function to obtain a GPIO vector value
Simon Glass [Mon, 7 Mar 2016 02:27:50 +0000 (19:27 -0700)]
gpio: Add a function to obtain a GPIO vector value

We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO
is assigned a single bit and can be set high or low on the circuit board. We
already have a legacy function for reading these values. Add one that
supports driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agocpu: Add support for microcode version and CPU ID
Simon Glass [Mon, 7 Mar 2016 02:27:49 +0000 (19:27 -0700)]
cpu: Add support for microcode version and CPU ID

Some CPUs use microcode and each core can have a different version of
microcode loaded. Also some CPUs support the concept of an integer ID used
for identification purposes. Add support for these in the CPU uclass.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agovideo: Allow simple-panel to be used without regulators
Simon Glass [Mon, 7 Mar 2016 02:27:48 +0000 (19:27 -0700)]
video: Allow simple-panel to be used without regulators

At present simple-panel requires regulator support and will not build
without it. But some panels do not have a power supply, or at least not one
that can be controlled. Update the implementation to cope with this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
8 years agox86: Document how to play with SeaBIOS
Bin Meng [Mon, 29 Feb 2016 07:54:52 +0000 (23:54 -0800)]
x86: Document how to play with SeaBIOS

Boting SeaBIOS is done via U-Boot's bootelf command. Document this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: qemu: Enable ACPI table generation by default
Bin Meng [Mon, 29 Feb 2016 07:54:51 +0000 (23:54 -0800)]
x86: qemu: Enable ACPI table generation by default

Now that ACPI is supported on QEMU, enable it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Support booting SeaBIOS
Bin Meng [Mon, 29 Feb 2016 07:54:50 +0000 (23:54 -0800)]
x86: Support booting SeaBIOS

SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.

As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Implement functions for writing coreboot table
Bin Meng [Sun, 28 Feb 2016 06:58:03 +0000 (22:58 -0800)]
x86: Implement functions for writing coreboot table

To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Support writing configuration tables in high area
Bin Meng [Sun, 28 Feb 2016 06:58:02 +0000 (22:58 -0800)]
x86: Support writing configuration tables in high area

For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow write_tables() to write the configuration tables in
high area (malloc'ed memory).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Simplify codes in write_tables()
Bin Meng [Sun, 28 Feb 2016 06:58:01 +0000 (22:58 -0800)]
x86: Simplify codes in write_tables()

Given all table write routines have the same signature, we can
simplify the codes by using a function table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Change write_acpi_tables() signature a little bit
Bin Meng [Sun, 28 Feb 2016 06:58:00 +0000 (22:58 -0800)]
x86: Change write_acpi_tables() signature a little bit

Change the parameter and return value of write_acpi_tables() to u32
to conform with other table write routines.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Use a macro for ROM table alignment
Bin Meng [Sun, 28 Feb 2016 06:57:59 +0000 (22:57 -0800)]
x86: Use a macro for ROM table alignment

Define ROM_TABLE_ALIGN instead of using 1024 directly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Change to use start/end address pair in write_tables()
Bin Meng [Sun, 28 Feb 2016 06:57:58 +0000 (22:57 -0800)]
x86: Change to use start/end address pair in write_tables()

Add a new variable rom_table_start and pass it to ROM table write
routines. This reads better than previous single rom_table_end.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Clean up coreboot_tables.h
Bin Meng [Sun, 28 Feb 2016 06:57:57 +0000 (22:57 -0800)]
x86: Clean up coreboot_tables.h

Clean up this file a little bit:
- Remove inclusion of <linux/compiler.h>
- Use tab in the macro definition

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Move sysinfo related to sysinfo.h
Bin Meng [Sun, 28 Feb 2016 06:57:56 +0000 (22:57 -0800)]
x86: Move sysinfo related to sysinfo.h

coreboot_tables.h should not include sysinfo related stuff.
Move those to asm/arch-coreboot/sysinfo.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agox86: Move asm/arch-coreboot/tables.h to a common place
Bin Meng [Sun, 28 Feb 2016 06:57:55 +0000 (22:57 -0800)]
x86: Move asm/arch-coreboot/tables.h to a common place

Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that
coreboot table definitions can be used by other x86 builds.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agospl: arm: Make sure to include all of the u_boot_list entries
Tom Rini [Tue, 15 Mar 2016 21:56:29 +0000 (17:56 -0400)]
spl: arm: Make sure to include all of the u_boot_list entries

Starting with 96e5b03 we use a linker list for partition table
information.  However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well.  While doing this, it's
best to simply include all linker lists to future proof ourselves.

Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agomvebu: ds414: Move cmd_syno into ds414 directory
Tom Rini [Wed, 16 Mar 2016 19:25:46 +0000 (15:25 -0400)]
mvebu: ds414: Move cmd_syno into ds414 directory

When we switch to including all linker lists in SPL it is important to
not include commands as that may lead to link errors due to other things
we have already discarded.  In this case as we don't have other common
code nor other Synology borads, move the cmd_syno.c file (which claims
to be ds414 specific anyways!) into the ds414 directory and only build
it for non-SPL builds.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoarm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX
Tom Rini [Wed, 16 Mar 2016 14:38:21 +0000 (10:38 -0400)]
arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XX

On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size.  Since OMAP44XX is only
seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we
will know that we don't have it for OMAP44XX.

Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agolpc32xx: work_92105: Rework Makefile
Tom Rini [Wed, 16 Mar 2016 13:56:55 +0000 (09:56 -0400)]
lpc32xx: work_92105: Rework Makefile

When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case change things so that we
only build the right objects for SPL or non-SPL

Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agocmd: scsi: Group the command portion together, guard with !CONFIG_SPL_BUILD
Tom Rini [Wed, 16 Mar 2016 13:45:03 +0000 (09:45 -0400)]
cmd: scsi: Group the command portion together, guard with !CONFIG_SPL_BUILD

When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case, the SCSI code needs a lot
of attention so for now just guard the command portions.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoARM: keystone2: Only link cmd_ddr3.o on non-SPL builds
Tom Rini [Wed, 16 Mar 2016 13:24:00 +0000 (09:24 -0400)]
ARM: keystone2: Only link cmd_ddr3.o on non-SPL builds

When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case simply move cmd_ddr3.o
over to the list with the rest.

Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoARM: keystone2: Switch to using the poweroff command
Tom Rini [Wed, 16 Mar 2016 13:19:43 +0000 (09:19 -0400)]
ARM: keystone2: Switch to using the poweroff command

Now that we have a standard way to power off the hardware, switch to
using that rather than our own command.

Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoARM: keystone2: Split monitor code / command code
Tom Rini [Wed, 16 Mar 2016 13:10:08 +0000 (09:10 -0400)]
ARM: keystone2: Split monitor code / command code

When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded.  In this case, we split the code for
supporting the monitor out from the code for loading it.

Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoARM: DRA7xx: Enable NFS boot command
Andrew F. Davis [Fri, 11 Mar 2016 21:22:20 +0000 (15:22 -0600)]
ARM: DRA7xx: Enable NFS boot command

NFS loading works on DRA7 variants, remove the undefinition.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoti_armv7_common: env: Add NFS loading support to default enviroment
Andrew F. Davis [Fri, 11 Mar 2016 21:04:03 +0000 (15:04 -0600)]
ti_armv7_common: env: Add NFS loading support to default enviroment

NFS loading is similar to net loading except initial files are loaded
over NFS instead of TFTP, this removes the need for multiple different
protocol servers running on the host and allows the use of a single
network file system containing boot related files in their usual
in-filesystem directory. Add defaults for this boot style here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agospl_nor: fix warning when compiled for 64bit target
Masahiro Yamada [Mon, 29 Feb 2016 11:50:34 +0000 (20:50 +0900)]
spl_nor: fix warning when compiled for 64bit target

Fix "warning: cast to pointer from integer of different size".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoARM: DRA7: DDR: Enable SR in Power Management Control
Nishanth Menon [Wed, 9 Mar 2016 12:09:56 +0000 (17:39 +0530)]
ARM: DRA7: DDR: Enable SR in Power Management Control

If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agokeystone2: env: Set mmc as default boot for k2g-evm
Yan Liu [Wed, 9 Mar 2016 10:09:39 +0000 (15:39 +0530)]
keystone2: env: Set mmc as default boot for k2g-evm

For k2l, k2e and k2hk, ubi is set to default boot in uboot
environment settings; while for k2g, mmc should be the
default boot. This patch is to set mmc as default for k2g-evm

Signed-off-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agokeystone2: env: add env script for booting with an initramfs with firmware
Murali Karicheri [Wed, 9 Mar 2016 10:09:38 +0000 (15:39 +0530)]
keystone2: env: add env script for booting with an initramfs with firmware

This patch updates the env script to include a initramfs with firmware
loaded and provided to kernel through second argument of bootz command
during boot. Defined DEFAULT_FW_INITRAMFS_BOOT_ENV to have all of the
required env variables and use it in evm specific config file.

The K2 linux drivers for PCIe and NetCP (1G, 10G) requires serdes
firmwares. These requires firmware to be available early through the boot
process in some cases to satisfy firmware requests from driver. Hence use
a small initramfs to provide the same and update boot env to accommodate
this in the boot flow. This method is used when rootfs is nfs and ubifs.
This fs contains just lib/firmware folder with all required firmware.

When rootfs is on initramfs, then the filesystem has the firmware under
lib/firmware and this early initramfs is not required and is not used.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agok2g: configs: Add support to save env in MMC
Lokesh Vutla [Wed, 9 Mar 2016 10:09:37 +0000 (15:39 +0530)]
k2g: configs: Add support to save env in MMC

Adding support to save env in MMC on k2g platforms, as it is the
preferred peripheral in saving env.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agok2g: env: Allow use of a script and plain text env files
Lokesh Vutla [Wed, 9 Mar 2016 10:09:36 +0000 (15:39 +0530)]
k2g: env: Allow use of a script and plain text env files

For development purposes, it is easier to use the env import command
and plain text or script files instead of script-images. So allow
u-boot to load env var from a text file or a script file.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoti_armv7_common: env: Consolidate support for loading script and text env files
Lokesh Vutla [Wed, 9 Mar 2016 10:09:35 +0000 (15:39 +0530)]
ti_armv7_common: env: Consolidate support for loading script and text env files

Support for loading bootscript and text env file is duplicated in all TI
platforms. Add this information to DEFAULT_MMC_TI_ARGS so that it can be
reused in all TI platforms.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoam43xx: configs: Enable USB commands for non usb boot also
Mugunthan V N [Wed, 9 Mar 2016 10:09:34 +0000 (15:39 +0530)]
am43xx: configs: Enable USB commands for non usb boot also

With commit aee119bd70b8 ('am43xx_evm: add usb host boot support') usb
commands is removed from U-boot second stage and enbaled only on USB
boot config. Fixing this by enable USB commands for both USB boot and
in second stage u-boot.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoam335x: configs: Fix usb ether boot support
Lokesh Vutla [Wed, 9 Mar 2016 10:09:33 +0000 (15:39 +0530)]
am335x: configs: Fix usb ether boot support

CONFIG_SPL_NET_VCI_STRING is available only with BOOTP. So if
CMD_DHCP is enabled for SPL in usb ether boot, it will not pass
the right vendor name and failing to download the right file.
Also all the net CMD_* are not required in SPL builds. So defining
these only for non-SPL builds.

Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoti_armv7_keystone2: env: Remove securedb.key.bin load
Carlos Hernandez [Wed, 9 Mar 2016 10:09:32 +0000 (15:39 +0530)]
ti_armv7_keystone2: env: Remove securedb.key.bin load

securedb.key.bin is not supported so it should not be loaded by
default init_ubi command.

Signed-off-by: Carlos Hernandez <ceh@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoti_armv7_keystone2: env: Update UBIFS image paths
Carlos Hernandez [Wed, 9 Mar 2016 10:09:31 +0000 (15:39 +0530)]
ti_armv7_keystone2: env: Update UBIFS image paths

UBI images created by OE does not contain boot partition by default,
instead kernel and dtb are placed in /boot directory inside rootfs
partition. So update env commands to load files from correct
location.

Signed-off-by: Carlos Hernandez <ceh@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoti_armv7_keystone2: configs: add usb mass storage support
Mugunthan V N [Wed, 9 Mar 2016 10:09:30 +0000 (15:39 +0530)]
ti_armv7_keystone2: configs: add usb mass storage support

Add USB mass storage support so that kernel can be read from
connected usb storage.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoefi_loader: Pass proper device path in on boot
Alexander Graf [Fri, 4 Mar 2016 00:10:14 +0000 (01:10 +0100)]
efi_loader: Pass proper device path in on boot

EFI payloads can query for the device they were booted from. Because
we have a disconnect between loading binaries and running binaries,
we passed in a dummy device path so far.

Unfortunately that breaks grub2's logic to find its configuration
file from the same device it was booted from.

This patch adds logic to have the "load" command call into our efi
code to set the device path to the one we last loaded a binary from.

With this grub2 properly detects where we got booted from and can
find its configuration file, even when searching by-partition.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agoefi_loader: Call fdt preparation functions
Alexander Graf [Fri, 4 Mar 2016 00:10:13 +0000 (01:10 +0100)]
efi_loader: Call fdt preparation functions

We have a nice framework around image fils to prepare a device tree
for OS execution. That one patches in missing device tree nodes and
fixes up the memory range bits.

We need to call that one from the EFI boot path too to get all those
nice fixups. This patch adds the call.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agoarm: Allow EFI payload code to take exceptions
Alexander Graf [Fri, 4 Mar 2016 00:10:12 +0000 (01:10 +0100)]
arm: Allow EFI payload code to take exceptions

There are 2 ways an EFI payload could return into u-boot:

  - Callback function
  - Exception

While in EFI payload mode, r9 is owned by the payload and may not contain
a valid pointer to gd, so we need to fix it up. We do that properly for the
payload to callback path already.

This patch also adds gd pointer restoral for the exception path.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agoarm64: Replace fdt_name env variables with fdtfile
Alexander Graf [Fri, 4 Mar 2016 00:10:11 +0000 (01:10 +0100)]
arm64: Replace fdt_name env variables with fdtfile

The commonly defined environment variable to determine the device tree
file name is called fdtfile rather than fdt_name. Replace all occurences
of fdt_name with fdtfile.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agoefi_loader: Add MAINTAINERS entry
Alexander Graf [Fri, 4 Mar 2016 00:10:10 +0000 (01:10 +0100)]
efi_loader: Add MAINTAINERS entry

Now that everything's in place, let's add myself as the maintainer for
the efi payload support.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoefi_loader: Add README section in README.efi
Alexander Graf [Fri, 4 Mar 2016 00:10:09 +0000 (01:10 +0100)]
efi_loader: Add README section in README.efi

To preserve all cover letter knowledge of the status on UEFI payload
support, let's add some sections to README.efi.

Signed-off-by: Alexander Graf <agraf@suse.de>
v3 -> v4:

  - Add section about config options
  - s/10kb/10KB/

8 years agoefi_loader: Add distro boot script for removable media
Alexander Graf [Wed, 9 Mar 2016 23:26:15 +0000 (00:26 +0100)]
efi_loader: Add distro boot script for removable media

UEFI defines a simple boot protocol for removable media. There we should look
at the EFI (first GPT FAT) partition and search for /efi/boot/bootXXX.efi with
XXX being different between different platforms (x86, x64, arm, aa64, ...).

This patch implements a simple version of that protocol for the default distro
boot script. With this we can automatically boot from valid UEFI enabled
removable media.

Because from all I could see U-Boot by default doesn't deliver device tree
blobs with its firmware, we also need to load the dtb from somewhere. Traverse
the same EFI partition for an fdt file that fits our current board so that
an OS receives a valid device tree when booted automatically.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
8 years agoefi_loader: hook up in build environment
Alexander Graf [Fri, 4 Mar 2016 00:10:07 +0000 (01:10 +0100)]
efi_loader: hook up in build environment

Now that we have all the bits and pieces ready for EFI payload loading
support, hook them up in Makefiles and KConfigs so that we can build.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
[trini: Enable only when we of OF_LIBFDT, disable on kwb and colibri_pxa270]
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoarm64: Allow EFI payload code to take exceptions
Alexander Graf [Fri, 4 Mar 2016 00:10:06 +0000 (01:10 +0100)]
arm64: Allow EFI payload code to take exceptions

There are 2 ways an EFI payload could return into u-boot:

  - Callback function
  - Exception

While in EFI payload mode, x18 is owned by the payload and may not contain
a valid pointer to gd, so we need to fix it up. We do that properly for the
payload to callback path already.

This patch also adds gd pointer restoral for the exception path.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agoarm64: Allow exceptions to return
Alexander Graf [Fri, 4 Mar 2016 00:10:05 +0000 (01:10 +0100)]
arm64: Allow exceptions to return

Our current arm64 exception handlers all panic and never return to the
exception triggering code.

But if any handler wanted to continue execution after fixups, it would
need help from the exception handling code to restore all registers.

This patch implements that help. With this code, exception handlers on
aarch64 can successfully return to the place the exception happened (or
somewhere else if they modify elr).

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agoefi_loader: Implement memory allocation and map
Alexander Graf [Fri, 4 Mar 2016 00:10:04 +0000 (01:10 +0100)]
efi_loader: Implement memory allocation and map

The EFI loader needs to maintain views of memory - general system memory
windows as well as used locations inside those and potential runtime service
MMIO windows.

To manage all of these, add a few helpers that maintain an internal
representation of the map the similar to how the EFI API later on reports
it to the application.

For allocations, the scheme is very simple. We basically allow allocations
to replace chunks of previously done maps, so that a new LOADER_DATA
allocation for example can remove a piece of the RAM map. When no specific
address is given, we just take the highest possible address in the lowest
RAM map that fits the allocation size.

Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: Simon Glass <sjg@chromium.org>
8 years agoefi_loader: Add "bootefi" command
Alexander Graf [Wed, 9 Mar 2016 23:27:20 +0000 (00:27 +0100)]
efi_loader: Add "bootefi" command

In order to execute an EFI application, we need to bridge the gap between
U-Boot's notion of executing images and EFI's notion of doing the same.

The best path forward IMHO here is to stick completely to the way U-Boot
deals with payloads. You manually load them using whatever method to RAM
and then have a simple boot command to execute them. So in our case, you
would do

  # load mmc 0:1 $loadaddr grub.efi
  # bootefi $loadaddr

which then gets you into a grub shell. Fdt information known to U-boot
via the fdt addr command is also passed to the EFI payload.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
[trini: Guard help text with CONFIG_SYS_LONGHELP]
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoefi_loader: Add disk interfaces
Alexander Graf [Fri, 4 Mar 2016 00:10:02 +0000 (01:10 +0100)]
efi_loader: Add disk interfaces

A EFI applications usually want to access storage devices to load data from.

This patch adds support for EFI disk interfaces. It loops through all block
storage interfaces known to U-Boot and creates an EFI object for each existing
one. EFI applications can then through these objects call U-Boot's read and
write functions.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
[trini: Update for various DM changes since posting]
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoefi_loader: Add runtime services
Alexander Graf [Fri, 4 Mar 2016 00:10:01 +0000 (01:10 +0100)]
efi_loader: Add runtime services

After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.

This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.

We could maybe in the future map U-boot environment variables to EFI variables
here.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
8 years agoefi_loader: Add console interface
Alexander Graf [Fri, 4 Mar 2016 00:10:00 +0000 (01:10 +0100)]
efi_loader: Add console interface

One of the basic EFI interfaces is the console interface. Using it an EFI
application can interface with the user. This patch implements an EFI console
interface using getc() and putc().

Today, we only implement text based consoles. We also convert the EFI Unicode
characters to UTF-8 on the fly, hoping that everyone managed to jump on the
train by now.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
8 years agoefi_loader: Add boot time services
Alexander Graf [Fri, 4 Mar 2016 00:09:59 +0000 (01:09 +0100)]
efi_loader: Add boot time services

When an EFI application runs, it has access to a few descriptor and callback
tables to instruct the EFI compliant firmware to do things for it. The bulk
of those interfaces are "boot time services". They handle all object management,
and memory allocation.

This patch adds support for the boot time services and also exposes a system
table, which is the point of entry descriptor table for EFI payloads.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
8 years agoefi_loader: Add PE image loader
Alexander Graf [Fri, 4 Mar 2016 00:09:58 +0000 (01:09 +0100)]
efi_loader: Add PE image loader

EFI uses the PE binary format for its application images. Add support to EFI PE
binaries as well as all necessary bits for the "EFI image loader" interfaces.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
8 years agoinclude/efi_api.h: Add more detailed API definitions
Alexander Graf [Fri, 4 Mar 2016 00:09:57 +0000 (01:09 +0100)]
include/efi_api.h: Add more detailed API definitions

The EFI API header is great, but missing a good chunk of function prototype,
GUID defines and enum declarations.

This patch extends it to cover more of the EFI API. It's still not 100%
complete, but sufficient enough for our EFI payload interface.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
8 years agodisk/part.c: Expose list of available block drivers
Alexander Graf [Fri, 4 Mar 2016 00:09:56 +0000 (01:09 +0100)]
disk/part.c: Expose list of available block drivers

We have a pretty nice and generic interface to ask for a specific block
device. However, that one is still based around the magic notion that
we know the driver name.

In order to be able to write fully generic disk access code, expose the
currently internal list to other source files so that they can scan through
all available block drivers.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
8 years agoarm64: Only allow dcache disabled in SPL builds
Alexander Graf [Fri, 4 Mar 2016 00:09:55 +0000 (01:09 +0100)]
arm64: Only allow dcache disabled in SPL builds

Now that we have an easy way to describe memory regions and enable the MMU,
there really shouldn't be anything holding people back from running with
caches enabled on AArch64. To make sure people catch early if they're missing
on the caching fun, give them a compile error.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agoarm64: Remove non-full-va map code
Alexander Graf [Fri, 4 Mar 2016 00:09:54 +0000 (01:09 +0100)]
arm64: Remove non-full-va map code

By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agohikey: Add MMU tables
Alexander Graf [Fri, 4 Mar 2016 00:09:53 +0000 (01:09 +0100)]
hikey: Add MMU tables

The hikey runs with dcache disabled today. There really should be no reason
not to use caches on AArch64, so let's add MMU definitions and enable the
dcache.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agodwmmc: Increase retry timeout
Alexander Graf [Fri, 4 Mar 2016 00:09:52 +0000 (01:09 +0100)]
dwmmc: Increase retry timeout

When enable dcache on HiKey, we're running into MMC command timeouts
because our retry loop is now faster than the eMMC (or an external SD
card) can answer.

Increase the retry count to the same as the timeout value for status
reports.

The real fix is obviously to not base this whole thing on a cycle counter
but on real wall time, but that would be slightly more intrusive.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agovexpress64: Add MMU tables
Alexander Graf [Fri, 4 Mar 2016 00:09:51 +0000 (01:09 +0100)]
vexpress64: Add MMU tables

There's no good excuse for running with caches disabled on AArch64,
so let's just move the vexpress64 target to enable the MMU and run
with caches on.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agotegra: Replace home grown mmu code with generic table approach
Alexander Graf [Fri, 4 Mar 2016 00:09:50 +0000 (01:09 +0100)]
tegra: Replace home grown mmu code with generic table approach

Now that we have nice table driven page table creating code that gives
us everything we need, move to that.

Signed-off-by: Alexander Graf <agraf@suse.de>
8 years agozymqmp: Replace home grown mmu code with generic table approach
Alexander Graf [Fri, 4 Mar 2016 00:09:49 +0000 (01:09 +0100)]
zymqmp: Replace home grown mmu code with generic table approach

Now that we have nice table driven page table creating code that gives
us everything we need, move to that.

Signed-off-by: Alexander Graf <agraf@suse.de>