Simon Glass [Wed, 5 Dec 2012 14:46:33 +0000 (14:46 +0000)]
sha1: Use const where possible, and unsigned for input len
In preparation for making the hash function common, we may as well use
const where we can. Also the input length cannot be negative, but may
be very large, so use unsigned.
designware_i2c: Fixed the setting of the i2c bus speed
There are three couple (hcnt/lcnt) of registers for each
speed (SS/FS/HS). The driver needs to set the proper couple
of regs according to what speed we are setting.
In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.
To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.
This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.
Marek Vasut [Fri, 30 Nov 2012 18:17:07 +0000 (18:17 +0000)]
mxs: i2c: Implement algorithm to set up arbitrary i2c speed
This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.
The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de>
Marek Vasut [Fri, 30 Nov 2012 18:17:06 +0000 (18:17 +0000)]
mxs: i2c: Restore speed setting after block reset
The I2C block reset configures the I2C bus speed to strange value.
Read the I2C speed from the block before reseting the block and
restore it afterwards, so the I2C operates correctly. This issue
can be replicated by doing unsuccessful I2C transfer, after such
transfer finishes, the I2C block clock speed is misconfigured.
Marek Vasut [Mon, 12 Nov 2012 14:34:31 +0000 (14:34 +0000)]
i2c: mxs: Fix TIMING2 register value
According to FSL, the value in the TIMING2 register shall be 0x00300030
instead of what's written in the datasheet. This new value correlates
with older STMP36xx datasheet. Issues were detected in Linux when this
register was misconfigured, so write this correct value.
Marek Vasut [Mon, 12 Nov 2012 14:34:28 +0000 (14:34 +0000)]
i2c: mxs: Abstract out the MXS I2C speed setup
This patch pulls out the I2C speed setup from the i2c_init() call
and implements the bus configuration lookup table with register
values that needs to be programmed into the I2C IP to run at
particular speed.
This patch is a first step towards implementing run-time I2C bus
speed configuration for the MXS I2C IP.
Marek Vasut [Mon, 12 Nov 2012 14:34:25 +0000 (14:34 +0000)]
i2c: Use __weak instead of __attribute__((weak, alias))
Use __weak from linux/compiler.h instead of __attribute__((weak, alias))
to define overridable function. This patch is intended as a cleanup patch
to bring some consistency into the code.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
Vincent Stehlé [Mon, 3 Dec 2012 05:23:16 +0000 (05:23 +0000)]
omap24xx_i2c: Handle wait_for_bb error
We add a return code to wait_for_bb() to be able to report errors to the
callers properly. We in turn handle this new error code in i2c_read, i2c_write
and i2c_probe.
ajoy [Sat, 17 Nov 2012 21:10:15 +0000 (21:10 +0000)]
OMAP3 SPI : Fixed bugs related to SPI transfer
Added posted writes (read after writes) to effect the
change immediately for channel confiuration and channel
enable register
Disable the channel to purge receieve data in TX_ONLY
mode transfer otherwise rx data will get affected by
the next immediate RX_ONLY mode transfer
Wait for the EOT bit to be set after last byte has been
loaded to TX shift register in the the TX_ONLY mode.This
ensures TX data has been completely shifted out
Disable the channel in RX_ONLY mode before reading the
last data from RXX register to prevent the SPI slave
to transmit next word
Signed-off-by: Ajoy Kumar Das <akdas75@yahoo.in> Cc: Tom Rini <trini@ti.com> Cc: jacopo mondi <j.mondi@voltaelectronics.com>
Lokesh Vutla [Thu, 15 Nov 2012 21:06:33 +0000 (21:06 +0000)]
omap: emif: configure emif only when required
DMM_LISA_MAP registers program whether memory is mapped
on particular EMIF or not. Irrespective of these registers
EMIF is getting configured. Correcting the same.
Peter Barada [Tue, 13 Nov 2012 07:40:28 +0000 (07:40 +0000)]
Pass sdrc timing values through board_sdrc_timings structure
Instead of passing individual registers by value to board_get_mem_timings,
pass a board_mem_timings structure pointer for the board files to fill in.
Pass same structure pointer to write_sdrc_timings. This saves about
90 bytes of space in SPL.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Mansoor Ahamed [Tue, 6 Nov 2012 13:06:33 +0000 (13:06 +0000)]
omap_gpmc: BCH8 support (ELM based)
This patch adds support for BCH8 error correction code to omap_gpmc
driver. We use GPMC to generate codes/syndromes but we need ELM to find
error locations from given syndrome.
Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
[ilya: merge it with omap_gpmc driver, some fixes and cleanup] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Mansoor Ahamed [Tue, 6 Nov 2012 13:06:32 +0000 (13:06 +0000)]
am33xx: add ELM support
AM33XX has Error Location Module (ELM) that can be used in conjuction
with GPMC controller to implement BCH codes fully in hardware.
This code is mostly taken from arago tree.
Ilya Yanok [Tue, 6 Nov 2012 13:06:30 +0000 (13:06 +0000)]
am33xx: NAND support
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.
Minkyu Kang [Sun, 9 Dec 2012 20:50:11 +0000 (20:50 +0000)]
universal_c210: fix compiler error and compiler warning
This patch fix following errors
universal.c: In function 'init_pmic_lcd':
universal.c:340: warning: implicit declaration of function 'get_pmic'
universal.c:340: warning: initialization makes pointer from integer without a cast
universal.c: In function 'lcd_power_on':
universal.c:431: warning: initialization makes pointer from integer without a cast
universal.c: At top level:
universal.c:335: warning: 'init_pmic_lcd' defined but not used
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Donghwa Lee <dh09.lee@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com>
Richard Genoud [Thu, 29 Nov 2012 23:18:34 +0000 (23:18 +0000)]
at91sam9x5ek: add USB configuration
Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Richard Genoud [Thu, 29 Nov 2012 23:18:33 +0000 (23:18 +0000)]
at91sam9x5ek: regroup FAT/DOS features
Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Richard Genoud [Thu, 29 Nov 2012 23:18:32 +0000 (23:18 +0000)]
at91sam9x5: enable USB support for 9x5ek board.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
In file included from ubifs.h:2137:0,
from ubifs.c:26:
misc.h: In function 'ubifs_zn_dirty':
misc.h:38:2: warning: passing argument 2 of 'test_bit' discards 'const' qualifier from pointer target type [enabled by default]
../include/asm/bitops.h:569:23: note: expected 'volatile void *' but argument is of type 'const long unsigned int *'
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Zhi-zhou Zhang [Sat, 24 Nov 2012 05:07:12 +0000 (05:07 +0000)]
MIPS: fix a latent bug on initialize $gp
If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned.
then the following ld insntrustion generates a Adel exception.
So here make _gp be always aligned in 8 bytes.
Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The filename buffer is allocated dynamically. It must be cache aligned.
Moreover, it is necessary to erase its content before we use it for
file name operations.
This prevents from corruption of written file names.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Łukasz Majewski [Wed, 5 Dec 2012 08:06:38 +0000 (08:06 +0000)]
fs:ext4:write: Store block device descriptor in file system structure
The device block descriptor (block_dev_desc_t) )shall be stored at
ext4 early code (at ext4fs_set_blk_dev in this case) to be available
for latter use (like put_ext4()).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Łukasz Majewski [Wed, 5 Dec 2012 08:06:37 +0000 (08:06 +0000)]
fs:ext4:write: Add lldiv and do_div to perform 64-32 bits division
The ext4write code has been using direct calls to 64-32 division
(/ and %).
Officially supported u-boot toolchains (eldk-5.[12].x) generate calls
to __aeabi_uldivmod(), which is niether defined in the toolchain libs
nor u-boot source tree.
Due to that, when the ext4write command has been executed, "undefined
instruction" execption was generated (since the __aeabi_uldivmod()
is not provided).
To fix this error, lldiv() for division and do_div() for modulo have
been used.
Those two functions are recommended for performing 64-32 bit number
division in u-boot.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Joshua Housh [Sun, 2 Dec 2012 17:09:26 +0000 (17:09 +0000)]
serial_pl011: Set RTS during initialization
If the pl011 is connected to another device which has hardware
flow-control on, characters are never received by the pl011.
Asserting RTS when flow-control is off will have no effect.
This is in line with how Linux behaves.
Signed-off-by: Joshua Housh <joshua.housh@calxeda.com> Tested-by: Marek Vasut <marex@denx.de>
Otavio Salvador [Tue, 4 Dec 2012 03:15:51 +0000 (03:15 +0000)]
mxs: SPL: Generalize memory initialization
Use a generic 'dram_vals[]' array that has the full initialization
sequence and rename the initialization method so it doesn't has a
frequency on its name.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Stefan Reinauer [Sat, 3 Nov 2012 11:41:39 +0000 (11:41 +0000)]
x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.
monitor_flash_len is unused, drop it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Vadim Bendebury [Sat, 3 Nov 2012 11:41:37 +0000 (11:41 +0000)]
x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.
This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.
Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Vadim Bendebury [Mon, 3 Dec 2012 13:59:20 +0000 (13:59 +0000)]
x86: Provide tick counter and frequency reference for Intel core architecture
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.
Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Duncan Laurie [Mon, 3 Dec 2012 13:59:00 +0000 (13:59 +0000)]
x86: Fix MTRR clear to detect which MTRR to use
Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move. Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 3 Dec 2012 13:56:51 +0000 (13:56 +0000)]
x86: fdt: Create basic .dtsi file for coreboot
This contains just the minimum information for a coreboot-based board.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Stefan Reinauer [Sat, 3 Nov 2012 11:41:29 +0000 (11:41 +0000)]
x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.
This can address the security risk of untrusted data being used during boot.
When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loadinlg of the environment. Add this to the
fdt as /config/delay-environment.
Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Gabe Black [Sat, 3 Nov 2012 11:41:28 +0000 (11:41 +0000)]
x86: Add back cold- and warm-boot flags
These were removed, but actually are useful.
Cold means that we started from a reset/power on.
Warm means that we started from another U-Boot.
We determine whether u-boot on x86 was warm or cold booted (really if
it started at the beginning of the text segment or at the ELF entry point).
We plumb the result through to the global data structure.
Gabe Black [Mon, 3 Dec 2012 14:26:08 +0000 (14:26 +0000)]
x86: Override calculate_relocation_address to use the e820 map
Because calculate_relocation_address now uses the e820 map, it will be able
to avoid addresses over 32 bits and regions that are at high addresses but
not big enough for U-Boot. It also means we can remove the hack which
limitted U-Boot's idea of the size of memory to less than 4GB.
Also take into account the space needed for the heap and stack, so we avoid
picking a very small region those areas might overlap with something it
shouldn't.
Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Gabe Black [Sat, 3 Nov 2012 11:41:24 +0000 (11:41 +0000)]
x86: Reorder x86's post relocation memory layout
This changes the layout in decreasing addresses from:
1. Stack
2. Sections in the image
3. Heap
to
1. Sections in the image
2. Heap
3. Stack
This allows the stack to grow significantly more since it isn't constrained by
the other u-boot areas. More importantly, the generic memory wipe code assumes
that the stack is the lowest addressed area used by the main part of u-boot.
In the original layout, that means that u-boot tramples all over itself. In
the new layout, it works.
Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>