powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Thu, 7 Apr 2016 16:56:48 +0000 (09:56 -0700)]
powerpc: Disable flush or invalidate dcache by range for some SoCs
Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-op for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues when the dcache is flushed. While the root cause is under
investigation, disable these functions for affected SoCs so various
drivers can work.
Hans de Goede [Thu, 12 May 2016 17:23:47 +0000 (19:23 +0200)]
sunxi: Enable USB host in CHIP defconfig
Reported-and-tested-by: Dennis Gilmore <dennis@ausil.us> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Andre Przywara [Thu, 12 May 2016 11:14:41 +0000 (12:14 +0100)]
arm/arm64: Move barrier instructions into separate header
Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.
Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.
This fixes compilation for 64-bit sunxi boards (Pine64).
Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fabio Estevam [Tue, 10 May 2016 16:31:40 +0000 (13:31 -0300)]
warp7: Fix boot by selecting CONFIG_OF_LIBFDT
CONFIG_OF_LIBFDT needs to be selected to avoid the following
boot problem:
reading zImage 6346216 bytes read in 118 ms (51.3 MiB/s)
Booting from mmc ...
reading imx7d-warp.dtb
32593 bytes read in 11 ms (2.8 MiB/s)
Kernel image @ 0x80800000 [ 0x000000 - 0x60d5e8 ]
FDT and ATAGS support not compiled in - hanging
### ERROR ### Please RESET the board ###
Stefan Roese [Fri, 6 May 2016 11:53:37 +0000 (13:53 +0200)]
usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA
With patch c998da0d (usb: Change power-on / scanning timeout handling),
the USB scanning is started earlier and with a smaller timeout. This
resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not
getting detected any more. This patch now adds a 1 second delay (in
the host mode only) to the DWC2 driver before the scanning is started.
With this delay, now all problematic USB keys are detected successfully
again. And there is no need any more to change the delay / timeout
in the common USB code (usb_hub.c).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de>
Marek Vasut [Tue, 3 May 2016 20:22:59 +0000 (22:22 +0200)]
usb: hub: Don't continue on get_port_status failure
The code shouldn't continue probing the port if get_port_status() failed.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Wed, 27 Apr 2016 01:32:56 +0000 (03:32 +0200)]
usb: Assure Get Descriptor request is in separate microframe
The Kingston DT Ultimate USB 3.0 stick is sensitive to this first
Get Descriptor request and if the request is not in a separate
microframe, the stick refuses to operate. Add slight delay, which
is enough for one microframe to pass on any USB spec revision.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Wed, 27 Apr 2016 01:08:12 +0000 (03:08 +0200)]
usb: Wait after sending Set Configuration request
Some devices, like the SanDisk Cruzer Pop need some time to process
the Set Configuration request, so wait a little until they are ready.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
Marek Vasut [Wed, 27 Apr 2016 21:38:05 +0000 (23:38 +0200)]
mtd: cqspi: Simplify indirect read code
The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSPI driver, which went through multiple rounds
of thorough review and testing. All the patch does is it plucks out
duplicate ad-hoc code distributed across the driver and replaces it
with more compact code doing exactly the same thing. There is no
speed change of the read operation.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com>
Marek Vasut [Wed, 27 Apr 2016 21:18:55 +0000 (23:18 +0200)]
mtd: cqspi: Simplify indirect write code
The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.
This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vignesh R <vigneshr@ti.com>
Marek Vasut [Tue, 26 Apr 2016 23:55:10 +0000 (01:55 +0200)]
usb: Don't init pointer to zero, but NULL
The pointer should always be inited to NULL, not zero (0). These are
two different things and not necessarily equal.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
Stefan Agner [Thu, 5 May 2016 23:59:12 +0000 (16:59 -0700)]
usb: ehci-mx6: allow board_ehci_hcd_init to fail
There could be runtime determined board specific reason why a EHCI
initialization fails (e.g. ENODEV if a Port is not available). In
this case, properly return the error code.
While at it, that function (board_ehci_hcd_init) has actually two
documentation blocks... Use the correct function name for the
documentation block of board_usb_phy_mode.
Peng Fan [Wed, 4 May 2016 07:27:50 +0000 (15:27 +0800)]
imx6: cache: disable L2 before touching Auxiliary Control Register
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"
So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Stephen Warren [Thu, 5 May 2016 23:02:06 +0000 (17:02 -0600)]
test/py: dfu: wait for USB device to go away at boot
It can take a while for a host machine to notice that a USB device has
disconnected, and process the change. At the end of the DFU test, we wait
up to 10 seconds for this to happen. This change makes the test wait the
same (up to) 10 seconds at the start of the test for any previously active
USB device-mode session to be cleaned up. Such as session might have been
used to download U-Boot into memory for example; this is certainly true
on my Tegra test systems. This changes should solve the DFU test
intermittency issues I've been seeing on some Tegra devices.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Russ Dill [Thu, 5 May 2016 13:52:10 +0000 (08:52 -0500)]
ARM: am33xx: Fix DDR initialization delays
The current delays in the DDR initialization routines for am33xx
architectures are sometimes not running long enough leading to DDR
init errors. On am437x, this shows up as an L3 NOC error after the
kernel boots. This is due to the timer not being initialized
properly, but instead still containing the timer init values from
the boot ROM which cause timers to expire in 1/4th the time
required.
timer_init is typically not called until board_init_r, however on
am33xx/am43xx udelay is required in sdram_init which is called
from board_init_f, so a call to timer_init is required earlier.
Note that this issue introduced in v2015.01 by:
b352dde "am33xx: Drop timer_init call from s_init".
Although this could instead fixed by reverting said commit, it
would cause timer_init to be called twice in both SPL and non-SPL
cases. This gives a little more fine grained control and also
matches what is being done on omap-command and fsl-layerscape.
Stephen Warren [Thu, 28 Apr 2016 18:45:44 +0000 (12:45 -0600)]
ARM: fix ifdefs in ARMv8 lowlevel_init()
Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some
ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
wrong endif was removed. This patch adds back that missing endif, and
adds a new ifdef to match the endif the now-correctly-terminated block
used to match against. Use "git show -U25 724219a65f55" to see enough
context to make the original issue clear.
In practical terms, this makes no difference to runtime behaviour. The
code that was incorrectly compiled into the binary when ifndef MULTIENTRY
is a no-op for other cases, since branch_if_master evaluates to a hard-
coded jump. The only issues were:
- A few extra instructions were added to the binary.
- The comment on the endif at the very end of the function, indicating
which ifdef it matched, were wrong.
An alternative might be to simply fix the comment on that trailing ifdef,
but that only addresses the second point above, not the first.
Marek Vasut [Wed, 4 May 2016 14:35:25 +0000 (16:35 +0200)]
mmc: Fix error in RPMB code
Since we do not build any board with CONFIG_SUPPORT_EMMC_RPMB , this
piece of code evaded conversion. Fix the following compiler error:
cmd/mmc.c: In function 'do_mmcrpmb':
cmd/mmc.c:316:32: error: 'struct blk_desc' has no member named 'part_num'
original_part = mmc->block_dev.part_num;
^
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
Ash Charles [Thu, 5 May 2016 18:58:07 +0000 (11:58 -0700)]
omap4: duovero: Disable EFI booting
The DuoVero board fails to compile with EFI enabled as the generated
binaries are too large. As this platform doesn't currently need EFI,
disable this feature.
Stephen Warren [Thu, 21 Apr 2016 22:03:37 +0000 (16:03 -0600)]
ARM: tegra: import latest Jetson TK1 spreadsheet
This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.
The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Wed, 20 Apr 2016 21:46:50 +0000 (15:46 -0600)]
pci: tegra: fix DM conversion issues on Tegra20
Tegra20's PCIe controller has a couple of quirks. There are workarounds in
the driver for these, but they don't work after the DM conversion:
1) The PCI_CLASS value is wrong in HW.
This is worked around in pci_tegra_read_config() by patching up the value
read from that register. Pre-DM, the PCIe core always read this via a
16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used,
so we need to check for offset 0x8 instead. Mask the offset value back to
32-bit alignment to make this work in all cases.
2) Accessing devices other than dev 1 causes a data abort.
Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code
called during enumeration while iterating over a bus. The DM PCIe core
doesn't use this function. Instead, enhance tegra_pcie_conf_address() to
validate the bdf being accessed, and refuse to access invalid devices.
Since pci_skip_dev() isn't used, delete it.
I've also validated that both these WARs are only needed for Tegra20, by
testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in
conditionally.
Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Tue, 12 Apr 2016 17:17:39 +0000 (11:17 -0600)]
ARM: tegra: enable GPU node by compatible value
In current Linux kernel Tegra DT files, 64-bit addresses are represented
in unit addresses as a pair of comma-separated 32-bit values. Apparently
this is no longer the correct representation for simple busses, and the
unit address should be represented as a single 64-bit value. If this is
changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no
longer be able to find and enable the GPU node, since it looks up the node
by name.
Fix that function to enable nodes based on their compatible value rather
than their node name. This will work no matter what the node name is, i.e
for DTs both before and after any rename operation.
Cc: Thierry Reding <treding@nvidia.com> Cc: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stefan Agner [Wed, 13 Apr 2016 23:38:02 +0000 (16:38 -0700)]
net: increase maximum frame size to accomediate VLAN packets
Ethernet packages with IEEE 802.1Q VLAN support may be up to 1522
bytes long. Increase the default size used to allocate packet
storage by 4 bytes. While at it, let git care about history and
rewrite the comment to represent the situation today only.
Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Lev Iserovich [Thu, 7 Jan 2016 23:04:16 +0000 (18:04 -0500)]
fdt: fix setting MAC addresses for multiple interfaces
For multiple ethernet interfaces the FDT offset of '/aliases' will change as we
are adding MAC addresses to the FDT.
Therefore only the first interface ('ethernet0') will get properly updated in
the FDT, with the rest getting FDT errors when we try to set their MAC address.
Signed-off-by: Lev Iserovich <iserovil@deshawresearch.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Tue, 26 Apr 2016 01:02:35 +0000 (03:02 +0200)]
usb: dwc2: Init desc_before_addr
Initialize desc_before_addr, otherwise the USB core won't send the
first 64B Get Device Descriptor request in common/usb.c function
usb_setup_descriptor() . There are some USB devices which expect
this sequence and otherwise can misbehave.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Wed, 27 Apr 2016 12:58:49 +0000 (14:58 +0200)]
usb: dwc2: Make OC protection configurable
Introduce a new flag in the controller private data, which allows selectively
disabling the OC protection. Use the standard 'disable-over-current' OF prop
to set this flag. This OC protection must be disabled on EBV SoCrates rev 1.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
Marek Vasut [Wed, 27 Apr 2016 12:55:57 +0000 (14:55 +0200)]
usb: dwc2: Pull Ext VBUS macro from dwc_otg_core_init()
Introduce a boolean flag in the dwc2 controller private data and set
it according to the macro (for now) instead of having this macro
directly in the dwc_otg_core_init(). This will let us configure the
flag from DT or such later on, if needed.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
Move CONFIG_SPL_TEXT_BASE down to 0x40200000 and set CONFIG_SPL_MAX_SIZE
to (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE), so that it's clear
what the limit is.
This will also help some compilers to fit all the code into the allocated
space.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Commit 7a439cadcf3192eb012a2432ca34670b676c74d2 broke generation of SPL
loadable FIT images (CONFIG_SPL_LOAD_FIT).
Fix it by removing the unnecessary storage of expected image type. This was a
left over of the previous implementation. It is not longer necessary since the
mkimage -b switch always has one parameter.
Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
Mario Six [Wed, 20 Apr 2016 08:44:52 +0000 (10:44 +0200)]
i2c/eeprom: Always define I2C_RXTX_LEN
I2C_RXTX_LEN from include/i2c.h is not defined if CONFIG_DM_I2C is
enabled. This leads to a compilation error on boards that enable both
CONFIG_CMD_EEPROM and CONFIG_DM_I2C.
To avoid this, we define I2C_RXTX_LEN in cmd/eeprom.c if it is not
already defined.
mx6ul_evk does not come with a eMMC populated, so we should not
define CONFIG_SUPPORT_EMMC_BOOT as it causes SPL to not be able
to boot some brands of SD cards, such as SanDisk microSD HC - 8GB:
U-Boot SPL 2016.05-rc1-28384-g108f841 (Apr 19 2016 - 11:19:11)
Trying to boot from MMC1
spl: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
When CONFIG_SUPPORT_EMMC_BOOT is defined spl_boot_mode() returns
MMCSD_MODE_EMMCBOOT, so remove this option to have a reliable boot
via SD card.
Michal Simek [Thu, 28 Apr 2016 07:08:18 +0000 (09:08 +0200)]
kbuild: Do not append dtb for OF_EMBED case
dtb is already included in binary that's why there is no need to replace
u-boot-spl.bin with u-boot-spl-dtb.bin. This is only needed for
OF_SEPARATE is enabled. Only copy -nodtb.bin version which is straight
output from objcopy -O binary.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ronald Zachariah [Thu, 28 Apr 2016 05:08:34 +0000 (07:08 +0200)]
fs: ext4: fix symlink read function
The function ext4fs_read_symlink was unable to handle a symlink
which had target name of exactly 60 characters.
Signed-off-by: Ronald Zachariah <rozachar@cisco.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 2 May 2016 14:52:51 +0000 (10:52 -0400)]
Revert "omap3: Use raw SPL by default for mmc1"
Unfortunately with this change we now are unable to do FS mode boots
from MMC1 as with the way the code works today we will always load and
assume that the hard-coded raw location contains U-Boot. Further, we
cannot fix this by just changing other logic to try FS-then-RAW as it
would also make us have to ignore what order the ROM is telling us to
try.
ARM: uniphier: allow to use System Bus for ROM boot mode of PH1-LD20
The System Bus is not available by default on the ROM boot mode of
PH1-LD20. To use devices connected to the System Bus, such as the
Micro Support Card, it is necessary to set up pin-muxing and some
System Bus Controller register.
Martin Pietryka [Wed, 27 Apr 2016 19:39:16 +0000 (21:39 +0200)]
drivers/video/am335x-fb: Properly point framebuffer behind palette
The DMA was outputting the palette on the screen because the base
for the DMA was not after the palette. In addition to that, the ceiling was
also too high, this led that the output on the screen was shifted.
NOTE: According to the TRM, even in 16/24bit mode a palette is required
in the first 32 bytes of the framebuffer.
See also:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/234967/834483#834483
"In this mode, the LCDC will assume all information is data and thus you
need to ensure that the DMA points to the first pixel of data and not the
first entry in the frame buffer which is the beginning of the 512 byte
palette."
Signed-off-by: Martin Pietryka <martin.pietryka@chello.at> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Martin Pietryka [Wed, 27 Apr 2016 19:39:15 +0000 (21:39 +0200)]
drivers/video/am335x-fb: Add support for 16bpp format
To support 16bpp we just need to change the raster_ctrl register
accordingly. Also 32bpp mode should work as well, but was not tested.
According to the TRM the uppermost byte will be ignored when
LCD_TFT_24BPP_UNPACK is set.
The switch logic is based on the Linux kernel tilcdc driver:
drivers/gpu/drm/tilcdc/tilcdc_crtc.c: lines 407 through 419
(kernel was checked out at commit: bcc981e9ed8)
Signed-off-by: Martin Pietryka <martin.pietryka@chello.at> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tom Rini [Wed, 27 Apr 2016 22:44:32 +0000 (18:44 -0400)]
omap3: Reduce logic/overo SPL max image size
While the OMAP3 has 64KiB of SRAM, per the TRM the download area is only
from 0x40200000 to 0x4020F000 and exceeding that will cause failure to
boot. Further, we need to make sure that we don't run into
SRAM_SCRATCH_SPACE_ADDR as once SPL is running we will write values
there and would corrupt our running image.
Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
We are running with the caches disabled when mctl_mem_matches gets called,
but the cpu's write buffer is still there and can still get in the way,
add a memory barrier to fix this.
This avoids mctl_mem_matches always returning false in some cases, which
was resulting in:
Michal Simek [Tue, 26 Apr 2016 14:12:06 +0000 (16:12 +0200)]
ARM64: zynqmp: Cleanup config file after CMD move
The patch:
"configs: Re-sync almost all of cmd/Kconfig"
(sha1: 78d1e1d0a157c8b48ea19be6170b992745d30f38)
doesn't remove empty if-endif. This patch is fixing it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.
Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5: Enable ABB configuration for MM voltage domain
Since we setup the voltage and frequency for the MM domain, we *must*
setup the ABB configuration needed for the domain as well. If we do not
do this, kernel configuring just the frequency using the default boot
loader configured voltage can fail on many corner lot units.
Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structure
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.
Hence, move the txdone mask definition over to structure describing
voltage domain.
ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2
This information is already available under vcores->volts.efuse.reg.
There is no reason for duplicating the information since AVS Class 0
definitions are common for OMAP5 and DRA7 and defined with
STD_FUSE_OPP_* macros. This allows a central location of defining
the ABB and voltage definitions especially since they are reused.
This also makes it simpler to prevent mistakes involved when changing
the boot OPP for the device.
The error message "spl: mmc block read error" may come from two
different functions, so we should better annotate the function name
where the error comes from to help debugging.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Peter Griffin [Wed, 20 Apr 2016 16:14:03 +0000 (17:14 +0100)]
ARM: hikey: Simplify README instructions.
This patch updates and simplifies the hikey README. The old
instructions were hard to follow, and convoluted.
This patch also updates the link to the mcuimage.bin which was outdated.
Using an outdated mcuimage.bin results in the additional a53 cores
not coming online when the kernel issues PSCI requests to
arm trusted firmware (ATF).
Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Peter Griffin [Wed, 20 Apr 2016 16:14:02 +0000 (17:14 +0100)]
ARM: hisilicon: hikey: Align memory node with upstream kernel
The memory node gets automatically generated by U-Boot
in arch_fixup_fdt(), before passing control to the kernel
using U-Boots representation of the dram banks.
However the upstream kernel uses the memory node to carve-out
regions of RAM for various purposes. To make this work without
changing arch_fixup_fdt() which will effect many platforms
we replicate the upstream memory node layout using the dram
banks.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Peter Griffin [Wed, 20 Apr 2016 16:13:59 +0000 (17:13 +0100)]
ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.
Currently only the serial pl01x driver is using DT,
and the other drivers still use platform data but
as more DT lands in the upstream kernel the aim is
to migrate the other drivers over to DT as well to
have a fully DT configured hikey u-boot.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Mon, 4 Apr 2016 17:03:52 +0000 (11:03 -0600)]
sf: fix timebase data type in _wait_ready()
get_timer() returns an unsigned 64-bit value, but is currently assigned to
a signed 32-bit variable. Due to sign extension and data truncation, this
causes the timeout loop in spi_flash_cmd_wait_ready() to immediately (and
incorrectly) fire for about 50% of all time values, based on whether bit
31 is set. In sandbox at least, this causes the test to pass or fail based
on system uptime, as opposed to time since the U-Boot binary was started.
Fixes: 4efad20a1751 ("sf: Update status reg check in spi_flash_cmd_wait_ready") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
According to common eMMC partition table for Android boot (see
PARTS_DEFAULT definition in include/configs/dra7xx_evm.h), "bootloader"
partition (where u-boot.img is stored) starts at 256 KiB. Which is equal
to 512 sectors (as 1 MMC sector size is 512 bytes).
This patch fixes CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR constant so that
it points to correct address of "bootloader" partition and SPL is able to
read, parse and run u-boot.img correctly.
This change was originally done as part of patch [1] in omapzoom u-boot.
Without this patch, SPL fails to parse U-Boot header with next error:
projects / u-boot / log