David Brownell [Fri, 11 Dec 2009 23:26:10 +0000 (15:26 -0800)]
ARM DPM: support updating HW breakpoints
Abstract the DPM breakpoint and watchpoint data structures to
have a shared core for housekeeping.
Abstract the code updating the watchpoint registers so that it
can be used to update breakpoint registers. Then do so, when
something has set up the breakpoint state used by this code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Fri, 11 Dec 2009 23:24:08 +0000 (15:24 -0800)]
ARM11: minor cleanup, mostly ITR comments
ITR register handling seemed to be giving me problems, so I updated
the comments to better say what the code is trying to do ... and to
note the preconditions (one of which seems to be an issue) as listed
in the ARM1136 TRM.
Also removed the unused "ARM11_TAP_DEFAULT" from the ITR scan code;
all the callers already specify an exit path, since this register
isn't usable with such vague semantics.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 10 Dec 2009 05:16:09 +0000 (21:16 -0800)]
stellaris: flash protection updates, minor fixes
Bugfix the read side of flash protection:
- read the right register(s)!
- handle more than 64K
- record the results in the right places
- don't display garbage.
Partially bugfix the write side:
- use 2KB lock regions instead of 1KB pages (!)
- validate input range
- don't try to _remove_ protection (it's write-once)
- #define values we'll need to commit writes.
- ... still doesn't handle pages over 64KB mark, or commit writes
And minor cleanup and fixes:
- get rid of some forward decls
- properly locate a doxygen comment
- fix some bad indentation
- remove superfluous #include
- add a new part ID (many are still missing)
- make the downloaded algorithm code be read-only
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Tue, 8 Dec 2009 21:09:38 +0000 (13:09 -0800)]
target: remove more exit() calls
These were all basically "can't happen" cases ... like having
state be corrupted by an alpha particle after the previous check
for whether a value was in-range.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Tue, 8 Dec 2009 21:06:41 +0000 (13:06 -0800)]
target: move 'extern' decls to *.h files
The exception being declarations for drivers. Those should
be split out in some clean way -- like driver add/remove calls
made by initialization code -- but that's for another day.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Øyvind Harboe [Fri, 4 Dec 2009 15:00:43 +0000 (16:00 +0100)]
minidriver: fix inline capability of minidriver
Low latency low CPU processing power systems(embedded)
will benefit greatly from being able to inline certain
jtag_add_xxx() fn's. The trick is that this has to be
done in such a way as to allow implementing an OpenOCD
API with a shared library(eventually) on a PC hosted
OpenOCD.
David Brownell [Tue, 8 Dec 2009 02:14:46 +0000 (18:14 -0800)]
ARM: cope with stupidheaded compiler
Some versions of GCC don't understand that if you mask with 0x3
then have cases 0-3, it's not possible for a variable assigned in
all those branches to have no value at end-of-case. Feh.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 7 Dec 2009 22:55:08 +0000 (14:55 -0800)]
ARM: list number of HW breakpoints/watchpoints
When starting up, say how many hardware breakpoints and watchpoints
are available on various targets.
This makes it easier to tell GDB how many of those resources exist.
Its remote protocol currently has no way to ask OpenOCD for that
information, so it must configured by hand (or not at all).
Update the docs to mention this; remove obsolete "don't do this" info.
Presentation of GDB setup information is still a mess, but at least
it calls out the three components that need setup.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 7 Dec 2009 22:55:08 +0000 (14:55 -0800)]
target: add debug_reason_name()
Provide and use debug_reason_name() instead of expecting targets
to call Jim_Nvp_value2name_simple(). Less dependency on Jim, and
the code becomes more clear too.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 7 Dec 2009 22:55:08 +0000 (14:55 -0800)]
ARM: don't clone arm_arch_state() code
Have various ARM cores delegate to arm_arch_state() to display
basic information, instead of duplicating that logic.
This shrinks the code, makes them all report when semihosting
is active, and highlights which data are specific to this core.
(Like ARM720 not having separate instruction and data caches.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 7 Dec 2009 22:55:07 +0000 (14:55 -0800)]
User's Guide: add quickie setup notes
Add a brief "setup with no customization" note showing the
how easily things can work if standard OpenOCD config scripts
already exist. We've had some new users comment that this
information is needlessly hard to find, so that starting to
use OpenOCD is more difficult than it should be.
Plus describe a few other issues that come up when setting
up an OpenOCD server.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 7 Dec 2009 22:54:13 +0000 (14:54 -0800)]
ARM: use <target/arm.h> not armv4_5.h
Move most declarations in <target/armv4_5.h> to <target/arm.h>
and update users.
What's left in the older file is stuff that I think should be
removed ... the old register cache access stuff, which makes it
awkward to support microcontroller profile (Cortex-M) cores.
The armv4_5_run_algorithm() declaration was moved too, even
though it's not yet as generic as it probably ought to be.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 7 Dec 2009 22:54:12 +0000 (14:54 -0800)]
ARM: move opcode macros to <target/arm_opcodes.h>
Move the ARM opcode macros from <target/armv4_5.h>, and a few
Thumb2 ones from <target/armv7m.h>, to more appropriate homes
in a new <target/arm_opcodes.h> file.
Removed duplicate opcodes from that v7m/Thumb2 set. Protected
a few macro argument references by adding missing parentheses.
Tightening up some of the line lengths turned up a curious artifact:
the macros for the Thumb opcodes are all 32 bits wide, not 16 bits.
There's currently no explanation for why it's done that way...
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 7 Dec 2009 22:54:12 +0000 (14:54 -0800)]
ARM: remove mrc_opcode(), use MRC() or MCR()
Get rid of mrc_opcode() in favor of ARMV4_5_MRC() or, where
arm*20t should have used it, ARMV4_5_MCR() instead.
Basically, *writing* coprocessor registers shouldn't have
used the *read* opcode ... and both should stick to standard
opcode constructors, not rearranging parameter sequence any
more than already needed.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Mon, 7 Dec 2009 19:57:46 +0000 (11:57 -0800)]
OMAP2420: define reset-assert event
Behave like OMAP3530: force global software reset. Given the
patch to teach ARM11 how to use these events, and use VCR to
catch the reset vector, this works better than either the
current reset logic or than using SRST.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Zachary T Welch [Mon, 7 Dec 2009 04:19:18 +0000 (20:19 -0800)]
allow 'flash_banks' command to give GDB output
The 'flash banks' command produces a list that needs to be formatted
properly for GDB's 'mem info' to work properly. The flash_banks TCL
wrapper provided this formatting, but wrappers no longer work for
second-level commands as they did in the past. With this patch,
the 'flash_banks' command can be used with the new command syntax
and display the required information.
Zachary T Welch [Sat, 5 Dec 2009 06:04:37 +0000 (22:04 -0800)]
rename nand.h to flash//nand/core.h
Rename nand.h as flash/nand/core.h, chase consumers. The public APIs
need to be sorted out with imp.h, but this allows other changes to
begin improving the separation between policy and mechanism.
Moves #include <target/target.h> and #include "driver.h" into the
internal headers or source files, removing it from <flash/nand/core.h>.
Zachary T Welch [Sat, 5 Dec 2009 02:24:14 +0000 (18:24 -0800)]
split NAND driver handling into nand/driver.[ch]
This work parallels the NOR directory, encapsulating the NAND drivers
into a separate file. This takes an extra step by encapsulating the
type of data structure used to manage the drivers, allowing it to be
changed from an array to a dynamic list in the future.
Zachary T Welch [Sat, 5 Dec 2009 00:07:47 +0000 (16:07 -0800)]
split flash.h into into flash/nor/*.h
Move the bulk of the flash.h file into flash/nor/core.h, leaving an
empty husk that will be removed in the next patch.
The NOR driver structure is an implementation detail, so move it into
its own private header file <flash/nor/driver.h> along with helper
declaration for finding them by name.
Zachary T Welch [Fri, 4 Dec 2009 12:01:45 +0000 (04:01 -0800)]
move more nor flash implementation details
Splits the exec mode commands out of flash.c into the flash/nor/ files.
The routines used by these high-level commands are moved into nor/core.c,
with their internal declarations placed in nor/imp.h.
David Brownell [Sat, 5 Dec 2009 00:51:48 +0000 (16:51 -0800)]
ARM: semihosting entry cleanup
Clean up arm_semihosting() entry a bit, comment some issues and just
which SVC opcodes are getting intercepted. Microcontroller profile
cores will need a new entry, since they use BKPT instead (and don't
have either SVC mode or an SPSR register).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Zachary T Welch [Fri, 4 Dec 2009 00:47:49 +0000 (16:47 -0800)]
add flash/nor/{tcl.c,imp.h} from flash/flash.c
Moves the top-level 'flash' command handlers into flash/nor/tcl.c,
with flash/nor/imp.h providing an internal implementation header
to share non-public API components.
Zachary T Welch [Fri, 4 Dec 2009 00:25:51 +0000 (16:25 -0800)]
separate Jim from jtag/core.c
After previous efforts, only one Jim routine remained in jtag/core.c,
and moving it to jtag/tcl.c painlessly finishes separating these layers.
The headers need separating, but the implementation is clean.
Zachary T Welch [Fri, 4 Dec 2009 01:38:24 +0000 (17:38 -0800)]
check top-level command registrations
When calling module_register_commands, the return value needs to be
checked for failures. Instead of duplicating code, use an array of
function pointers to the identical registration functions to iterate
over during startup.
Nicolas Pitre [Thu, 3 Dec 2009 22:27:13 +0000 (17:27 -0500)]
basic ARM semihosting support
Semihosting enables code running on an ARM target to use the
I/O facilities on the host computer. The target application must
be linked against a library that forwards operation requests by
using the SVC instruction that is trapped at the Supervisor Call
vector by the debugger. The "hosted" library version provided
with CodeSourcery's Sourcery G++ Lite for ARM EABI is one example.
This is currently available for ARM9 processors, but any ARM
variant should be able to support this with little additional work.
Tested using binaries compiled with Sourcery G++ Lite 2009q1-161
and ARM RVCT 3.0.
Dean Glazeski [Mon, 16 Nov 2009 19:40:46 +0000 (13:40 -0600)]
Make ARM NAND I/O operations aware of last op
Updates the ARM NAND I/O code to look at and update the op
field of arm_nand_data to reflect the last operation performed.
It uses this field to copy the correct code to the target in the
case where the struct is used for reads and writes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Dean Glazeski [Mon, 16 Nov 2009 19:34:24 +0000 (13:34 -0600)]
ARM NAND I/O interface update
Modify the arm_nand_data struct to better support both read and
write operations while using the same struct. An additional
field was added, and initialized, to record the last operation
so that the correct code can be loaded to the working area.
David Brownell [Fri, 4 Dec 2009 00:08:04 +0000 (16:08 -0800)]
ARM DPM: share debug reason logic
No point in both ARM11 and Cortex-A8 having private copies
of the logic sorting out e.g. DBG_REASON_WATCHPOINT.
Add and use a shared routine for this ... there's actually
a bunch more debug entry logic that could be shared, this
is just a start on that. Note that this routine fixes a
bug observed in the ARM11 code, where some abort mode quirks
were displayed as being an unknown debug reason; and also
silences needless ARM11 chatter.
Likewise with private copies of DSCR ... add one to the DPM
struct. Save it as part of setting DBG_REASON_* so later
patches can switch over to using that copy.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Fri, 4 Dec 2009 00:08:04 +0000 (16:08 -0800)]
ARM11: use shared DSCR bit names
For the bits now defined in "arm_dpm.h", switch to the
shared DSCR_* symbol and remove the ARM11_DSCR_* version.
Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_*
sibling symbol. (Note: for both ARM11 and Cortex-A8, this
should arguably be enabled by default when single stepping.)
Remove some other unused declarations in "arm11.h".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Fri, 4 Dec 2009 00:08:04 +0000 (16:08 -0800)]
ARM DPM: make DSCR bit defs sharable
Move the symbols for these bits from "armv7a.h" to "arm_dpm.h",
where they can be seen and used not just by Cortex-A but also
by the ARM11 (armv6) code.
Change them from bit numbers to bit masks ... this matches the
usage in ARM11 code, and also makes it easier to read.
Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's
enabling ITR functionality, not external interrupts, so this
changes the name to be less misleading. (There *IS* a bit
affecting interrupts, and this isn't it.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
David Brownell [Thu, 3 Dec 2009 22:44:03 +0000 (14:44 -0800)]
fix another init regression
This makes Beagle work again, instead of losing horribly because
the JTAG event handlers are no longer able to e.g. "runtest". I
get the previous quirky behavior ... comes up OK but "reset halt"
somewhat mysteriously makes it all better. (Instead of nothing
being able to work at all...) However, I'm still seeing:
The 'init' command must be used before 'init'.
That seems to come from invoking "jtag init", sometime after it
gets mapped to "ocd_jtag init", according to debug message traces.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Zachary T Welch [Thu, 3 Dec 2009 13:23:16 +0000 (05:23 -0800)]
fix double 'init' regression
To prevent regression in the behavior of 'init', we allow it to run in
any mode. If provided with -c init and with -c noinit, then the second
init at startup caused a spurious mode failure. Let 'init' handle it.
Zachary T Welch [Thu, 3 Dec 2009 13:13:45 +0000 (05:13 -0800)]
fix regressions with GDB port numbers
Use a separate variable for iterating GDB service port numbers than
the one set by the user. Restores the behavior of returning the
original port number and only incrementing the port used on success.
Zachary T Welch [Thu, 3 Dec 2009 11:46:15 +0000 (03:46 -0800)]
change #include "../hello.h" to "hello.h"
Before we can -I the top-level src/ directory alone, references to
"hello.h" must be updated. This is an internal header, so it does
not need angle brackets.
projects / openocd / log