Spencer Oliver [Mon, 28 Jan 2013 11:45:51 +0000 (11:45 +0000)]
helper: hexify correctly handle signed chars
The current implementation of hexify was not correctly handling signed chars.
This function is currently used by the ti-icdi driver and as such was causing
random write issues.
As a note perhaps a better long term fix would be to change to using uint8_t
buffers rather than char. This will require changes to the ti-icdi driver
aswell.
Evan Hunter [Thu, 3 Jan 2013 16:29:18 +0000 (16:29 +0000)]
rtos: Fix regression preventing use of first RTOS & clean up rtos_qsymbol()
ThreadX support was not working due to it being first in the list of RTOS - regression.
Auto-detect off, an RTOS was always be marked as successfully detected, even if symbols are not found.
Lines 223-227 were unnecessary as they are done in rtos_try_next()
Added lots of comments
Improved readability by separating: GDB not finding a symbol vs no more symbols being available
Regression caused by patch which was allowed only 52 minutes for review : http://openocd.zylin.com/895
Spencer Oliver [Fri, 4 Jan 2013 11:46:00 +0000 (11:46 +0000)]
flash: add stm32lx loader Hard Fault workaround
An issue has been seen with the stm32lx flash driver that if a
power cycle/reset is applied after a erase, any ram loader will Hard Fault
on execution.
A similar issue is mentioned in the errata for the device.
Two solution's seem to workaround this issue:
1, Handle the exception, this means adding exception vectors to the loader
and changing the exception address using nvic vtor register.
2. falling back to using slower direct page writes - approx 50% slower.
Using solution 1 would mean restrictions are placed on the loader location.
Solution 2 was chosen mainly as it was simpler too implement.
Change-Id: I429f06b5a3e3b1d8de90071a88a7df11fc9b46a7 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1010 Tested-by: jenkins
Roman D [Fri, 18 Jan 2013 06:53:43 +0000 (10:53 +0400)]
flash: EFM32 GG/LG page size detection fix
Fixed flash page size detection according to EFM32 GG/LG errata.
MEM_INFO_PAGE_SIZE register containts invalid value in devices with
revision number lower than 18 and should not be used.
Change-Id: Idb2832246efcbbec2fd98a5c458f72a36df386fb Signed-off-by: Roman D <me@iamroman.org>
Reviewed-on: http://openocd.zylin.com/1116 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Roman Reichel [Tue, 15 Jan 2013 22:13:08 +0000 (23:13 +0100)]
opendous: Inhibit unnecessary state transitions
When current tap state and end state are the same, transitions are added which is not what should happen.
The usbprog driver was already patched like this long time ago.
Change-Id: I339e87156bdc7b5c83c10c14025b749605d3871a Signed-off-by: Roman Reichel <romanreichel@aol.de>
Reviewed-on: http://openocd.zylin.com/1113 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Roman D [Thu, 10 Jan 2013 08:31:45 +0000 (12:31 +0400)]
flash: EFM32 flash implementation
Limited (no page unprotect, no block writes) implementation of EFM32
flash support. Verified with EFM32 development kit and STLink V2 adapter
using SWD.
Change-Id: I3db2054d9aa628a1fe4814430425db3c9959c71c Signed-off-by: Roman D <me@iamroman.org>
Reviewed-on: http://openocd.zylin.com/1106 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Spencer Oliver [Tue, 13 Nov 2012 12:01:35 +0000 (12:01 +0000)]
stlink: enable connect under reset
Currently if the target supports srst_nogate we wait until target assert_reset
until we get a chance to assert the srst.
However sometimes we will not get this far if the target has already failed
the initial scan.
This has been tested on stm32.
Change-Id: I2c4486942a011534d3e2044788563669bf457b60 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/972 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Spencer Oliver [Tue, 13 Nov 2012 12:02:26 +0000 (12:02 +0000)]
jtag: enable connect under reset
Currently if the target supports srst_nogate we wait until target assert_reset
until we get a chance to assert the srst.
However sometimes we will not get this far if the target has already failed
the jtag_examine_chain.
This has been tested on targets that support this behaviour (STM32 and STR9).
Change-Id: Ibcf7584b137b472f31ba6ddd5cd99d848c5508d1 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/971 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Kamal Dasu [Wed, 17 Oct 2012 16:16:36 +0000 (12:16 -0400)]
mips_m4k: Added SMP debug support for mips architectures
This change adds smp debug support for mips platforms. The change
leverages the exiting gdb smp support as mentioned in the OpenOCD
documentation for using gdb in smp environemnt. Added commands
smp_on, smp_off, smp_gdb to control the smp mode. The implementation
also provides a way to send Jc packet and toggle the gdb display core
context as well.
Change-Id: I0835a5aed1844b6ebf8291582912f20695346003 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Reviewed-on: http://openocd.zylin.com/937 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Jason Moehlman [Mon, 19 Nov 2012 23:33:34 +0000 (18:33 -0500)]
arm: Mis-aligned data issue fix.
Fixes issue with big endian hosts and mis-aligned data on some hosts.
Fixes unaligned access exception on hosts that do not support unaligned
access when debugging some arm targets.
Salvador Arroyo [Sat, 3 Nov 2012 11:39:27 +0000 (12:39 +0100)]
mips: optimize mips32_pracc_read_regs() code
Current code needs 101 pracc accesses for this function, this code needs 12 less.
There is a singularity in this code, is the only function that restore
a register from param out instead from pracc stack. Obviously the register
was previously stored at param out. This save 2 pracc accesses.
Change-Id: Ie95b6f983a3198dafc0eab2dd5acc11f871a8d83 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/958 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sat, 3 Nov 2012 10:29:46 +0000 (11:29 +0100)]
mips: optimize mips32_pracc_write_regs() code.
All the the loads are done with lui and ori instructions, there is
no need to save any register, they will be overwritten.
Like in the previous patch, for speed optimization in write code,
same instructions can be saved if the lower half word or the upper
half word is 0.
If the lower half word is 0, it can be loaded with only a lui instruction.
If the higher half word is 0 it can be done with an ori instruction with register 0.
This code saves 10 pracc accesses at a minimum, and 40 at a maximum,
obviously if register 2 to 31 are 0 or a half word is 0
Current code needs 91 pracc accesses.
Change-Id: I892c5b440191d0c7a474c96845d41c373b7fc637 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/957 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
Salvador Arroyo [Fri, 2 Nov 2012 15:08:31 +0000 (16:08 +0100)]
mips: optimize write code for speed
All the writes are done by the new function mips32_pracc_write_mem_generic().
The code is similar to the read generic code.
The reuse of register 15 as memory base address saves 3 pracc accesses.
The first write takes 13(12) pracc accesses and for additional writes 3(2).
Loading miniprograms should take 25% less time and loading fastdata transfer
handler code should be over 2x faster.
Change-Id: Ia3b24ba084af33be99da19f00a7fd4d1b291f350 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/956 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Fri, 2 Nov 2012 09:14:58 +0000 (10:14 +0100)]
mips: optimize read code for speed
Really nothing new that not explained in previous patches.
The code is expanded as needed, there are no loops in pracc code.
For the first value pracc accesses are reduced from 39 to 16
and for aditional values from 10 to 3.
dump_image should work around 3x faster.
Change-Id: I37c9b13395c09eb52a91f10cdb6cbaedef8ab98b Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/955 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Thu, 1 Nov 2012 22:22:32 +0000 (23:22 +0100)]
mips: optimize mips32_pracc_read_u32() function
This function is highly optimized, there is not much to
improve.
Loading the base address for pracc access with the new
defined MIPS32_PRACC_BASE_ADDR saves one instruction.
The memory address is loaded in too steps. First the upper
address is loaded. The lower address is passed as an offset in
the memory load instruction.
The offset is signed, if the lower address is in the range of
0x8000 to 0xffff the offset is a negative value, and the upper
address must be incremented by 1.
Pracc accesses are now 12 instead of 14.
Change-Id: I286945b240ed5c5d5cc540780a41a8a5fa075da3 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/952 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Thu, 1 Nov 2012 19:55:28 +0000 (20:55 +0100)]
mips: optimize CP0 read/write code
MIPS32_PRACC_BASE_ADDR is defined as 0xFF200000. Now is
possible to load the base address with a lui instruction and
only one pracc access.
Offsets to the pracc code addresses are defined to simplify the code
and probably make it a bit more readable or self-explained.
Change-Id: I853dd2d7fad52745931cc6e6be68c0ae156d897e Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/951 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
Salvador Arroyo [Thu, 1 Nov 2012 14:45:12 +0000 (15:45 +0100)]
mips: code clean up in mips_m4k_debug_entry() function
The function mips_ejtag_read_debug() is defined in mips_ejtag.c
and is called only by mips_m4k_debug_entry() for reading the
CP0 debug register. The comment in this function is obviously wrong.
There is a generic function to read CP0 registers with similar code.
A call to mips32_cp0_read() should work in the same way.
The purpose of reading the debug register is to test if the DSS
bit is set and clear the SSt bit.
It is faster and easier if the SSt bit is cleared without any check.
Remark: DSS bit set only means that a debug single-step exception
ocurred, but it is not possible to step over a sdbbp instruction,
in this case DSS will not be set and the SSt bit not cleared by code.
Resume command at another address will step, so really the behavior
is not the same.
Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/950 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Tue, 30 Oct 2012 22:15:35 +0000 (23:15 +0100)]
mips: optimize mips_ejtag_step_disable() code
The code is a bit large compared to mips_ejtag_step_enable().
With the mips32 xori instruction the code can be
reused.
The number of pracc accesses are reduced from 18 to 7.
Change-Id: If3974ebd64da4461c22b089796646990e68e1b72 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/944 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sat, 1 Sep 2012 11:50:39 +0000 (13:50 +0200)]
Pic32mx.cfg: Change system clock to 8Mhz after reset-init.
As for openocd 0.6.0-rc2 the function mips32_pracc_fastdata_xfer()
should now work at a scan frequency up to 1200Khz.
Mainly usefull to increase programming speed.
Also verify_image should be slightly faster.
Change-Id: I1e9b2be73690a4597e2f6ba069c1205026850f07 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/805 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Freddie Chopin [Fri, 9 Nov 2012 22:18:23 +0000 (23:18 +0100)]
Revert "mpsse: Always perform a general reset of the MPSSE in mpsse_open()"
This reverts commit 452248af1d06cb1140b85f53ef4fdee1c746d807. This change
breaks all non-high speed adapters. The patch was not tested and did not get
any review.
Spencer Oliver [Mon, 5 Nov 2012 13:04:15 +0000 (13:04 +0000)]
target: add async algorithm timeout
An issue was observed when using an async algorithm with a target that had
not been previously reset beforehand. The target would enter a infinite
loop within target_run_flash_async_algorithm.
Add a timeout that will at least prevent this issue from happening. and also
suggest the user resets the target.
Change-Id: I5277e0d64e252d3d353e8d5bc9889a37fdc63060 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/949 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Peter Horn [Mon, 8 Oct 2012 20:06:07 +0000 (22:06 +0200)]
cortex_m: Fix single stepping will not return to debug mode sometimes
This occurs when stepping past a breakpoint on a even address with
maskisr option set to auto
With -d3 the following log message appears in this case:
"Debug : Interrupt handlers didn't complete within time,
leaving target running"
Cause : Given a breakpoint is set on the lower half word and the PC is on
the upper half word. When another breakpoint is now set on the current PC
then resuming the core will not result in a break on the newly set
breakpoint. This has been observed on a STM32F1x, STM32F2x (CM3) but not
on a STM32F0x (CM0). It's not clear if this is a STM32F1/F2 only or a
general CM3 problem.
Change-Id: I384813f3bfdf935373b5e23cdb2d7f243c70cc00 Signed-off-by: Peter Horn <peter.horn@bluewin.ch>
Reviewed-on: http://openocd.zylin.com/864 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Gianluca Renzi [Thu, 25 Oct 2012 12:29:33 +0000 (14:29 +0200)]
Added support for NXP LPC1850 Microcontroller
Added a new configuration file for LPC18xx based boards, such as
HitexLPC1850RevA Evaluation Board, and all other based on the
same microcontroller by NXP.
Gianluca Renzi [Thu, 25 Oct 2012 12:26:42 +0000 (14:26 +0200)]
Generic LPC1850 board w/ SPIFI flash.
This config file is intended as an example of how to
use the lpcspifi flash driver, but it should be functional
for most LPC1850 boards utilizing SPIFI flash.
Spencer Oliver [Fri, 26 Oct 2012 11:59:29 +0000 (12:59 +0100)]
gdb: fix broken qCRC packet handling
The rtos layer was incorrectly handling a qCRC packet as a qC packet.
Make sure we check for the qCRC packet and return unhandled so the gdb
server gets a chance to handle it.
This packet is used in the gdb compare-sections cmd.
Change-Id: I21f8e5fa7225fccd13d65cf9e40186895065a7e3 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/933 Tested-by: jenkins Reviewed-by: Matthias Blaicher <matthias@blaicher.com> Reviewed-by: Peter Stuge <peter@stuge.se>
projects / openocd / log