board/BuR/common: Introduce Network Console and common environment for it
It is often necessary to "break in" into boards bootloader commandline if
something fails or even for development purposes some parameters have to be
changed.
So we enable u-boot's CONFIG_NETCONSOLE feature.
We also modify Networksettings to apply with this new use-case.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
board/BuR/common: try to setup cpsw mac-address from the devicetree
since we have a dtb blob programmed on the board we try to setup the cpsw
interface with the programmed mac.
If this method fails, we fall back to the device-fuses.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
common/lcd: Add command for writing to lcd-display
Sometimes we do not want redirect u-boot's console to screen but anyway we want
write out some status information out of a u-boot script to the display.
So we cannot use the normal "echo ....", instead we write explicitly using
"lcdputs ..." for writing to the actual cursor position on LCD.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
common/lcd: Add command for setting cursor within lcd-console
Sometimes we do not want redirect u-boot's console to screen but anyway we want
write out some status information out of a u-boot script to the display.
To define the specific position of the string to be written, we have to set
the cursor with "setcurs" before writing.
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
drivers/video/am335x-fb: Add possibility to wait for stable power/picture
Often on boards exists a circuit which switches power on/off to LCD display.
Due to the need of limiting the in-rush current the output voltage from this
circuit rises "slowly", so it is necessary to wait a bit (VCC ramp up time)
before starting output on LCD-pins.
This time is specified in <n> ms within the panel-settings, called "pup_delay"
Further some LCDs need a couple of frames to stabilize the image on it.
We have now the possibility to wait some time after starting output on LCD.
This time is also specified in <n> ms within panel-settings, called "pon_delay"
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Rob Herring [Mon, 26 Jan 2015 15:44:18 +0000 (09:44 -0600)]
gpt: support random UUIDs without setting environment variables
Currently, an environment variable must be used to store the randomly
generated UUID for each partition. This is not necessary, so make storing
the UUID optional. Now passing uuid_disk and uuid are optional when random
UUIDs are enabled.
Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Rob Herring [Mon, 26 Jan 2015 15:43:15 +0000 (09:43 -0600)]
gpt: fix error reporting on partition table write failures
The gpt command always reports success even if writing the partition table
failed. Propagate the return value of gpt_restore so we get proper status
reported.
Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
Heiko Schocher [Thu, 5 Mar 2015 08:02:23 +0000 (09:02 +0100)]
travis.yml: some adaptions
- adapt to build with eldk-5.4
- add more targets for building with buildman:
- freescale -x arm,m68k,aarch64
- arm1136
- arm1176
- arm720t
- arm920t
- davinci
- kirkwood
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Roger Meier <r.meier@siemens.com>
Marcel Ziswiler [Wed, 4 Mar 2015 13:57:31 +0000 (14:57 +0100)]
arm: pxa: introducing cpuinfo display for marvell pxa270m
According to table 2-3 on page 87 of Marvell's latest PXA270
Specification Update Rev. I from 2010.04.19 [1] there exists a breed of
chips with a new CPU ID for PXA270M A1 stepping which our latest
Colibri PXA270 V2.4A modules actually have assembled. This patch helps
in correctly identifying those chips upon boot as well which then looks
as follows:
Simon Glass [Tue, 3 Mar 2015 15:03:02 +0000 (08:03 -0700)]
ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACK
Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f(). Adjust the
code paths in these cases to be correct. In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment). In these cases switch to CONFIG_SPL_STACK_R. In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM. In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM Tested-by: Matt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 3 Mar 2015 15:03:00 +0000 (08:03 -0700)]
arm: spl: Allow board_init_r() to run with a larger stack
At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and
environment) require a lot of stack, some boards set CONFIG_SPL_STACK to
point into SDRAM. They then set up SDRAM very early, before board_init_f(),
so that the larger stack can be used.
This is an abuse of lowlevel_init(). That function should only be used for
essential start-up code which cannot be delayed. An example of a valid use is
when only part of the SPL code is visible/executable, and the SoC must be set
up so that board_init_f() can be reached. It should not be used for SDRAM
init, console init, etc.
Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new
address before board_init_r() is called in SPL.
The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README.
Signed-off-by: Simon Glass <sjg@chromium.org>
For version 1: Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Tue, 3 Mar 2015 15:02:58 +0000 (08:02 -0700)]
arm: spl: Avoid setting up a duplicate global data structure
This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.
As an interim measure, remove it only if CONFIG_DM is not defined. This
allows us to press ahead with driver model in SPL and allow the stragglers
to catch up.
Simon Glass [Tue, 3 Mar 2015 15:02:57 +0000 (08:02 -0700)]
arm: Reduce the scope of lowlevel_init()
This function has grown into something of a monster. Some boards are setting
up a console and DRAM here in SPL. This requires global_data which should be
set up in one place (crt0.S).
There is no need for SPL to use s_init() for anything since board_init_f()
is called immediately afterwards.
board: samsung: reserve memory for the secure firmware
Since more than one board requires memory reservation
for the secure firmware, the reservation code can be
made in a common code.
Now, to reserve some part of the the last bank,
board config should define:
- CONFIG_TZSW_RESERVED_DRAM - len in bytes
- CONFIG_NR_DRAM_BANKS - number of memory banks
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Hyungwon Hwang <human.hwang@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Lukasz Majewski [Thu, 26 Feb 2015 12:23:49 +0000 (13:23 +0100)]
MAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibility
After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.
Raul Cardenas [Fri, 27 Feb 2015 17:22:06 +0000 (11:22 -0600)]
imx6: Added DEK blob generator command
Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.
During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process, is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.
Commands added
--------------
dek_blob - encapsulating DEK as a cryptgraphic blob
Commands Syntax
---------------
dek_blob src dst len
Encapsulate and create blob of a len-bits DEK at
address src and store the result at address dst.
Fabio Estevam [Mon, 23 Feb 2015 12:09:09 +0000 (09:09 -0300)]
mx35: Fix boot hang by avoiding vector relocation
Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx35
does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX35 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
Fabio Estevam [Mon, 23 Feb 2015 12:09:08 +0000 (09:09 -0300)]
mx31: Fix boot hang by avoiding vector relocation
Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx31
does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX31 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.
Masahiro Yamada [Thu, 26 Feb 2015 17:27:06 +0000 (02:27 +0900)]
ARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macros
Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs. The line
size is still 128 byte. Thus, the way size is 32KB/64KB for old/new
SoCs.
To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB. It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.
Masahiro Yamada [Thu, 26 Feb 2015 17:27:05 +0000 (02:27 +0900)]
ARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initialization
This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.
Masahiro Yamada [Thu, 26 Feb 2015 17:27:03 +0000 (02:27 +0900)]
ARM: UniPhier: switch to 1CS support card
The 3CS support card (CONFIG_DCC_MICRO_SUPPORT_CARD) used to be used
very often before, but it is recently getting a minority. Swith to
the 1CS support card (CONFIG_PFC_MICRO_SUPPORT_CARD).
Masahiro Yamada [Thu, 26 Feb 2015 17:27:02 +0000 (02:27 +0900)]
ARM: UniPhier: support 1CS support card for all the UniPhier SoCs
Two support card variants are used with UniPhier reference boards:
- 1 chip select support card (original CPLD)
- 3 chip selects support card (ARIMA-compatible CPLD)
Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.
Masahiro Yamada [Thu, 26 Feb 2015 17:27:01 +0000 (02:27 +0900)]
ARM: UniPhier: switch to xHCI for PH1-Pro4
PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously. Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.
Masahiro Yamada [Thu, 26 Feb 2015 17:26:59 +0000 (02:26 +0900)]
ARM: UniPhier: add xHCI device nodes to PH1-Pro4 device tree
Each USB port corresponds to the following IP core:
port0: xHCI (0x65a00000) SS+HS
port1: xHCI (0x65c00000) HS (SS PHY is not implemented)
port2: EHCI (0x5a800100) HS
port3: EHCI (0x5a810100) HS
Masahiro Yamada [Thu, 26 Feb 2015 17:26:54 +0000 (02:26 +0900)]
ARM: UniPhier: remove EHCI platform devices
Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers. We still keep UART platform devices because they might
be useful for SPL.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
Masahiro Yamada [Thu, 26 Feb 2015 17:26:52 +0000 (02:26 +0900)]
ARM: UniPhier: reset NAND core in SPL for non-NAND boot mode
For all the UniPhier SoCs so far, the reset signal of the NAND core
is automatically deasserted after the PLL gets stabled.
(The bit 2 of SC_RSTCTRL is default to one.)
This causes a fatal problem on the NAND controller of PH1-LD4.
For that SoC, the NAND I/O pins are not set up yet at the power-on
reset except the NAND boot mode. As a result, the NAND controller
begins automatic device scanning with wrong I/O pins and finally
hangs up.
Actually, U-Boot dies after printing "NAND:" on the console unless
the boot mode latch detected the NAND boot mode.
To work around this problem, reset the NAND core in SPL for non-NAND
boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is
deasserted again in U-Boot proper. At this time, I/O pins have been
correctly set up, the device scanning should succeed.
Masahiro Yamada [Thu, 26 Feb 2015 17:26:49 +0000 (02:26 +0900)]
ARM: UniPhier: fix SBC init code
Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.
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