]> git.sur5r.net Git - u-boot/log
u-boot
10 years agousb: tegra: combine header file
Stefan Agner [Sun, 2 Mar 2014 18:46:50 +0000 (19:46 +0100)]
usb: tegra: combine header file

Combine the Tegra USB header file into one header file for all SoCs.
Use ifdef to account for the difference, especially Tegra20 is quite
different from newer SoCs. This avoids duplication, mainly for
Tegra30 and newer devices.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agousb: tegra: fix PHY configuration
Stefan Agner [Sun, 2 Mar 2014 18:46:49 +0000 (19:46 +0100)]
usb: tegra: fix PHY configuration

On Tegra30 and later, the PTS (parallel transceiver select) and STS
(serial transceiver select) are part of the HOSTPC1_DEVLC_0 register
rather than PORTSC1_0 register. Since the reset configuration
usually matches the intended configuration, this error did not show
up on Tegra30 devices.

Also use the slightly different bit fields of first USB, (USBD) on
Tegra20 and move those definitions to the Tegra20 specific header
file.

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agousb: tegra: fix USB2 powerdown for Tegra30 and later
Stefan Agner [Sun, 2 Mar 2014 18:46:48 +0000 (19:46 +0100)]
usb: tegra: fix USB2 powerdown for Tegra30 and later

Clear the forced powerdown bit in the UTMIP_PLL_CFG2_0 register
which brings USB2 in UTMI mode to work. This was clearly missing
since the forced powerdown bit is set in reset by default for all
USB ports.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: add Jetson TK1 board
Stephen Warren [Tue, 25 Mar 2014 17:39:33 +0000 (11:39 -0600)]
ARM: tegra: add Jetson TK1 board

Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of
its design with Venice2.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: Tegra124 pinmux cleanup
Stephen Warren [Fri, 21 Mar 2014 18:29:01 +0000 (12:29 -0600)]
ARM: tegra: Tegra124 pinmux cleanup

This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.

The entries in tegra124_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

There are differences in the set of drive groups. I have validated this
against the TRM. There are differences order of pin definitions in
pinmux.c; these previously had significant mismatches with the correct
order:-( I adjusted a few entries in pinmux-config-venice2.h since the
set of legal functions for some pins was updated to match the TRM.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: Tegra114 pinmux cleanup
Stephen Warren [Fri, 21 Mar 2014 18:29:00 +0000 (12:29 -0600)]
ARM: tegra: Tegra114 pinmux cleanup

This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.

The entries in tegra114_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted a few entries in
pinmux-config-dalmore.h due to this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: Tegra30 pinmux cleanup
Stephen Warren [Fri, 21 Mar 2014 18:28:59 +0000 (12:28 -0600)]
ARM: tegra: Tegra30 pinmux cleanup

This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.

The entries in tegra30_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

This introduces a few changes to pin/group/function naming and the set of
available functions for each pin. The new values now exactly match the
TRM; the chip documentation. I adjusted one entry in
pinmux-config-cardhu.h due to this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: Tegra20 pinmux cleanup
Stephen Warren [Fri, 21 Mar 2014 18:28:58 +0000 (12:28 -0600)]
ARM: tegra: Tegra20 pinmux cleanup

This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: pinmux naming consistency fixes
Stephen Warren [Fri, 21 Mar 2014 18:28:56 +0000 (12:28 -0600)]
ARM: tegra: pinmux naming consistency fixes

Clean up the naming of pinmux-related objects:
* Refer to drive groups rather than pad groups to match the Linux kernel.
* Ensure all pinmux API types are prefixed with pmux_, values (defines)
  are prefixed with PMUX_, and functions prefixed with pinmux_.
* Modify a few type names to make their content clearer.
* Minimal changes to SoC-specific .h/.c files are made so the code still
  compiles. A separate per-SoC change will be made immediately following,
  in order to keep individual patch size down.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: reduce public pinmux API
Stephen Warren [Fri, 21 Mar 2014 18:28:55 +0000 (12:28 -0600)]
ARM: tegra: reduce public pinmux API

Remove a few unused functions from the pinmux header. They aren't
currently used, and removing them prevents any new usage from appearing.
This will ease moving to just pinmux_config_table() and
padgrp_config_table() in the future.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: pinctrl: remove duplication
Stephen Warren [Fri, 21 Mar 2014 18:28:54 +0000 (12:28 -0600)]
ARM: tegra: pinctrl: remove duplication

Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the
duplication by creating pinmux-common.c for all the identical code.

This leaves:
* arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of
  the various pins/pin groups, drive groups, and mux functions.
* arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table
  stating which pin groups support which mux functions.

The code in pinmux-common.c is semantically identical to that in the
various original pinmux.c, but had some consistency and cleanup fixes
applied during migration.

I removed the definition of struct pmux_tri_ctlr, since this is different
between SoCs (especially Tegra20 vs all others), and it's much simpler to
deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c,
and warmboot_avp.c needed updates due to this, since they previously
hijacked this struct to encode the location of some non-pinmux registers.
Now, that code simply calculates these register addresses directly using
simple and obvious math. I like this method better irrespective of the
pinmux code cleanup anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: use apb_misc.h in more places
Stephen Warren [Fri, 21 Mar 2014 18:28:53 +0000 (12:28 -0600)]
ARM: tegra: use apb_misc.h in more places

Tegra's "APB misc" register region contains various miscellaneous
registers and the Tegra pinmux registers. Some code that touches the
misc registers currently uses struct pmux_tri_ctlr, which is intended to
be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl,
which is intended to be a definition of the miscellaneous registers.
Convert all such code to use struct apb_misc_pp_ctrl, since struct
pmux_tri_ctlr goes away in the next patch.

This requires adding a missing field definition to struct
apb_misc_pp_ctrl, and moving the header into a more common location.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: prototype pinmux_init() in board.h
Stephen Warren [Fri, 21 Mar 2014 18:28:52 +0000 (12:28 -0600)]
ARM: tegra: prototype pinmux_init() in board.h

pinmux_init() is a board-level function, not a pinmux driver function.
Move the prototype to a board header rather than the driver header.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: pinctrl: make pmux_func values consistent on Tegra20
Stephen Warren [Fri, 21 Mar 2014 18:28:51 +0000 (12:28 -0600)]
ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20

For consistency with other SoCs, modify Tegra20's enum pmux_func to:

* Remove PMUX_FUNC values that aren't real
* Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0;
  this will be assumed by pinmux_set_func() in a future patch.

Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a
private define inside the driver to prevent this from causing compilaton
errors. This will be cleaned up when the pin tables are re-written in a
later patch in this series.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: pinctrl: remove vddio
Stephen Warren [Fri, 21 Mar 2014 18:28:50 +0000 (12:28 -0600)]
ARM: tegra: pinctrl: remove vddio

This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoARM: tegra: pinctrl: remove func_safe
Stephen Warren [Fri, 21 Mar 2014 18:28:49 +0000 (12:28 -0600)]
ARM: tegra: pinctrl: remove func_safe

This field isn't used anywhere, so remove it. Note that PIN() macros are
left unchanged for now, to avoid many diffs to them; later commits will
completely rewrite them just one time.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
10 years agoboard:tricorder: fixup SPL OOB layout
Andreas Bießmann [Thu, 10 Apr 2014 10:52:52 +0000 (12:52 +0200)]
board:tricorder: fixup SPL OOB layout

Commit d016dc42cedbf6102e100fa9ecb58462edfb14f8 changed the layout of BCH8 SW
on omap3 boards. We need to adopt the ecc layout for the nand_spl_simle
driver to avoid wrong ecc errors.

Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de>
Cc: Thomas Weber <thomas.weber@corscience.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
10 years agoboard:tricorder: enable omap_gpio clocks
Andreas Bießmann [Thu, 10 Apr 2014 10:52:51 +0000 (12:52 +0200)]
board:tricorder: enable omap_gpio clocks

Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de>
Cc: Thomas Weber <thomas.weber@corscience.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
10 years agoboard:tricorder: always work with valid eeprom data
Andreas Bießmann [Thu, 10 Apr 2014 10:52:50 +0000 (12:52 +0200)]
board:tricorder: always work with valid eeprom data

Commit 890880583d84607e36b52a785a96b167728bbf73 introduced EEPROM parsing and
board detection but faild to return a valid tricorder_eeprom struct for backup
case.  When pressing S200 while reading EEPROM we ignore the value. We
returned falsely a tricorder_eeprom struct with uninitialized data which is
just garbage.
Initialize it by zeroing the whole structure.

Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de>
Cc: Thomas Weber <thomas.weber@corscience.de>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
10 years agoarm:board:trats2:FIX: Clear INFORM4 and INFORM5 registers at correct boot
Łukasz Majewski [Wed, 9 Apr 2014 13:09:44 +0000 (15:09 +0200)]
arm:board:trats2:FIX: Clear INFORM4 and INFORM5 registers at correct boot

During switch to device tree, commit 1ecab0f has removed this code.

INFORM4 and INFORM5 registers are used by TRATS2 first stage bootloader for
providing recovery. For normal operation, those two must be cleared out.

This error emerges when one force reset from u-boot's command line for
three times.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agokbuild: fix a bug in regeneration of linker scripts
Masahiro Yamada [Wed, 9 Apr 2014 11:10:43 +0000 (20:10 +0900)]
kbuild: fix a bug in regeneration of linker scripts

In some use cases, SPL linker script was not updated even when
it should be.

For instance,

  $ make tricoder_config all
    [ build complete ]
  ... modify include/configs/tricoder.h
  $ make

spl/u-boot-spl.lds should be updated in this case, but it wasn't.

To fix this problem, linker scripts generation should be handled
by $(call if_changed_dep,...) rather than by $(call if_changed,...).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reported-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
10 years agoMerge branch 'u-boot/master' into 'u-boot-arm/master'
Albert ARIBAUD [Tue, 8 Apr 2014 07:25:08 +0000 (09:25 +0200)]
Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
include/configs/trats.h
include/configs/trats2.h
include/mmc.h

10 years agoarm64 patch: gicv3 support
David Feng [Fri, 14 Mar 2014 06:26:27 +0000 (14:26 +0800)]
arm64 patch: gicv3 support

This patch add gicv3 support to uboot armv8 platform.

Changes for v2:
  - rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S
  - move smp_kick_all_cpus() from gic.S to start.S, it would be
    implementation dependent.
  - Each core initialize it's own ReDistributor instead of master
    initializeing all ReDistributors. This is advised by arnab.basu
    <arnab.basu@freescale.com>.

Signed-off-by: David Feng <fenghua@phytium.com.cn>
10 years agobootstage: arm: fix fdt stashing code
Mela Custodio [Wed, 19 Feb 2014 15:16:56 +0000 (00:16 +0900)]
bootstage: arm: fix fdt stashing code

The conditional is using a variable that is not defined.

Signed-off-by: Rommel G Custodio <sessyargc+u-boot@gmail.com>
10 years agoARMv8: fix bug for flush data cache by set/way
Leo Yan [Mon, 31 Mar 2014 01:50:35 +0000 (09:50 +0800)]
ARMv8: fix bug for flush data cache by set/way

When flush the d$ with set/way instruction, it need calculate the way's
offset = log2(Associativity); but in current uboot's code, it use below
formula to calculate the offset: log2(Associativity * 2 - 1), so finally
it cannot flush data cache properly.

Signed-off-by: Leo Yan <leoy@marvell.com>
10 years agoarmv8: Flush dcache before switching to EL2
York Sun [Mon, 31 Mar 2014 21:40:32 +0000 (14:40 -0700)]
armv8: Flush dcache before switching to EL2

For ARMv8, U-boot has been running at EL3 with cache and MMU enabled.
Without proper setup for EL2, cache and MMU are both disabled (out of
reset). Before switching, we need to flush the dcache to make sure the
data is in the main memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: David.Feng <fenghua@phytium.com.cn>
10 years agoarm: vf610: fix double iomux configuration for vf610twr board
Marcel Ziswiler [Tue, 11 Mar 2014 17:44:00 +0000 (18:44 +0100)]
arm: vf610: fix double iomux configuration for vf610twr board

Get rid of double VF610_PAD_DDR_A15__DDR_A_15 iomux configuration.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
10 years agoarm: vf610: add enet1 support
Marcel Ziswiler [Tue, 11 Mar 2014 17:43:59 +0000 (18:43 +0100)]
arm: vf610: add enet1 support

This patch contains several changes required for second Ethernet
(enet1/RMII1) port on vf610
- ANADIG PLL5 control definitions required for Ethernet RMII1 clock
- Secondary Ethernet (enet1) MAC RMII1 base address definition
- RMII1 iomux definitions
- VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for
  internal (e.g. crystal-less) Ethernet clocking.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner <stefan@agner.ch>
10 years agoarm: vf610: add uart0 clock/iomux definitions
Marcel Ziswiler [Tue, 11 Mar 2014 17:43:58 +0000 (18:43 +0100)]
arm: vf610: add uart0 clock/iomux definitions

Add CCM_CCGR0_UART0_CTRL_MASK clock definition and add TX/RX iomux
definitions for UART0 (aka. SCI0).

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner <stefan@agner.ch>
10 years agoarm: vf610: fix anadig register struct
Marcel Ziswiler [Tue, 11 Mar 2014 17:43:57 +0000 (18:43 +0100)]
arm: vf610: fix anadig register struct

The anadig_reg structure started at the wrong offset (fixed by adding
reserved_0x000[4]), was missing some reserved field required for
alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl)
and further contained a too short reserved field causing further miss-
alignment (reserved_0x0C4[7]). Also, rename all the reserved fields
and using a memory offset based scheme for.

Discovered and tested by temporarily putting the following debug
instrumentation into board_init():
    struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
    printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl);
    printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl);

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[stefan@agner.ch: regrouped patch]
Signed-off-by: Stefan Agner <stefan@agner.ch>
10 years agobuild:arm: Remove setting of CROSS_COMPILE environment variable
Łukasz Majewski [Tue, 18 Mar 2014 15:46:48 +0000 (16:46 +0100)]
build:arm: Remove setting of CROSS_COMPILE environment variable

After Kbuild introduction, the CROSS_COMPILE environment variable has been
set to some default value (prefix arm-linux-).

This shall be removed since it breaks building u-boot for native arm target
(like qemu ARM).
Moreover not all compilers have arm-linux- prefix.

Additionally the u-boot cross compiles with CROSS_COMPILE= set explicitly-
e.g.:
CROSS_COMPILE=/ .... /arm-v7a-linux-gnueabi- make

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
10 years agoMerge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Albert ARIBAUD [Mon, 7 Apr 2014 17:13:42 +0000 (19:13 +0200)]
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

10 years agoMX6: Enable ARM errata workaround 794072 and 761320
Nitin Garg [Wed, 2 Apr 2014 13:55:03 +0000 (08:55 -0500)]
MX6: Enable ARM errata workaround 794072 and 761320

Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 794072 and 761320.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
10 years agoARM: Add workaround for Cortex-A9 errata 761320
Nitin Garg [Wed, 2 Apr 2014 13:55:02 +0000 (08:55 -0500)]
ARM: Add workaround for Cortex-A9 errata 761320

Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
10 years agoARM: Add workaround for Cortex-A9 errata 794072
Nitin Garg [Wed, 2 Apr 2014 13:55:01 +0000 (08:55 -0500)]
ARM: Add workaround for Cortex-A9 errata 794072

A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
10 years agoarmv8/cache: Change cache invalidate and flush function
York Sun [Wed, 26 Feb 2014 21:26:04 +0000 (13:26 -0800)]
armv8/cache: Change cache invalidate and flush function

When SoC first boots up, we should invalidate the cache but not flush it.
We can use the same function for invalid and flush mostly, with a wrapper.

Invalidating large cache can ben slow on emulator, so we postpone doing
so until I-cache is enabled, and before enabling D-cache.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
10 years agoarmv8/cache: Flush D-cache, invalidate I-cache for relocation
York Sun [Wed, 26 Feb 2014 21:26:03 +0000 (13:26 -0800)]
armv8/cache: Flush D-cache, invalidate I-cache for relocation

If D-cache is enabled, we need to flush it, and invalidate i-cache before
jumping to the new location. This should be done right after relocation.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
10 years agoarmv8/cache: Consolidate setting for MAIR and TCR
York Sun [Wed, 26 Feb 2014 21:26:02 +0000 (13:26 -0800)]
armv8/cache: Consolidate setting for MAIR and TCR

Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
sub-architecture.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
10 years agoarm: Handle .gnu.hash section in ldscripts
Andreas Färber [Mon, 27 Jan 2014 04:48:11 +0000 (05:48 +0100)]
arm: Handle .gnu.hash section in ldscripts

Avoids "could not find output section .gnu.hash" ld.bfd errors on openSUSE.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
10 years agosocfpga: Adding Clock Manager driver
Chin Liang See [Wed, 5 Mar 2014 04:13:53 +0000 (22:13 -0600)]
socfpga: Adding Clock Manager driver

Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
10 years agoRevert "Start the deprecation process for generic board"
Tom Rini [Fri, 4 Apr 2014 14:09:19 +0000 (10:09 -0400)]
Revert "Start the deprecation process for generic board"

We've run into a non-trivial conversion to CONFIG_SYS_GENERIC_BOARD so
we'll postpone this notice until right after v2014.04 is out.

This reverts commit 36c4b1d98059244c34ec3327d9cc9f3c552fd01b.

Signed-off-by: Tom Rini <trini@ti.com>
10 years agoarm: mxs: Add support for generating signed BootStream
Marek Vasut [Thu, 3 Apr 2014 17:12:21 +0000 (19:12 +0200)]
arm: mxs: Add support for generating signed BootStream

This patch adds the groundwork for generating signed BootStream, which
can be used by the HAB library in i.MX28. We are adding a new target,
u-boot-signed.sb , since the process for generating regular non-signed
BootStream is much easier. Moreover, the signed bootstream depends on
external _proprietary_ _binary-only_ tool from Freescale called 'cst',
which is available only under NDA.

To make things even uglier, the CST or HAB mandates a kind-of circular
dependency. The problem is, unlike the regular IVT, which is generated
by mxsimage, the IVT for signed boot must be generated by hand here due
to special demands of the CST. The U-Boot binary (or SPL binary) and IVT
are then signed by the CST as a one block. But here is the problem. The
size of the entire image (U-Boot, IVT, CST blocks) must be appended at
the end of IVT. But the size of the entire image is not known until the
CST has finished signing the U-Boot and IVT. We solve this by expecting
the CST block to be always 3904B (which it is in case two files, U-Boot
and the hand-made IVT, are signed in the CST block).

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
10 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm into master
Stefano Babic [Fri, 4 Apr 2014 09:35:30 +0000 (11:35 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-arm into master

Conflicts:
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>
10 years agoRevert "arm: mxs: Add support for generating signed BootStream"
Stefano Babic [Fri, 4 Apr 2014 09:29:29 +0000 (11:29 +0200)]
Revert "arm: mxs: Add support for generating signed BootStream"

This reverts commit 53e6b14e037c9f72e6d03244c32d8d597e2e0234.

Patch does not merge anymore with u-boot-arm and must be rebased.

Signed-off-by: Stefano Babic <sbabic@denx.de>
10 years agotrats/trats2: enable CONFIG_RANDOM_UUID
Przemyslaw Marczak [Wed, 2 Apr 2014 08:20:07 +0000 (10:20 +0200)]
trats/trats2: enable CONFIG_RANDOM_UUID

This change enables automatically uuid generation by command gpt.
In case of updating partitions layout user don't need to care about
generate uuid manually.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: trini@ti.com
10 years agocmd:gpt: randomly generate each partition uuid if undefined
Przemyslaw Marczak [Wed, 2 Apr 2014 08:20:06 +0000 (10:20 +0200)]
cmd:gpt: randomly generate each partition uuid if undefined

Changes:
- randomly generate partition uuid if any is undefined and CONFIG_RAND_UUID
  is defined
- print debug info about set/unset/generated uuid
- update doc/README.gpt

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Tom Rini <trini@ti.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
10 years agonew commands: uuid and guid - generate random unique identifier
Przemyslaw Marczak [Wed, 2 Apr 2014 08:20:05 +0000 (10:20 +0200)]
new commands: uuid and guid - generate random unique identifier

Those commands basis on implementation of random UUID generator version 4
which is described in RFC4122. The same algorithm is used for generation
both ids but string representation is different as below.

char:  0        9    14   19   24         36
       xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
UUID:     be     be   be   be       be
GUID:     le     le   le   be       be

Commands usage:
- uuid [<varname>]
- guid [<varname>]

The result is saved in environment as a "varname" variable if argument is given,
if not then it is printed.

New config:
- CONFIG_CMD_UUID

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: trini@ti.com
10 years agolib: uuid: add functions to generate UUID version 4
Przemyslaw Marczak [Wed, 2 Apr 2014 08:20:04 +0000 (10:20 +0200)]
lib: uuid: add functions to generate UUID version 4

This patch adds support to generate UUID (Universally Unique Identifier)
in version 4 based on RFC4122, which is randomly.

Source: https://www.ietf.org/rfc/rfc4122.txt

Changes:
- new configs:
  - CONFIG_LIB_UUID for compile lib/uuid.c
  - CONFIG_RANDOM_UUID for functions gen_rand_uuid() and gen_rand_uuid_str()
- add configs dependency to include/config_fallbacks.h for lib uuid.

lib/uuid.c:
- add gen_rand_uuid() - this function writes 16 bytes len binary representation
  of UUID v4 to the memory at given address.

- add gen_rand_uuid_str() - this function writes 37 bytes len hexadecimal
  ASCII string representation of UUID v4 to the memory at given address.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
[trini: Add CONFIG_EFI_PARTITION to fallbacks]
Signed-off-by: Tom Rini <trini@ti.com>
10 years agolib: uuid: code refactor for proper maintain between uuid bin and string
Przemyslaw Marczak [Wed, 2 Apr 2014 08:20:03 +0000 (10:20 +0200)]
lib: uuid: code refactor for proper maintain between uuid bin and string

Changes in lib/uuid.c to:
- uuid_str_to_bin()
- uuid_bin_to_str()

New parameter is added to specify input/output string format in listed functions
This change allows easy recognize which UUID type is or should be stored in given
string array. Binary data of UUID and GUID is always stored in big endian, only
string representations are different as follows.

String byte: 0                                  36
String char: xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
string UUID:    be     be   be   be       be
string GUID:    le     le   le   be       be

This patch also updates functions calls and declarations in a whole code.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: trini@ti.com
10 years agopart_efi: move uuid<->string conversion functions into lib/uuid.c
Przemyslaw Marczak [Wed, 2 Apr 2014 08:20:02 +0000 (10:20 +0200)]
part_efi: move uuid<->string conversion functions into lib/uuid.c

This commit introduces cleanup for uuid library.
Changes:
- move uuid<->string conversion functions into lib/uuid.c so they can be
  used by code outside part_efi.c.
- rename uuid_string() to uuid_bin_to_str() for consistency with existing
  uuid_str_to_bin()
- add an error return code to uuid_str_to_bin()
- update existing code to the new library functions.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: trini@ti.com
10 years agoahci: Fix data abort on multiple scsi resets.
Roger Quadros [Tue, 1 Apr 2014 14:26:40 +0000 (17:26 +0300)]
ahci: Fix data abort on multiple scsi resets.

Commit 2faf5fb82ed6 introduced a regression that causes a data
abort when running scsi init followed by scsi reset.

There are 2 problems with the original commit
1) ALLOC_CACHE_ALIGN_BUFFER() allocates memory on the stack but is
assigned to ataid[port] and used by other functions.
2) The function ata_scsiop_inquiry() tries to free memory which was
never allocated on the heap.

Fix these problems by using tmpid as a temporary cache aligned buffer.
Allocate memory separately for ataid[port] and re-use it if required.

Fixes: 2faf5fb82ed6 (ahci: Fix cache align error messages)
Reported-by: Eli Nidam <elini@marvell.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
10 years agoconfig:trats2: Change u-boot's TEXT_BASE from 0x78100000 to 0x43e00000
Łukasz Majewski [Wed, 19 Mar 2014 13:47:06 +0000 (14:47 +0100)]
config:trats2: Change u-boot's TEXT_BASE from 0x78100000 to 0x43e00000

The u-boot's image TEXT_BASE needs to be changed to 0x43e00000 from 0x78100000.

This change provides compatibility with other trats2 (RD_PQ) devices
(http://download.tizen.org/releases/system/).

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
10 years agommc:eSDHC: Workaround for data timeout issue on Txxx SoC
Haijun.Zhang [Tue, 18 Mar 2014 09:04:23 +0000 (17:04 +0800)]
mmc:eSDHC: Workaround for data timeout issue on Txxx SoC

1. The Data timeout counter value in eSDHC_SYSCTL register is
not working as it should be, so add quirks to enable this
workaround to fix it to the max value 0xE.

2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.

* Update of patch for change mmc interface by
Pantelis Antoniou <panto@antoniou-consulting.com>

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
10 years agommc: fsl_esdhc: add controller reset in case of data related errors too
Andrew Gabbasov [Mon, 24 Mar 2014 07:41:06 +0000 (02:41 -0500)]
mmc: fsl_esdhc: add controller reset in case of data related errors too

The controller reset is performed now if command error occurs.
This commit adds the reset for the case of data related errors too.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
10 years agommc: fsl_esdhc: fix calculation of timeout for data transactions
Andrew Gabbasov [Mon, 24 Mar 2014 07:40:41 +0000 (02:40 -0500)]
mmc: fsl_esdhc: fix calculation of timeout for data transactions

Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
10 years agommc: Add 'mmc rst-function' sub-command
Tom Rini [Fri, 7 Feb 2014 19:15:20 +0000 (14:15 -0500)]
mmc: Add 'mmc rst-function' sub-command

Some eMMC chips may need the RST_n_FUNCTION bit set to a non-zero value
in order for warm reset of the system to work.  Details on this being
required will be part of the eMMC datasheet.  Also add using this
command to the dra7xx README.

* Whitespace fix by panto

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
10 years agommc: sh_mmcif: Fix warning by unused variable
Nobuhiro Iwamatsu [Mon, 31 Mar 2014 05:54:29 +0000 (14:54 +0900)]
mmc: sh_mmcif: Fix warning by unused variable

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
10 years agommc: sh_mmcif: Fix compile error
Nobuhiro Iwamatsu [Mon, 31 Mar 2014 05:54:28 +0000 (14:54 +0900)]
mmc: sh_mmcif: Fix compile error

BY commit "mmc: Split mmc struct, rework mmc initialization (v2)",
sh_mmcif has compile error. This fixes compile error.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Pantelis Antoniou <panto@antoniou-consulting.com>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
10 years agomx6: add example DTB for mx6qsabreauto
Stefano Babic [Mon, 31 Mar 2014 07:50:36 +0000 (09:50 +0200)]
mx6: add example DTB for mx6qsabreauto

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
10 years agoimx: add rules for U-Boot DTB support
Stefano Babic [Mon, 31 Mar 2014 07:50:35 +0000 (09:50 +0200)]
imx: add rules for U-Boot DTB support

Signed-off-by: Stefano Babic <sbabic@denx.de>
10 years agomxs: fix warning in SPL with console support
Stefano Babic [Wed, 2 Apr 2014 08:42:06 +0000 (10:42 +0200)]
mxs: fix warning in SPL with console support

Signed-off-by: Stefano Babic <sbabic@denx.de>
10 years agoMerge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Albert ARIBAUD [Wed, 2 Apr 2014 04:43:09 +0000 (06:43 +0200)]
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

10 years agoarm: mxs: Add serial console support into SPL
Marek Vasut [Wed, 19 Mar 2014 01:21:36 +0000 (02:21 +0100)]
arm: mxs: Add serial console support into SPL

Add support for serial console into the i.MX23/i.MX28 SPL. A full,
uncrippled serial console support comes very helpful when debugging
various spectacular hardware bringup issues early in the process.
Because we do not use SPL framework, but have our own minimalistic
SPL, which is compatible with the i.MX23/i.MX28 BootROM, we do not
use preloader_console_init(), but instead use a similar function to
start the console. Nonetheless, to avoid blowing up the size of the
SPL binary, this support is enabled only if CONFIG_SPL_SERIAL_SUPPORT
is defined, which is disabled by default.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
10 years agoarm: mxs: Properly set GD pointer in SPL
Marek Vasut [Wed, 19 Mar 2014 01:21:35 +0000 (02:21 +0100)]
arm: mxs: Properly set GD pointer in SPL

Set the GD pointer in the SPL to a defined symbol so various
functions from U-Boot can be used without adverse side effects.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
10 years agoPrepare v2014.04-rc3 v2014.04-rc3
Tom Rini [Mon, 31 Mar 2014 19:24:48 +0000 (15:24 -0400)]
Prepare v2014.04-rc3

Signed-off-by: Tom Rini <trini@ti.com>
10 years agoarm: mx5: Avoid hardcoding memory sizes on M53EVK
Marek Vasut [Fri, 28 Mar 2014 07:31:01 +0000 (08:31 +0100)]
arm: mx5: Avoid hardcoding memory sizes on M53EVK

The DRAM size can be easily detected at runtime on i.MX53. Implement
such detection on M53EVK and adjust the rest of the macros accordingly
to use the detected values.

An important thing to note here is that we had to override the function
for trimming the effective DRAM address, get_effective_memsize(). That
is because the function uses CONFIG_MAX_MEM_MAPPED as the upper bound of
the available DRAM and we don't have gd->bd->bi_dram[0].size set up at
the time the function is called, thus we cannot put this into the macro
CONFIG_MAX_MEM_MAPPED . Instead, we use custom override where we use the
size of the first DRAM block which we just detected.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
10 years agoarm: mx5: Fix memory slowness on M53EVK
Marek Vasut [Fri, 28 Mar 2014 07:31:00 +0000 (08:31 +0100)]
arm: mx5: Fix memory slowness on M53EVK

Fix memory access slowness on i.MX53 M53EVK board. Let us inspect the
issue: First of all, the i.MX53 CPU has two memory banks mapped at
0x7000_0000 and 0xb000_0000 and each of those can hold up to 1GiB of
DRAM memory. Notice that the memory area is not continuous. On M53EVK,
each of the banks contain 512MiB of DRAM, which makes a total of 1GiB
of memory available to the system.

The problem is how the relocation of U-Boot is treated on i.MX53 . The
U-Boot is placed at the ((start of first DRAM partition) + (gd->ram_size)) .
This in turn poses a problem, since in our case, the gd->ram_size is 1GiB,
the first DRAM bank starts at 0x7000_0000 and contains 512MiB of memory.
Thus, with this algorithm, U-Boot is placed at offset:

    0x7000_0000 + 1GiB - sizeof(u-boot and some small margin)

This is past the DRAM available in the first bank on M53EVK, but is still
within the address range of the first DRAM bank. Because of the memory
wrap-around, the data can still be read and written to this area, but the
access is much slower.

There were two ideas how to solve this problem, first was to map both of
the available DRAM chunks next to one another by using MMU, second was to
define CONFIG_VERY_BIG_RAM and CONFIG_MAX_MEM_MAPPED to size of the memory
in the first DRAM bank. We choose the later because it turns out the former
is not applicable afterall. The former cannot be used in case Linux kernel
was loaded into the second DRAM bank area, which would be remapped and one
would try booting the kernel, since at some point before the kernel is started,
the MMU would be turned off, which would destroy the mapping and hang the
system.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
10 years agoarm: mx5: Avoid hardcoding memory sizes on MX53QSB
Marek Vasut [Fri, 28 Mar 2014 07:30:59 +0000 (08:30 +0100)]
arm: mx5: Avoid hardcoding memory sizes on MX53QSB

The DRAM size can be easily detected at runtime on i.MX53. Implement
such detection on MX53QSB and adjust the rest of the macros accordingly
to use the detected values.

An important thing to note here is that we had to override the function
for trimming the effective DRAM address, get_effective_memsize(). That
is because the function uses CONFIG_MAX_MEM_MAPPED as the upper bound of
the available DRAM and we don't have gd->bd->bi_dram[0].size set up at
the time the function is called, thus we cannot put this into the macro
CONFIG_MAX_MEM_MAPPED . Instead, we use custom override where we use the
size of the first DRAM block which we just detected.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
10 years agoarm: mx5: Fix memory slowness on MX53QSB
Marek Vasut [Fri, 28 Mar 2014 07:30:58 +0000 (08:30 +0100)]
arm: mx5: Fix memory slowness on MX53QSB

Fix memory access slowness on i.MX53 MX53QSB board. Let us inspect the
issue: First of all, the i.MX53 CPU has two memory banks mapped at
0x7000_0000 and 0xb000_0000 and each of those can hold up to 1GiB of
DRAM memory. Notice that the memory area is not continuous. On MX53QSB,
each of the banks contain 512MiB of DRAM, which makes a total of 1GiB
of memory available to the system.

The problem is how the relocation of U-Boot is treated on i.MX53 . The
U-Boot is placed at the ((start of first DRAM partition) + (gd->ram_size)) .
This in turn poses a problem, since in our case, the gd->ram_size is 1GiB,
the first DRAM bank starts at 0x7000_0000 and contains 512MiB of memory.
Thus, with this algorithm, U-Boot is placed at offset:

    0x7000_0000 + 1GiB - sizeof(u-boot and some small margin)

This is past the DRAM available in the first bank on MX53QSB, but is still
within the address range of the first DRAM bank. Because of the memory
wrap-around, the data can still be read and written to this area, but the
access is much slower.

There were two ideas how to solve this problem, first was to map both of
the available DRAM chunks next to one another by using MMU, second was to
define CONFIG_VERY_BIG_RAM and CONFIG_MAX_MEM_MAPPED to size of the memory
in the first DRAM bank. We choose the later because it turns out the former
is not applicable afterall. The former cannot be used in case Linux kernel
was loaded into the second DRAM bank area, which would be remapped and one
would try booting the kernel, since at some point before the kernel is started,
the MMU would be turned off, which would destroy the mapping and hang the
system.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
10 years agoARM: mx6: Add PCIe on SabreSDP
Marek Vasut [Sun, 23 Mar 2014 21:45:41 +0000 (22:45 +0100)]
ARM: mx6: Add PCIe on SabreSDP

Add support for PCIe on MX6 SabreSDP board and enable the support
in the config file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Liu Ying <Ying.Liu@freescale.com>
10 years agopci: mx6: Implement power callback
Marek Vasut [Sun, 23 Mar 2014 21:45:40 +0000 (22:45 +0100)]
pci: mx6: Implement power callback

Implement a callback to toggle the slot power supply. The callback
can be overriden in case some more complex power supply for the slot
was implemented in hardware, yet for the usual case, one can define
a GPIO which toggles the power to the slot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Liu Ying <Ying.Liu@freescale.com>
10 years agoARM: mx6: Disable PCIe on SABRE Lite/Nitrogen6x
Eric Nelson [Sat, 22 Mar 2014 15:17:09 +0000 (08:17 -0700)]
ARM: mx6: Disable PCIe on SABRE Lite/Nitrogen6x

Use of PCIe on SABRE Lite and Nitrogen6x boards
is atypical and requires the use of custom daughter
boards.

Use in U-Boot is even rarer, so this patch removes it from
the standard configuration.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
10 years agowoodburn_sd: Remove CONFIG_BOOT_INTERNAL
Fabio Estevam [Sun, 16 Mar 2014 21:20:09 +0000 (18:20 -0300)]
woodburn_sd: Remove CONFIG_BOOT_INTERNAL

CONFIG_BOOT_INTERNAL is not used anywhere, so let's remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
10 years agoARM: mxs: Add OCOTP driver
Marek Vasut [Thu, 6 Mar 2014 00:52:03 +0000 (01:52 +0100)]
ARM: mxs: Add OCOTP driver

Add yet another OCOTP driver for this i.MX family. This time, it's a driver for
the OCOTP variant found in the i.MX23 and i.MX28. This version of OCOTP is too
different from the i.MX6 one that I could not use the mxc_ocotp.c driver without
making it into a big pile of #ifdef . This driver implements the regular fuse
command interface, but due to the IP blocks' limitation, we support only READ
and PROG functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
10 years agoarm: mxs: Add support for generating signed BootStream
Marek Vasut [Wed, 5 Mar 2014 19:01:14 +0000 (20:01 +0100)]
arm: mxs: Add support for generating signed BootStream

This patch adds the groundwork for generating signed BootStream, which
can be used by the HAB library in i.MX28. We are adding a new target,
u-boot-signed.sb , since the process for generating regular non-signed
BootStream is much easier. Moreover, the signed bootstream depends on
external _proprietary_ _binary-only_ tool from Freescale called 'cst',
which is available only under NDA.

To make things even uglier, the CST or HAB mandates a kind-of circular
dependency. The problem is, unlike the regular IVT, which is generated
by mxsimage, the IVT for signed boot must be generated by hand here due
to special demands of the CST. The U-Boot binary (or SPL binary) and IVT
are then signed by the CST as a one block. But here is the problem. The
size of the entire image (U-Boot, IVT, CST blocks) must be appended at
the end of IVT. But the size of the entire image is not known until the
CST has finished signing the U-Boot and IVT. We solve this by expecting
the CST block to be always 3904B (which it is in case two files, U-Boot
and the hand-made IVT, are signed in the CST block).

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
10 years agoarm: mxs: Adjust the load address of U-Boot and SPL for HAB
Marek Vasut [Wed, 5 Mar 2014 19:01:13 +0000 (20:01 +0100)]
arm: mxs: Adjust the load address of U-Boot and SPL for HAB

When using HAB, there are additional special requirements on the placement of
U-Boot and the U-Boot SPL in memory. To fullfill these, this patch moves the
U-Boot binary a little further from the begining of the DRAM, so the HAB CST
and IVT can be placed in front of the U-Boot binary. This is necessary, since
both the U-Boot and the IVT must be contained in single CST signature. To
make things worse, the IVT must be concatenated with one more entry at it's
end, that is the length of the entire CST signature, IVT and U-Boot binary
in memory. By placing the blocks in this order -- CST, IVT, U-Boot, we can
easily align them all and then produce the length field as needed.

As for the SPL, on i.MX23/i.MX28, the SPL size is limited to 32 KiB, thus
we place the IVT at 0x8000 offset, CST right past IVT and claim the size
is correct. The HAB library accepts this setup.

Finally, to make sure the vectoring in SPL still works even after moving
the SPL from 0x0 to 0x1000, we add a small function which copies the
vectoring code and tables to 0x0. This is fine, since the vectoring code
is position independent.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
10 years agoKbuild: allow building tools without board configuration
Masahiro Yamada [Mon, 31 Mar 2014 08:33:51 +0000 (17:33 +0900)]
Kbuild: allow building tools without board configuration

Prior to Kbuild, U-Boot could build under tools/ directory
withour configuring for a specific board.

That feature was lost when switching to Kbuild.

This patch revives it again by adding a make target "tools-only".

Usage:
  $ make tools-only

Neither board configuration nor cross compiler are required to
build host tools.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
10 years agotegra: fix Makefile to pass per-file CFLAGS
Masahiro Yamada [Mon, 31 Mar 2014 05:23:15 +0000 (14:23 +0900)]
tegra: fix Makefile to pass per-file CFLAGS

Since Kbuild was introduced, warmboot_avp.o has been compiled
without -march=armv4t.

Makefile should be adjusted to pass a per-file option.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
10 years agoboard: enable 32kHz RTC OSC at B&R boards
Hannes Petermaier [Thu, 27 Mar 2014 09:37:36 +0000 (10:37 +0100)]
board: enable 32kHz RTC OSC at B&R boards

Since RTC-Clock is needed on all B&R boards, the OSC will be enabled
wihtin SPL-stage.

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
10 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Mon, 31 Mar 2014 12:29:35 +0000 (08:29 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

10 years agodrivers: i2c: delete an unused source file
Masahiro Yamada [Mon, 31 Mar 2014 04:03:30 +0000 (13:03 +0900)]
drivers: i2c: delete an unused source file

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
10 years agoboard: ecovec: fix USB0 clock enable
Baruch Siach [Mon, 17 Mar 2014 14:14:54 +0000 (16:14 +0200)]
board: ecovec: fix USB0 clock enable

Enable USB0 clock by resetting bit 20 of MSTPCR2. Leave other bits unchanged.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
10 years agoboard: ecovec: fix debug LEDs pin direction
Baruch Siach [Mon, 17 Mar 2014 14:14:53 +0000 (16:14 +0200)]
board: ecovec: fix debug LEDs pin direction

All pins should be output.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
10 years agoblackfin: mmc: Correct mmc_host_is_spi and bfin_sdh.c
Tom Rini [Fri, 28 Mar 2014 20:55:29 +0000 (16:55 -0400)]
blackfin: mmc: Correct mmc_host_is_spi and bfin_sdh.c

In the recent mmc cleanup, the mmc_host_is_spi macro was broken and
bfin_sdh.c had mmc->bus_width turned into mmc_bus_width(mmc), both of
which were incorrect.

Signed-off-by: Tom Rini <trini@ti.com>
10 years agoam335x_evm: Drop CONFIG_SPL_ETH_SUPPORT from default build
Tom Rini [Wed, 26 Mar 2014 19:56:07 +0000 (15:56 -0400)]
am335x_evm: Drop CONFIG_SPL_ETH_SUPPORT from default build

On the boards this target supports this option is either non possible
without hardware mods (Beaglebone White/Black) or not supported due to
board design.  Drop this and regain some space.

Signed-off-by: Tom Rini <trini@ti.com>
10 years agoam335x_evm: Clarify when we build board_eth_init
Tom Rini [Wed, 26 Mar 2014 19:53:12 +0000 (15:53 -0400)]
am335x_evm: Clarify when we build board_eth_init

If we build this function in cases where we would be discarding it
anyhow we still end up with maybe unused warnings.  Rather than litter
the function with __maybe_unused, just spell out when to build it.

Signed-off-by: Tom Rini <trini@ti.com>
10 years agokbuild: fix bugs in cleaning targets
Masahiro Yamada [Fri, 28 Mar 2014 05:55:02 +0000 (14:55 +0900)]
kbuild: fix bugs in cleaning targets

"make clean", "make clobber", "make mrproper" and "make distclean"
missed to clean-up some files when they were run with
O=<some_dir> option.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reported-by: Wolfgang Denk <wd@denx.de>
10 years agokbuild: create a build directory automatically for out-of-tree build
Masahiro Yamada [Mon, 24 Mar 2014 04:55:27 +0000 (13:55 +0900)]
kbuild: create a build directory automatically for out-of-tree build

Prior to Kbuild, the build system created a build directory,
when it did not exist, for out-of-tree build.

This feature was dropped when we switched to Kbuild
because many of lines in makefiles were copied from Linux Kernel.
(In Linux Kernel, we have to create a build directory by ourselves
before starting build.)

That feature seems worth reviving for less typing
even if our code and Linux Kernel diverge.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
10 years agoStart the deprecation process for generic board
Simon Glass [Sat, 22 Mar 2014 23:14:51 +0000 (17:14 -0600)]
Start the deprecation process for generic board

We should move forward to remove the old board init code. Add a
prominent message to encourage maintainers to get started on this
work.

Signed-off-by: Simon Glass <sjg@chromium.org>
10 years agotrats/trats2: enable exynos ace sha subsystem and hardware based lib rand
Przemyslaw Marczak [Tue, 25 Mar 2014 09:58:22 +0000 (10:58 +0100)]
trats/trats2: enable exynos ace sha subsystem and hardware based lib rand

This allows to use exynos random number generator by enabling configs:
- CONFIG_EXYNOS_ACE_SHA
- CONFIG_LIB_HW_RAND

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
cc: Piotr Wilczek <p.wilczek@samsung.com>
cc: Minkyu Kang <mk7.kang@samsung.com>

10 years agodrivers: crypto: ace_sha: add implementation of hardware based lib rand
Przemyslaw Marczak [Tue, 25 Mar 2014 09:58:21 +0000 (10:58 +0100)]
drivers: crypto: ace_sha: add implementation of hardware based lib rand

This patch adds implementation of rand library based on hardware random
number generator of security subsystem in Exynos SOC.

This library includes:
- srand()  - used for seed hardware block
- rand()   - returns random number
- rand_r() - the same as above with given seed

which depends on CONFIG_EXYNOS_ACE_SHA and CONFIG_LIB_HW_RAND.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
cc: Akshay Saraswat <akshay.s@samsung.com>
cc: ARUN MANKUZHI <arun.m@samsung.com>
cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
10 years agocpu: exynos4: add ace sha base address
Przemyslaw Marczak [Tue, 25 Mar 2014 09:58:20 +0000 (10:58 +0100)]
cpu: exynos4: add ace sha base address

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
10 years agolib: rand: introduce new configs: CONFIG_LIB_RAND and CONFIG_LIB_HW_RAND
Przemyslaw Marczak [Tue, 25 Mar 2014 09:58:19 +0000 (10:58 +0100)]
lib: rand: introduce new configs: CONFIG_LIB_RAND and CONFIG_LIB_HW_RAND

New configs:
- CONFIG_LIB_RAND    - to enable implementation of rand library in lib/rand.c
- CONFIG_LIB_HW_RAND - to enable hardware based implementations of lib rand

Other changes:
- add CONFIG_LIB_RAND to boards configs which needs rand()
- put only one rand.o dependency in lib/Makefile

CONFIG_LIB_HW_RAND should be defined for drivers which implements rand library
(declared in include/common.h):
- void srand(unsigned int seed)
- unsigned int rand(void)
- unsigned int rand_r(unsigned int *seedp)

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
10 years agocommon, env: Fix support for environment in i2c eeprom
Matthias Fuchs [Wed, 19 Mar 2014 09:25:08 +0000 (10:25 +0100)]
common, env: Fix support for environment in i2c eeprom

When using CONFIG_SYS_I2C i2c needs to be initialized by
i2c_init_all(). This is done in some places but not in
eeprom_init().

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
10 years agoaxs101: flush DMA buffer descriptors before DMA transactons starts
Alexey Brodkin [Fri, 21 Mar 2014 12:57:47 +0000 (16:57 +0400)]
axs101: flush DMA buffer descriptors before DMA transactons starts

CPU sets DMA buffer descriptors with data required for inetrnal DMA such as:
 * Ownership of BD
 * Buffer size
 * Pointer to data buffer in memory

Then we need to make sure DMA engine of NAND controller gets proper data.
For this we flush buffer rescriptor.

Then we're  ready for DMA transaction.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
10 years agonet/designware: align DMA buffer descriptors to D$ line
Alexey Brodkin [Fri, 21 Mar 2014 12:16:57 +0000 (16:16 +0400)]
net/designware: align DMA buffer descriptors to D$ line

It's important to have ability to flush/invalidate each DMA buffer descriptor
individually to prevent incoherency of adjacent BDs.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
10 years agoLogo: TIZEN: Change booting logo size to official size.
Jonghwa Lee [Fri, 21 Mar 2014 09:18:02 +0000 (18:18 +0900)]
Logo: TIZEN: Change booting logo size to official size.

Since TIZEN group has been used 450 X 140 bmp logo for lunchbox,
this patch tries to change the logo size from 500 X 150 to official size.
By reducing image size, we also save about 35KB.

To make row aligned 4 bytes, add 2 pixels to row. Therefore the real width
of image size is 452.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Reviewed-by : Przemyslaw Marczak <p.marczak@samsung.com>

10 years agospl: Fix guardian macros in spl.h
Marek Vasut [Wed, 19 Mar 2014 01:02:55 +0000 (02:02 +0100)]
spl: Fix guardian macros in spl.h

Fix the macros guarding the spl.h header for various platforms. Due to
a typo and a propagation of it, the macros went out-of-sync with their
ifdef check, so fix this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
10 years agokbuild: move asm-offsets.c from SoC directory to arch/$(ARCH)/lib
Masahiro Yamada [Tue, 18 Mar 2014 07:38:13 +0000 (16:38 +0900)]
kbuild: move asm-offsets.c from SoC directory to arch/$(ARCH)/lib

U-Boot has supported two kinds of asm-offsets.h.

One is generic for all architectures and its source is located at
./lib/asm-offsets.c.

The other is SoC specific and its source is under SoC directory.
The problem here is that only boards with SoC directory can use
the asm-offsets infrastructure.
Putting asm-offsets.c right under CPU directory does not work.

Now a new demand is coming. PowerPC folks want to use asm-offsets.
But no PowerPC boards have SoC directory.

It seems inconsistent that some boards add asm-offsets.c to SoC
directoreis and some to CPU directories.
It looks more reasonable to put asm-offsets.c under arch/$(ARCH)/lib.

This commit merges asm-offsets.c under SoC directories into
arch/$(ARCH)/lib/asm-offsets.c.

By the way, I doubt the necessity of some entries in asm-offsets.c.
I am leaving refactoring to the board maintainers.
Please check "TODO" in the comment blocks in
arch/{arm,nds32}/lib/asm-offsets.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Yuantian Tang <Yuantian.Tang@freescale.com>
10 years agokbuild: Rename UIMAGE to MKIMAGE
Marek Vasut [Fri, 14 Mar 2014 04:00:14 +0000 (05:00 +0100)]
kbuild: Rename UIMAGE to MKIMAGE

U-Boot uses the 'mkimage' tool to produce various image types,
not only uImage image type. Rename the invocation name from
UIMAGE to MKIMAGE.

The following command was used to do the replacement:
git grep 'quiet_cmd_mkimage.* = UIMAGE' | cut -d : -f 1 | \
 xargs -i sed -i "s@\(quiet_cmd_mkimage\)\(.*\) = UIMAGE @\1\2 = MKIMAGE@" {}

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>