Alexander Holler [Tue, 18 Jan 2011 23:24:40 +0000 (00:24 +0100)]
Print compiler and linker version with the version command
After years of unsuccessful research I've finally shamelessly stolen other
peoples intellectual properties to present the all-new and world-changing
updated version command:
-
U-Boot>> version
U-Boot 2010.12-00014-g7435056-dirty (Jan 18 2011 - 23:19:38)
MyBoard
gcc (GCC) 0.42 (Distro foobar)
GNU ld (GNU Binutils) 0.314159265
-
May the toolchain bugs rest in peace.
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Po-Yu Chuang [Sun, 19 Dec 2010 23:07:23 +0000 (23:07 +0000)]
arm: a320evb: fixes for relocation support
* add CONFIG_SYS_SDRAM_BASE and CONFIG_SYS_INIT_SP_ADDR
* do not update gd->bd in dram_init() because bd is unavailable then
* move CONFIG_SYS_TEXT_BASE from config.mk to a320evb.h
* remove config.mk
ARM: Avoid compiler optimization for readb, writeb and friends.
gcc 4.5.1 seems to ignore (at least some) volatile definitions,
avoid that as done in the kernel.
Reading C99 6.7.3 8 and the comment 114) there, I think it is a bug of that
gcc version to ignore the volatile type qualifier used e.g. in __arch_getl().
Anyway, using a definition as in the kernel headers avoids such optimizations when
gcc 4.5.1 is used.
Maybe the headers as used in the current linux-kernel should be used,
but to avoid large changes, I've just added a small change to the current headers.
Signed-off-by: Alexander Holler <holler@ahsoftware.de> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Alessandro Rubini <rubini-list@gnudd.com> Tested-by: Thomas Weber <weber@corscience.de> Acked-by: Alexander Holler <holler@ahsoftware.de> Tested-by: Alexander Holler <holler@ahsoftware.de>
Sandeep Paulraj [Tue, 28 Dec 2010 22:38:22 +0000 (17:38 -0500)]
DaVinci DM6467: Enhance board Support
Support for DM6467 was incomplete and the build failed
as well. Patches were sent to the list but have not been
added. This enhances the DM6467 support.
Some more patches will need to be sent to bring
it in line with what is available in internal TI
trees
Sandeep Paulraj [Tue, 28 Dec 2010 20:43:16 +0000 (15:43 -0500)]
DaVinci DM6467: Added ET1011C (LSI) PHY support
Added arch/arm/cpu/arm926ejs/davinci/et1011c.c for handling
ET1011C gigabit phy. which overrides get_link_speed function
from default implementation. This enables output of 125 MHz
reference clock on SYS_CLK pin.
Sandeep Paulraj [Tue, 28 Dec 2010 19:42:27 +0000 (14:42 -0500)]
DaVinci EMAC: Add name to Ethernet device
Adds "DaVinci-EMAC" as the name of the device so that
it gets printed as "Using DaVinci-EMAC device"
during network access (dhcp, tftp) instead of empty name
in "Using" statement.This name also gets
reflected in 'ethact' env variable.
Sandeep Paulraj [Tue, 28 Dec 2010 19:37:33 +0000 (14:37 -0500)]
DaVinci EMAC: Fix davinci_eth_gigabit_enable
Enabling the gigabit was overwriting the
previous configuration by setting up only GIGAFORCE and
GIG bits of MAC control register.
Modified to retain previous configuration while
gigabit enabling.
Sandeep Paulraj [Tue, 21 Dec 2010 01:01:21 +0000 (20:01 -0500)]
Davinci MMCSD Support
Added support for MMC/SD cards for Davinci. This feature is enabled by
CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC
options. This is tested on DM355 and DM365 EVMs with both the available mmc
controllers.
The patch adds the -pie option to link u-boot.bin only.
Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <liu.h.jason@gmail.com> CC: lool@dooz.org CC: Wolfgang Denk <wd@denx.de> CC: Albert Aribaud <albert.aribaud@free.fr> Tested-by: Alexander Holler <holler@ahsoftware.de>
Stefano Babic [Thu, 20 Jan 2011 08:05:15 +0000 (08:05 +0000)]
Add support for Freescale's mx35pdk board.
The patch adds suupport for the Freescale's mx35pdk board
(known as well as mx35_3stack).
The board boots from the NOR flash. Following devices
are supported:
- two ethernet devices (FEC and SMC911x on debug board)
- I2C
- PMIC (MC13892) via I2C interface
- UART
- NOR flash (64MB)
- NAND flash (2GB)
- basic access to mc9sdz60 registers via I2C interface
SPI: mxc_spi: add SPI clock calculation and setup to the driver
The MXC SPI driver didn't calculate the SPI clock up to
now and just used highest possible divider 512 for DATA
RATE in the control register. This results in very low
transfer rates.
The patch adds code to calculate and setup the SPI clock
frequency for transfers.
SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case
We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift operations are
performed in each loop cycle causing zero gaps in the transmited
data, so not all data scheduled for transmition is actually
transmited.
The proper swapping in unaligned rx case is missing, so add it
as we need to put the received data into the rx buffer in the
correct byte order.
Stefano Babic [Thu, 20 Jan 2011 07:51:31 +0000 (07:51 +0000)]
I2C: mxc_i2c: address failure with mx35 processor
There is sporadic failures when more as one I2C slave
is on the bus and the processor tries to communicate
with more as one slave.
The problem was seen on a mx35pdk (two I2C slaves,
PMIC controller and CAN/RTC chip).
The current driver uses the IIF bit in the status register
to check if the bus is busy or not. According to the manual,
this is not correct, because the IIB bit should be checked.
Not only, to check if a transfer is finished must be checked
the ICF bit, and this is not tested at all.
This patch comes from analyse with a corresponding driver
provided by Freescale as part of the LTIB tool. Comparing
the two drivers, it appears that the current u-boot driver checks
the wrong bits, and depending on race condition, the transfer
can be successful or not.
The patch gets rid also of own debug function (DPRINTF),
replaced with the general debug().
Stefano Babic [Thu, 20 Jan 2011 07:50:44 +0000 (07:50 +0000)]
I2C: mxc_i2c: get rid of __REG access
This driver accesses to processor's register
via __REG macros, that are removed (or are planned
to be removed) and replaced by C structures.
This patches replaces all occurrencies of __REG macros.
Liu Hui-R64343 [Mon, 3 Jan 2011 22:27:35 +0000 (22:27 +0000)]
MX5: Add initial support for MX53 processor
Add initial support for Freescale MX53 processor,
- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro
Liu Hui-R64343 [Thu, 23 Dec 2010 01:13:17 +0000 (01:13 +0000)]
MX51EVK: UART does not print out the early information
The early bootup information is not print out due to
the UART pin iomux not set up correctly before board_init
Add the board_early_init_f function and enable the
CONFIG_BOARD_EARLY_INIT_F. Move the UART pin setting
from board_init to board_early_init_f function.
This patch also move the FEC pin iomux setup to the
board_early_init_f.
Alex Dubov [Mon, 24 Jan 2011 05:59:10 +0000 (21:59 -0800)]
mpq101: initial support for Mercury Computer Systems MPQ101 board
Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash
memory, real time clock and additional serial EEPROM on i2c bus (enabled).
USB controller is available, but not presently enabled.
Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx
Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling). This is achieved by means of
custom ld script.
Signed-off-by: Alex Dubov <oakad@yahoo.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Wed, 26 Jan 2011 18:30:00 +0000 (10:30 -0800)]
p1022ds: fix pixis_reset altbank
Fix the bits for ngpixis to reset to alternative bank. Originally the mask
was 0xE0, which left it possible to reset to bank 3 if DIP switch is set to
boot from bank 1. Changing to 0xF0 gurantees to reset to bank 2.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Liu Ying [Tue, 11 Jan 2011 07:29:58 +0000 (15:29 +0800)]
lcd: align fb writing address for horizontal display offset
CONFIG_SPLASH_SCREEN_ALIGN makes uboot support display
offset for splashimage. The framebuffer writing address
should be calculated according to different kinds of
framebuffer pixel format, i.e., bits per pixel value.
Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS
Linker needs to use the proper endian/bfd flags even when doing partial linking.
LDFLAGS_u-boot sets linker option which is called it when U-boot is built
(u-boot final).
LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target).
CC: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
FPU POST: fix warnings when building with 2.18 binutils
However, this only took into effect if CONFIG_SYS_POST_FPU was enabled.
We can simply move the GNU_FPOST_ATTR out of the CONFIG_SYS_POST_FPU
ifdef block to address the issue.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 19 Jan 2011 09:36:40 +0000 (03:36 -0600)]
UEC: Fix compiler warnings introduced by linux/mii.h change
Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced the following
compiler warnings in the uec ethernet driver:
In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0,
from uec.c:32:
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined
uec_phy.h:34:0: note: this is the location of the previous definition
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined
uec_phy.h:35:0: note: this is the location of the previous definition
In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0,
from uec_phy.c:27:
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined
uec_phy.h:34:0: note: this is the location of the previous definition
/local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined
uec_phy.h:35:0: note: this is the location of the previous definition
Fix them be removing the duplication in the uec code and utlizing the
linux/mii.h version instead.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Loïc Minier [Wed, 19 Jan 2011 12:16:30 +0000 (13:16 +0100)]
Cleanup .boards.depend when using an objtree
.boards.depend was created in the source tree even when calling make
with O=objtree, and distclean O=objtree wouldn't clean it. Create
.boards.depend in objtree instead as to clean it up properly.
Reported-by: Loïc Minier <loic.minier@linaro.org> Signed-off-by: Wolfgang Denk <wd@denx.de>
Loïc Minier [Wed, 19 Jan 2011 12:16:29 +0000 (13:16 +0100)]
Don't add symlink in srctree when using an objtree
When building with srctree != objtree, the build creates arch/soc/cpu
specific symlinks in the source tree. This means that the same source
tree can't be used for multiple builds at the same time. Also, these
symlinks in the source tree are only cleaned up if one passes the same
O= to distclean.
When srctree != objtree, mkconfig creates an $objtree/include2 directory
in the objtree to host the asm -> arch/$arch/include/asm symlink so that
"#include <asm>" can be used. But it also creates another identical
symlink in $objtree/include.
Then, mkconfig creates two symlinks:
$objtree/include/asm/arch -> arch/$arch/include/asm/arch-$cpu (or $soc)
$objtree/include/asm/proc -> arch/$arch/include/asm/proc-armv (on arm)
but because $objtree/include/asm points at $srctree already, the two
symlinks are created under $srctree.
To fix this, create a real $objtree/include/asm directory, instead of a
symlink. Update cleanup code accordingly.
Dipen Dudhat [Wed, 19 Jan 2011 07:16:27 +0000 (12:46 +0530)]
powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC
Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Mon, 10 Jan 2011 12:03:01 +0000 (12:03 +0000)]
mpc85xx: Implement workaround for erratum DDR-A003
Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM.
Also adding polling after enabling DDR controller to ensure completion.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Mon, 10 Jan 2011 12:03:00 +0000 (12:03 +0000)]
mpc85xx: Enable unique mode registers and dynamic ODT for DDR3
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.
Enable address parity and RCW by default for RDIMMs.
Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.
Use a formula to calculate rodt_on for timing_cfg_5.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Mon, 10 Jan 2011 12:02:59 +0000 (12:02 +0000)]
mpc85xx: Adding more registers and options
This patch exposes more registers which can be used by the DDR drivers or
interactive debugging. U-boot doesn't use all the registers in DDRC.
When advanced tuning is required, writing to those registers is needed.
Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers
Add options to override rcw, address parity to RDIMMs.
Use array for debug registers.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Mon, 10 Jan 2011 12:02:57 +0000 (12:02 +0000)]
mpc8xxx: Enable ECC on/off control in hwconfig
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
default.
Updated hwconfig calls to use local buffer.
Syntax is
hwconfig=fsl_ddr:ecc=on
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.
Eventually this should be handled by Kconfig & defconfigs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
Kumar Gala [Sun, 9 Jan 2011 17:37:00 +0000 (11:37 -0600)]
powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR init
There are several users of the hwconfig APIs (8xxx DDR) before we have
the environment properly setup. This causes issues because of the
numerous ways the environment might be accessed because of the
non-volatile memory it might be stored in. Additionally the access
might be so early that memory isn't even properly setup for us.
Towards resolving these issues we provide versions of all the hwconfig
APIs that can be passed in a buffer to parse and leave it to the caller
to determine how to allocate and populate the buffer.
We use the _f naming convention for these new APIs even though they are
perfectly useable after relocation and the environment being ready.
We also now warn if the non-f APIs are called before the environment is
ready to allow users to address the issues.
Finally, we convert the 8xxx DDR code to utilize the new APIs to
hopefully address the issue once and for all. We have the 8xxx DDR code
create a buffer on the stack and populate it via getenv_f().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
Kumar Gala [Tue, 1 Jun 2010 15:29:11 +0000 (10:29 -0500)]
powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* SERDES Table
* Added p2040 to cpu_type_list and SVR list
* Added number of LAWs for p2040
* Set CONFIG_MAX_CPUS to 4 for p2040
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Poonam Aggrwal [Thu, 13 Jan 2011 16:10:05 +0000 (21:40 +0530)]
powerpc/85xx: Add Support for Freescale P1014 Processor
The P1014 is similar to the P1010 processor with the following differences:
- 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC)
- no eCAN interface. (P1010 has 2 eCAN interfaces)
- Two SGMII interface (P1010 has 3 SGMII)
- No secure boot
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Poonam Aggrwal [Thu, 13 Jan 2011 16:09:27 +0000 (21:39 +0530)]
powerpc/85xx: Add Support for Freescale P1010 Processor
Key Features include of the P1010:
* e500v2 core frequency operation of 500 to 800 MHz
* Power consumption less than 5.0 W at 800 MHz core speed
* Dual SATA 3 Gbps controllers with integrated PHY
* Dual PCI Express controllers
* Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs)
* TCP/IP acceleration and classification capabilities
* IEEE 1588 support
* Lossless flow control
* RGMII, SGMII
* DDR3 with support for a 32-bit data interface (40 bits including ECC),
up to 800 MHz data rate 32/16-bit DDR3 memory controller
* Dedicated security engine featuring trusted boot
* TDM interface
* Dual controller area networks (FlexCAN) controller
* SD/MMC card controller supporting booting from Flash cards
* USB 2.0 host and device controller with an on-chip, high-speed PHY
* Integrated Flash controller (IFC)
* Power Management Controller (PMC)
* Four-channel, general-purpose DMA controller
* I2C controller
* Serial peripheral interface (SPI) controller with master and slave support
* System timers including a periodic interrupt timer, real-time clock,
software watchdog timer, and four general-purpose timers
* Dual DUARTs
Prabhakar [Tue, 18 Jan 2011 03:33:59 +0000 (09:03 +0530)]
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR
CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET.
It should be as
CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET.
Haiying Wang [Wed, 1 Dec 2010 15:35:31 +0000 (10:35 -0500)]
8xxx/ddr: add support to only compute the ddr sdram size
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Lei Wen [Wed, 1 Dec 2010 15:43:43 +0000 (23:43 +0800)]
usb_ether: register usb ethernet gadget at each eth init
Since the ether may not be the only one usb gadget would be used
in the uboot, it is neccessary to do the register each time the
eth begin to work to make usb gadget driver less confussed when
we want to use two different usb gadget at the same time.
Usb gadget driver could simple ignore the register operation, if
it find the driver has been registered already.
Loïc Minier [Tue, 4 Jan 2011 01:32:36 +0000 (02:32 +0100)]
Escape minus signs in manpage
By default, "-" chars are interpreted as hyphens (U+2010) by groff, not
as minus signs (U+002D). Since options to programs use minus signs
(U+002D), this means for example in UTF-8 locales that you cannot cut
and paste options, nor search for them easily.
When a flash partition was positioned at the very top of a 32-bit memory
map (eg located at 0xf8000000 with a size of 0x8000000)
get_part_sector_size_nor() would incorrectly calculate the partition's
ending address to 0x0 due to overflow. When the overflow occurred
get_part_sector_size_nor() would falsely return a sector size of 0.
A sector size of 0 results in subsequent jffs2 operations failing.
To workaround the overflow subtract 1 from calculated address of
the partition endpoint.
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