The Xilinx ML507 Board is a Virtex 5 prototyping board that includes,
among others:
-Virtex 5 FX FPGA (With a ppc440x5 in it)
-256MB of SDRAM2
-32MB of Flash
-I2C Eeprom
-System ACE chip
-Serial ATA connectors
-RS232 Level Conversors
-Ethernet Transceiver
This patch gives support to a standard design produced by EDK for this
board: ppc440, uartlite, xilinx_int and flash
- Includes Changes propossed by Stefan Roese and Michal Simek
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
-This patchs gives support for the embbedded ppc440
on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by Stefan Roese
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
Robin Getz [Tue, 15 Jul 2008 19:44:46 +0000 (21:44 +0200)]
Fix DHCP protocol so U-Boot does not respond too early
on the network with it's offered IP number; it should not reply until
after it has received a DHCP ACK message. Also ensures that U-Boot
does it's DHCPREQUEST as broadcast (per RFC 2131).
Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> Acked-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
Timur Tabi [Thu, 19 Jun 2008 22:56:11 +0000 (17:56 -0500)]
Update Freescale sys_eeprom.c to handle CCID formats
Update the sys_eeprom.c file to handle both NXID and CCID EEPROM formats. The
NXID format replaces the older CCID format, but it's important to support both
since most boards out there still use the CCID format. This change is in
preparation for using one file to handle both formats. This will also unify
EEPROM support for all Freescale 85xx and 86xx boards.
Also update the 86xx board header files to use the standard CFG_I2C_EEPROM_ADDR
instead of ID_EEPROM_ADDR.
Andy Fleming [Tue, 15 Jul 2008 01:29:07 +0000 (20:29 -0500)]
Clean up INIT_RAM options
The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out. In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Tue, 15 Jul 2008 01:26:57 +0000 (20:26 -0500)]
Remove fake flash bank from 8544 DS
The fake flash bank was generating errors for anyone who didn't have a
PromJET hooked up to the board. As that constitutes the vast majority of
users, we remove it.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Kumar Gala [Mon, 14 Jul 2008 19:07:00 +0000 (14:07 -0500)]
85xx: Cleanup L2 cache size detection
The L2 size detection code was a bit confusing and we kept having to add
code to it to handle new processors. Change the sense of detection so we
look for the older processors that aren't changing.
Also added support for 1M cache size on 8572.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Fri, 11 Jul 2008 19:33:07 +0000 (15:33 -0400)]
sbc8560: add default fdt values
Add in the default fdt settings and the typical EXTRA_ENV
settings as borrowed from the mpc8560ads. Fix a couple
of stale references to the mpc8560ads dating back to the
original clone/fork.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Paul Gortmaker [Fri, 11 Jul 2008 19:33:05 +0000 (15:33 -0400)]
sbc8560: define eth0 and eth1 instead of eth1 and eth2
The existing config doesn't define CONFIG_HAS_ETH0, and so the
fdt support doesn't update the zeros in the dtb local-mac with
real data from the u-boot env. Since the existing config is
tailored to just two interfaces, get rid of the ETH2 definitions
at the same time.
Also don't include any end user specific data into the environment
by default -- things like MAC address, network parameters etc. need
to come from the end user.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Paul Gortmaker [Fri, 11 Jul 2008 19:33:03 +0000 (15:33 -0400)]
sbc8560: proper definitions for TSEC.
The definitions for the TSEC have become out of date. There is no
longer any such options like "CONFIG_MPC85xx_TSEC1" or similar.
Update to match those of other boards, like the MPC8560ADS.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
Paul Gortmaker [Wed, 9 Jul 2008 17:23:05 +0000 (13:23 -0400)]
8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreq
Some boards that have external 16550 UARTs don't have a direct
tie between bi_busfreq and the clock used for the UARTs. Boards
that do have such a tie should set CFG_NS16550_CLK to be
get_bus_freq(0) -- which most of them do already.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
Andrew Klossner [Wed, 2 Jul 2008 14:03:53 +0000 (07:03 -0700)]
Change the temp map to ROM to align addresses to page size.
With a page size of BOOKE_PAGESZ_16M, both the real and effective
addresses must be multiples of 16MB. The hardware silently truncates
them so the code happens to work. This patch clarifies the situation
by establishing addresses that the hardware doesn't need to truncate.
Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Kim Phillips [Mon, 16 Jun 2008 20:55:53 +0000 (15:55 -0500)]
fdt: add crypto node handling for MPC8{3, 5}xxE processors
Delete the crypto node if not on an E-processor. If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Andy Fleming [Mon, 7 Jul 2008 23:02:08 +0000 (18:02 -0500)]
Remove LBC_CACHE_BASE from 8544 DS
The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.
Signed-off-by: Andy Fleming <afleming@freescale.com>
We need to wait while drawing engine clears frame
buffer before any further software accesses to frame
buffer will be initiated. Otherwise software drawn
parts could be partially destroyed by the drawing
engine or even GDC chip freeze could occur (as
observed on socrates board).
Michal Simek [Fri, 11 Jul 2008 08:43:13 +0000 (10:43 +0200)]
FIS: repare incorrect return value with ramdisk handling
Microblaze and PowerPC use boot_get_ramdisk for loading
ramdisk to memory with checking return value.
Return 0 means success. Return 1 means failed.
Here is correspond part of code from bootm.c which check
return code.
ret = boot_get_ramdisk (argc, argv, images, IH_ARCH_PPC,
&rd_data_start, &rd_data_end);
if (ret)
goto error;
Stefan Roese [Thu, 10 Jul 2008 11:53:31 +0000 (13:53 +0200)]
ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boards
This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.
Mail to kharris@nexus-tech.net bounces because the user doesn't exist
anymore. You can't be a maintainer without a valid e-mail address, so
move all boards that used to be maintained by Kyle Harris to the
"orphaned" list.
Currently, only PowerPC has a list of orphaned boards, so this patch
creates one for ARM as well.
at91: Fix to enable using Teridian MII phy (78Q21x3) with at91sam9260
On the at91sam9260ep development board there is an EEPROM
connected to the TWI interface (PA23, PA24 Peripheral A
multiplexing), so we cannot use these pins as ETX2, ETX3.
This patch configures PA10, PA11 pins for ETX2, ETX3
instead of PA23, PA24 pins.
Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Manuel Sahm <Manuel.Sahm@feig.de>
The DIU_DIV register is 8 bit not 5 bit. This prevented large DIV values
so it was not possible to set a slow pixel clock and thus prevented
display on small screens.
Signed-off-by: Kenneth Johansson <kenneth@southpole.se> Acked-by: John Rigby <jrigby@freescale.com>
John Rigby [Fri, 11 Jul 2008 20:44:09 +0000 (14:44 -0600)]
ADS5121 cleanup compile warnings
board/ads5121/iopin.c
Replace bit fields in struct iopin_t with a single
field and intialize it via plain old macros.
This fixes the type pun warnings and makes the code
more readable.
board/ads5121/ads5121.c
Add include iopin.h to ads5121.c for the iopin_initialize
prototype.
TsiChung Liew [Thu, 29 May 2008 17:21:54 +0000 (12:21 -0500)]
ColdFire: Fix UART baudrate formula
The formula "counter = (u32) (gd->bus_clk / gd->baudrate) / 32"
can generate the wrong divisor due to integer division truncation.
Round the calculated divisor value by adding 1/2 the baudrate
before dividing by the baudrate.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Stefan Roese [Thu, 10 Jul 2008 09:38:26 +0000 (11:38 +0200)]
ppc4xx: Fix include sequence in 4xx_pcie.c
This patch now moves common.h to the top of the inlcude list. This
is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that
the phys_size_t/phys_addr_t are defined to the correct size in this
driver.
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