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u-boot
11 years agoARM: OMAP: I2C: New read, write and probe functions
Lubomir Popov [Sat, 1 Jun 2013 06:44:38 +0000 (06:44 +0000)]
ARM: OMAP: I2C: New read, write and probe functions

New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
(4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
OMAPs and derivatives as well. The only anticipated exception would
be the OMAP2420, which shall require driver modification.
- Rewritten i2c_read to operate correctly with all types of chips
  (old function could not read consistent data from some I2C slaves).
- Optimised i2c_write.
- New i2c_probe, performs write access vs read. The old probe could
  hang the system under certain conditions (e.g. unconfigured pads).
- The read/write/probe functions try to identify unconfigured bus.
- Status functions now read irqstatus_raw as per TRM guidelines
  (except for OMAP243X and OMAP34XX).
- Driver now supports up to I2C5 (OMAP5).

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Heiko Schocher <hs@denx.de>
11 years agoarm: Remove OMAP2420H4 and all omap24xx support
Tom Rini [Tue, 4 Jun 2013 12:02:06 +0000 (12:02 +0000)]
arm: Remove OMAP2420H4 and all omap24xx support

The omap2420H4 was the only mainline omap24xx board.  Prior to being
fixed by Jon Hunter in time for v2013.04 it had been functionally broken
for a very long time.  Remove this board as there's not been interest in
it in U-Boot for quite a long time.

Signed-off-by: Tom Rini <trini@ti.com>
11 years agoda830: add MMC support
Vishwanathrao Badarkhe, Manish [Wed, 22 May 2013 03:38:48 +0000 (03:38 +0000)]
da830: add MMC support

Add MMC support for da830 boards in order to perform
mmc operations(read,write and erase).

Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
11 years agoARM: OMAP5: Power: Add more functionality to Palmas driver
Lubomir Popov [Thu, 6 Jun 2013 04:16:40 +0000 (04:16 +0000)]
ARM: OMAP5: Power: Add more functionality to Palmas driver

Add some useful functions, and the corresponding definitions.

Add support for powering on the dra7xx_evm SD/MMC LDO
(courtesy Lokesh Vutla <lokeshvutla@ti.com>).

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoARM: DRA7xx: EMIF: Change settings required for EVM board
Sricharan R [Thu, 30 May 2013 03:19:39 +0000 (03:19 +0000)]
ARM: DRA7xx: EMIF: Change settings required for EVM board

DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: clocks: Update PLL values
Lokesh Vutla [Thu, 30 May 2013 03:19:38 +0000 (03:19 +0000)]
ARM: DRA7xx: clocks: Update PLL values

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
11 years agoARM: DRA7xx: Update pinmux data
Lokesh Vutla [Thu, 30 May 2013 03:19:37 +0000 (03:19 +0000)]
ARM: DRA7xx: Update pinmux data

Updating pinmux data as specified in the latest DM

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
11 years agommc: omap_hsmmc: Update pbias programming
Balaji T K [Thu, 6 Jun 2013 05:04:32 +0000 (05:04 +0000)]
mmc: omap_hsmmc: Update pbias programming

Update pbias programming sequence for OMAP5 ES2.0/DRA7

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: Correct SRAM END address
Sricharan R [Thu, 30 May 2013 03:19:35 +0000 (03:19 +0000)]
ARM: DRA7xx: Correct SRAM END address

NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: Correct the SYS_CLK to 20MHZ
Sricharan R [Thu, 30 May 2013 03:19:34 +0000 (03:19 +0000)]
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ

The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: Change the Debug UART to UART1
Sricharan R [Thu, 30 May 2013 03:19:33 +0000 (03:19 +0000)]
ARM: DRA7xx: Change the Debug UART to UART1

Serial UART is connected to UART1. So add the change
for the same.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
11 years agoARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Lokesh Vutla [Thu, 30 May 2013 03:19:32 +0000 (03:19 +0000)]
ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's

Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP5: DRA7xx: support class 0 optimized voltages
Nishanth Menon [Thu, 30 May 2013 03:19:31 +0000 (03:19 +0000)]
ARM: OMAP5: DRA7xx: support class 0 optimized voltages

DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: clocks: Fixing i2c_init for PMIC
Lokesh Vutla [Thu, 30 May 2013 03:19:30 +0000 (03:19 +0000)]
ARM: DRA7xx: clocks: Fixing i2c_init for PMIC

In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: power Add support for tps659038 PMIC
Lokesh Vutla [Thu, 30 May 2013 03:19:29 +0000 (03:19 +0000)]
ARM: DRA7xx: power Add support for tps659038 PMIC

TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: Add control id code for DRA7xx
Lokesh Vutla [Thu, 30 May 2013 03:19:28 +0000 (03:19 +0000)]
ARM: DRA7xx: Add control id code for DRA7xx

The registers that are used for device identification
are changed from OMAP5 to DRA7xx.
Using the correct registers for DRA7xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP4+: pmic: Make generic bus init and write functions
Lokesh Vutla [Thu, 30 May 2013 02:54:33 +0000 (02:54 +0000)]
ARM: OMAP4+: pmic: Make generic bus init and write functions

Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h
Lokesh Vutla [Thu, 30 May 2013 02:54:32 +0000 (02:54 +0000)]
ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h

To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP5: clocks: Do not enable sgx clocks
Sricharan R [Thu, 30 May 2013 02:54:31 +0000 (02:54 +0000)]
ARM: OMAP5: clocks: Do not enable sgx clocks

SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP4+: Cleanup header files
Lokesh Vutla [Thu, 30 May 2013 02:54:30 +0000 (02:54 +0000)]
ARM: OMAP4+: Cleanup header files

After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoOMAP5: Fix bug in omap5_es1_prcm struct
Lubomir Popov [Sun, 26 May 2013 10:03:17 +0000 (10:03 +0000)]
OMAP5: Fix bug in omap5_es1_prcm struct

The newly introduced function setup_warmreset_time(), called
from within prcm_init(), tries to write to the prm_rsttime
OMAP5 register. The struct member holding this register's
address is however initialized for OMAP5 ES2.0 only. On ES1.0
devices this uninitialized value causes a second (warm) reset
at startup.

Add .prm_rsttime address init to the ES1.0 struct.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Tom Rini <trini@ti.com>
11 years agoOMAP5: add ABB setup for MPU voltage domain
Andrii Tseglytskyi [Mon, 20 May 2013 22:42:09 +0000 (22:42 +0000)]
OMAP5: add ABB setup for MPU voltage domain

Patch adds a call of abb_setup() function, and proper registers
definitions needed for ABB setup sequence. ABB is initialized
for MPU voltage domain.

Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
11 years agoOMAP3+: introduce generic ABB support
Andrii Tseglytskyi [Mon, 20 May 2013 22:42:08 +0000 (22:42 +0000)]
OMAP3+: introduce generic ABB support

Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains
starting with OMAP3630. There are three modes of operation:

* Bypass - the default, it just follows the vdd voltage
* Foward Body-Bias - applies voltage bias to increase transistor
  performance at the cost of power.  Used to operate safely at high
  OPPs.
* Reverse Body-Bias - applies voltage bias to decrease leakage and
  save power.  Used to save power at lower OPPs.

Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
11 years agoam33xx: Board: Make CPSW section of ethernet initialization depend on CPSW driver
Joel A Fernandes [Tue, 7 May 2013 05:52:55 +0000 (05:52 +0000)]
am33xx: Board: Make CPSW section of ethernet initialization depend on CPSW driver

Not doing so breaks cases where CPSW is not required such as for USB RNDIS network boot.

Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
11 years agoMerge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Albert ARIBAUD [Sat, 8 Jun 2013 12:35:10 +0000 (14:35 +0200)]
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

Conflicts:
drivers/serial/Makefile

11 years agoARM: tegra: only enable SCU on Tegra20
Tom Warren [Thu, 23 May 2013 12:26:18 +0000 (12:26 +0000)]
ARM: tegra: only enable SCU on Tegra20

The non-SPL build of U-Boot on Tegra only runs on a single CPU, and
hence there is no need to enable the SCU when running U-Boot. If an
SMP OS is booted, and it needs the SCU enabled, it will enable the SCU
itself. U-Boot doing so is redundant.

The one exception is Tegra20, where an enabled SCU is required for some
aspects of PCIe to work correctly.

Some Tegra SoCs contain CPUs without a software-controlled SCU. In this
case, attempting to turn it on actively causes problems. This is the case
for Tegra114. For example, when running Linux, the first (or at least
some very early) user-space process will trigger the following kernel
message:

Unhandled fault: imprecise external abort (0x406) at 0x00000000

This is typically accompanied by that process receving a fatal signal,
and exiting. Since this process is usually pid 1, this causes total
system boot failure.

Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, fleshed out description, ported to upstream chipid APIs]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agovf610twr: Drop unneeded 'status' variable
Fabio Estevam [Wed, 5 Jun 2013 11:34:48 +0000 (11:34 +0000)]
vf610twr: Drop unneeded 'status' variable

No need to use the 'status' variable, so just remove it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
11 years agoARM: imx: Fix incorrect usage of CONFIG_SYS_MMC_ENV_PART
Fabio Estevam [Tue, 4 Jun 2013 15:05:39 +0000 (15:05 +0000)]
ARM: imx: Fix incorrect usage of CONFIG_SYS_MMC_ENV_PART

When running the "save" command several times on a mx6qsabresd we see:

U-Boot > save
Saving Environment to MMC...
Writing to MMC(1)... done
U-Boot > save
Saving Environment to MMC...
MMC partition switch failed
U-Boot > save
Saving Environment to MMC...
Writing to MMC(1)... done
U-Boot > save
Saving Environment to MMC...
MMC partition switch failed
U-Boot > save
Saving Environment to MMC...
Writing to MMC(1)... done
U-Boot > save
Saving Environment to MMC...
MMC partition switch failed

This issue is caused by the incorrect usage of CONFIG_SYS_MMC_ENV_PART.

CONFIG_SYS_MMC_ENV_PART should be used to specify the mmc partition that stores
the environment variables.

On some imx boards it is been incorrectly used to pass the partition of kernel
and dtb files for the 'mmcpart' script variable.

Remove the CONFIG_SYS_MMC_ENV_PART usage and configure the 'mmcpart' variable
directly.

Reported-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
11 years agoam33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c
Tom Rini [Fri, 31 May 2013 16:31:59 +0000 (12:31 -0400)]
am33xx/omap: Move save_omap_boot_params to omap-common/boot-common.c

We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common.  Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx.  Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.

Reviewed-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
11 years agoam33xx: Correct NON_SECURE_SRAM_START/END
Tom Rini [Fri, 31 May 2013 14:48:03 +0000 (10:48 -0400)]
am33xx: Correct NON_SECURE_SRAM_START/END

Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being
used.  As part of correcting these tests, make use of the fact that
we've always been placing our stack outside of the download image area
(which is fine, once the downloaded image is run, ROM is gone) so
correct the max size test to be the ROM defined top of the download area
to where we link/load at.

Signed-off-by: Tom Rini <trini@ti.com>
---
Changes in v2:
- Fix typo noted by Peter Korsgaard

11 years agoomap-common/hwinit-common.c: Mark omap_rev_string as static
Tom Rini [Fri, 31 May 2013 14:44:23 +0000 (10:44 -0400)]
omap-common/hwinit-common.c: Mark omap_rev_string as static

Only called in this file, mark as static.

Signed-off-by: Tom Rini <trini@ti.com>
11 years agoAdd support for Congatec Conga-QEVAl board
SARTRE Leo [Mon, 3 Jun 2013 23:30:36 +0000 (23:30 +0000)]
Add support for Congatec Conga-QEVAl board

Add minimal support (only boot from mmc device) for the Congatec
Conga-QEVAl Evaluation Carrier Board with conga-Qmx6q (i.MX6 Quad
processor) module.

Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
11 years agowandboard: Add Boot Splash image with Wandboard logo
Otavio Salvador [Mon, 27 May 2013 12:18:44 +0000 (12:18 +0000)]
wandboard: Add Boot Splash image with Wandboard logo

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
11 years agowandboard: Enable HDMI splashscreen
Fabio Estevam [Thu, 23 May 2013 07:50:23 +0000 (07:50 +0000)]
wandboard: Enable HDMI splashscreen

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
11 years agobuild: Use generic boot logo matching
Otavio Salvador [Mon, 27 May 2013 12:18:43 +0000 (12:18 +0000)]
build: Use generic boot logo matching

The boot logo matching is now done in following way:

 - use LOGO_BMP if it is set, or
 - use $(BOARD).bmp if it exists in tools/logos, or
 - use $(VENDOR).bmp if it exists in tools/logos, or
 - use denx.bmp otherwise.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Wolfgang Denk <wd@denx.de>
11 years agomx6: mx6qsabrelite/nitrogen6x: Remove incorrect setting of gpio CS signal
Andrew Gabbasov [Thu, 30 May 2013 04:47:38 +0000 (04:47 +0000)]
mx6: mx6qsabrelite/nitrogen6x: Remove incorrect setting of gpio CS signal

The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.

Also, SPI driver sets the direction and initial value of a gpio,
used as a chip select signal, before any actual activity happens
on the bus.

So, it is safe to just remove the gpio_direction_output call,
that works incorrectly, thus making no effect, anyway.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Tested-by: Robert Winkler <robert.winkler@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
11 years agomx6qsabreauto: Add Port Expander reset
Renato Frias [Mon, 13 May 2013 18:01:13 +0000 (18:01 +0000)]
mx6qsabreauto: Add Port Expander reset

There are 3 IO expanders on the mx6qsabreauto all reset by the
same GPIO, just set it to high to use the IO.

Signed-off-by: Renato Frias <b13784@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
11 years agomx6qsabreauto: Add i2c to mx6qsabreauto board
Renato Frias [Mon, 13 May 2013 18:01:12 +0000 (18:01 +0000)]
mx6qsabreauto: Add i2c to mx6qsabreauto board

Add i2c2 and 3 to mx6qsabreauto board, i2c3 is multiplexed
use gpio to set steering.

Signed-off-by: Renato Frias <b13784@freescale.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
11 years agomx6slevk: Allow booting a device tree kernel
Fabio Estevam [Thu, 23 May 2013 13:57:18 +0000 (13:57 +0000)]
mx6slevk: Allow booting a device tree kernel

When the mx6slevk board support was added in U-boot there was no device tree
support for mx6sl, so only a FSL 3.0.35 was tested at that time.

Now that mx6slevk support is available we can boot a device tree kernel, by
adjusting CONFIG_LOADADDR into a proper location, so that a non-dt and a dt
kernels can be booted.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
11 years agoarm: mxs: Fix vectoring table crafting
Marek Vasut [Thu, 25 Apr 2013 16:37:12 +0000 (16:37 +0000)]
arm: mxs: Fix vectoring table crafting

The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28
starts from RAM, so the vectoring table at 0x0 is not present. Craft
code that will be placed at 0x0 and will redirect interrupt vectoring
to proper location of the U-Boot in RAM.

Signed-off-by: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
11 years agoarm: vf610: Add basic support for Vybrid VF610TWR board
Alison Wang [Mon, 27 May 2013 22:55:47 +0000 (22:55 +0000)]
arm: vf610: Add basic support for Vybrid VF610TWR board

VF610TWR is a board based on Vybrid VF610 SoC.

This patch adds basic support for Vybrid VF610TWR board.

Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
11 years agoarm: vf610: Add Vybrid VF610 to mxc_ocotp document
Alison Wang [Mon, 27 May 2013 22:55:46 +0000 (22:55 +0000)]
arm: vf610: Add Vybrid VF610 to mxc_ocotp document

This patch adds Vybrid VF610 to mxc_ocotp document.

Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
11 years agoarm: vf610: Add uart support for Vybrid VF610
Alison Wang [Mon, 27 May 2013 22:55:45 +0000 (22:55 +0000)]
arm: vf610: Add uart support for Vybrid VF610

This patch adds lpuart support for Vybrid VF610 platform.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
11 years agoarm: vf610: Add watchdog support for Vybrid VF610
Alison Wang [Mon, 27 May 2013 22:55:44 +0000 (22:55 +0000)]
arm: vf610: Add watchdog support for Vybrid VF610

This patch adds watchdog support for Vybrid VF610 platform.

Signed-off-by: Alison Wang <b18965@freescale.com>
11 years agonet: fec_mxc: Add support for Vybrid VF610
Alison Wang [Mon, 27 May 2013 22:55:43 +0000 (22:55 +0000)]
net: fec_mxc: Add support for Vybrid VF610

This patch adds FEC support for Vybrid VF610 platform.

In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.

Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
11 years agoarm: vf610: Add Vybrid VF610 CPU support
Alison Wang [Mon, 27 May 2013 22:55:42 +0000 (22:55 +0000)]
arm: vf610: Add Vybrid VF610 CPU support

This patch adds generic codes to support Freescale's Vybrid VF610 CPU.

It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.

Signed-off-by: Alison Wang <b18965@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
11 years agoarm: vf610: Add IOMUX support for Vybrid VF610
Alison Wang [Mon, 27 May 2013 22:55:41 +0000 (22:55 +0000)]
arm: vf610: Add IOMUX support for Vybrid VF610

This patch adds the IOMUX support for Vybrid VF610 platform.

There is a little difference for IOMUXC module between VF610 and i.MX
platform, the muxmode and pad configuration share one 32bit register on
VF610, but they are two independent registers on I.MX platform. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.

Signed-off-by: Alison Wang <b18965@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
11 years agoarm: factorize relocate_code routine
Albert ARIBAUD [Sun, 19 May 2013 01:48:15 +0000 (01:48 +0000)]
arm: factorize relocate_code routine

Replace all relocate_code routines from ARM start.S files
with a single instance in file arch/arm/lib/relocate.S.
For PXA, this requires moving the dcache unlocking code
from within relocate_code into c_runtime_cpu_setup.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
11 years agoarm: do not compile relocate_code() for SPL builds
Albert ARIBAUD [Sun, 19 May 2013 01:48:14 +0000 (01:48 +0000)]
arm: do not compile relocate_code() for SPL builds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
11 years agotx25: copy SPL directly, not using relocate_code.
Albert ARIBAUD [Sun, 19 May 2013 01:48:13 +0000 (01:48 +0000)]
tx25: copy SPL directly, not using relocate_code.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
11 years agomx31pdk: copy SPL directly, not using relocate_code.
Albert ARIBAUD [Sun, 19 May 2013 01:48:12 +0000 (01:48 +0000)]
mx31pdk: copy SPL directly, not using relocate_code.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Simon Glass <sjg@chromium.org>
11 years agoMerge branch 'u-boot/master' into 'u-boot-arm/master'
Albert ARIBAUD [Thu, 30 May 2013 12:45:06 +0000 (14:45 +0200)]
Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c

11 years agotegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL build
Axel Lin [Tue, 21 May 2013 13:45:18 +0000 (13:45 +0000)]
tegra: Define CONFIG_SKIP_LOWLEVEL_INIT for SPL build

Then we can get rid of the #ifdef CONFIG_TEGRA guard in cpu_init_crit.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_crit
Axel Lin [Tue, 21 May 2013 13:44:10 +0000 (13:44 +0000)]
ARM: arm720t: Add missing CONFIG_SKIP_LOWLEVEL_INIT guard for cpu_init_crit

cpu_init_crit() can be skipped, but the code is still enabled requiring a
platform to supply lowlevel_init().

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: tegra: support SKU 7 of Tegra20
Stephen Warren [Fri, 17 May 2013 14:10:15 +0000 (14:10 +0000)]
ARM: tegra: support SKU 7 of Tegra20

Make U-Boot aware of the Tegra20 SKU 7, and treat it identically
to any other Tegra20.

My Whistler board has a SoC with this SKU.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: tegra: support SKU 1 of Tegra114
Stephen Warren [Fri, 17 May 2013 14:10:14 +0000 (14:10 +0000)]
ARM: tegra: support SKU 1 of Tegra114

Make U-Boot aware of the Tegra114 SKU 1, and treat it identically
to any other Tegra114.

This value is used on (at least some) Dalmore boards with a production
rather than engineering chip. Such boards are in the hands of some
partners who want to use upstream U-Boot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agotegra: always build u-boot-nodtb-tegra.bin
Stephen Warren [Tue, 14 May 2013 08:00:53 +0000 (08:00 +0000)]
tegra: always build u-boot-nodtb-tegra.bin

Even when eventually building u-boot-dtb-tegra.bin, separately building
u-boot-nodtb-tegra.bin can be useful, since building it encapsulates the
SPL padding step. If you want to tweak u-boot.dtb and regenerate
u-boot-dtb-tegra.bin, it is then a simple cat operation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoTegra: clk: always use find_best_divider() for periph clocks
Allen Martin [Fri, 10 May 2013 16:56:55 +0000 (16:56 +0000)]
Tegra: clk: always use find_best_divider() for periph clocks

When adjusting peripheral clocks always use find_best_divider()
instead of clk_get_divider() even when a secondary divider is not
available.  In the case where is requested clock is too slow to be
derived from the parent clock this allows a best effort to get close
to the requested clock.

This comes up for commands like "sf" where the user can pass a clock
speed on the command line or "sspi" where the clock is hardcoded to
1MHz, but the Tegra114 SPI controller can't go that low.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoTegra: Remove unused/non-existent spl linker script reference
Tom Warren [Wed, 17 Apr 2013 15:24:57 +0000 (08:24 -0700)]
Tegra: Remove unused/non-existent spl linker script reference

Tegra builds use the common u-boot-spl.lds now.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhu
Tom Warren [Tue, 16 Apr 2013 22:57:51 +0000 (15:57 -0700)]
Tegra: T30: Beaver: Fix board/board_name env vars, s/b beaver, not cardhu

Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both
board and board_name == beaver. Didn't test as I have no T30
Beaver board here.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
11 years agopowerpc/mpc85xx: Clear L1 D-cache lock
York Sun [Fri, 5 Apr 2013 13:07:13 +0000 (13:07 +0000)]
powerpc/mpc85xx: Clear L1 D-cache lock

dcbi instruction has been used to clear D-cache lock. However, the cache
lock is persistent for e6500 core. Use dcblc to clear the lock explicitly.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoSECURE BOOT - Removed deletion of TLB entries code
Ruchika Gupta [Mon, 25 Mar 2013 07:40:25 +0000 (07:40 +0000)]
SECURE BOOT - Removed deletion of TLB entries code

Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete TLB entries after CPU initialization
is no longer required.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Acked-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Shaveta Leekha [Mon, 25 Mar 2013 07:40:24 +0000 (07:40 +0000)]
powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/p5040: fix mdio mux for 10G port
Shaohui Xie [Mon, 25 Mar 2013 07:40:21 +0000 (07:40 +0000)]
powerpc/p5040: fix mdio mux for 10G port

Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux.
So we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h
Poonam Aggrwal [Mon, 25 Mar 2013 07:40:20 +0000 (07:40 +0000)]
powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.h

B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.

Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agosf: spansion: Add support for S25FL128S
Xie Xiaobo [Mon, 25 Mar 2013 07:40:19 +0000 (07:40 +0000)]
sf: spansion: Add support for S25FL128S

SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/p2041: fix serdes reference clock frequency display for PC board
Shaohui Xie [Mon, 25 Mar 2013 07:40:18 +0000 (07:40 +0000)]
powerpc/p2041: fix serdes reference clock frequency display for PC board

PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/b4860: fix for Serdes connectivity to SFP's
Shaveta Leekha [Mon, 25 Mar 2013 07:40:17 +0000 (07:40 +0000)]
powerpc/b4860: fix for Serdes connectivity to SFP's

Crossbar switches were wrongly programmed to
route the CPRI lanes to SFP as the connectivity table
was not correct.
Modified it correctly for SFPs connections.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: fix PHY reset timeout issue
Shengzhou Liu [Mon, 25 Mar 2013 07:40:15 +0000 (07:40 +0000)]
powerpc/t4240qds: fix PHY reset timeout issue

QSGMII card has different PHY address against previous SGMII card.
We check the type of card in slots and set correct PHY address to
avoid complainning "PHY reset timed out" during u-boot booting up.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4qds: Add SW7[4] in the DIP switch display
York Sun [Mon, 25 Mar 2013 07:40:14 +0000 (07:40 +0000)]
powerpc/t4qds: Add SW7[4] in the DIP switch display

SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoEnable XAUI interface for B4860QDS
Suresh Gupta [Mon, 25 Mar 2013 07:40:13 +0000 (07:40 +0000)]
Enable XAUI interface for B4860QDS

- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Stephen George [Mon, 25 Mar 2013 07:40:12 +0000 (07:40 +0000)]
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M

Debug trace buffers are memory mapped in DCSR space beyond 4M.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/p5040: enable PBL tool support
Shaohui Xie [Mon, 25 Mar 2013 07:40:11 +0000 (07:40 +0000)]
powerpc/p5040: enable PBL tool support

Provided a default RCW for P5040, then it can use PBL to build
ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4qds: use clock measurement for sysclk and ddr clock
Ed Swarthout [Mon, 25 Mar 2013 07:40:10 +0000 (07:40 +0000)]
powerpc/t4qds: use clock measurement for sysclk and ddr clock

Use QIXIS measurement registers to obtain sysclk and ddr clock. This
allows using non-standard clock speeds, set by directly writing to
clock chip or store the values in qixis clock data eeprom.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/qixis: add clock measurement registers
Ed Swarthout [Mon, 25 Mar 2013 07:40:09 +0000 (07:40 +0000)]
powerpc/qixis: add clock measurement registers

QIXIS includes frequency measurement functions for each major processor
clock input. After reset (and after clocks are stable), QIXIS measures
the clocks against a reference frequency and stores the results in
CLK_FREQ registers. A base register supplies a multiplier which allows
directly obtaining the measured value, without requiring knowledge of
the target system or QIXIS core frequency.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc8xxx: Allow DDR overclock
York Sun [Mon, 25 Mar 2013 07:40:08 +0000 (07:40 +0000)]
powerpc/mpc8xxx: Allow DDR overclock

Allow DDR clock runs faster than SPD specifes. This may cause memory
failure, but the user should know what is going to happen when using
higher than expected DDR clock.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/chassis2: Change core numbering scheme
York Sun [Mon, 25 Mar 2013 07:40:07 +0000 (07:40 +0000)]
powerpc/chassis2: Change core numbering scheme

To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.

Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.

Cluster clock registers are reorganized to be easily indexed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc8xxx: Add T1040 and variant SoCs
York Sun [Mon, 25 Mar 2013 07:40:06 +0000 (07:40 +0000)]
powerpc/mpc8xxx: Add T1040 and variant SoCs

T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h
York Sun [Mon, 25 Mar 2013 07:40:05 +0000 (07:40 +0000)]
powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.h

T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/p5040: enable NAND, SD, SPI boot support
Shaohui Xie [Mon, 25 Mar 2013 07:40:04 +0000 (07:40 +0000)]
powerpc/p5040: enable NAND, SD, SPI boot support

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoAdd e6500 L2 replacement policy selection
James Yang [Mon, 25 Mar 2013 07:40:03 +0000 (07:40 +0000)]
Add e6500 L2 replacement policy selection

This is compile-time config.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoT4240/ramboot: enable PBL tool for T4240
Shaohui Xie [Mon, 25 Mar 2013 07:40:02 +0000 (07:40 +0000)]
T4240/ramboot: enable PBL tool for T4240

Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use
PBL tool to produce the ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Add VDD override
York Sun [Mon, 25 Mar 2013 07:40:01 +0000 (07:40 +0000)]
powerpc/t4240qds: Add VDD override

Allow VDD voltage overriding with a command. This is an add-on feasture of
VID. To override VDD, use command vdd_override with the value of voltage
in mV, for example

vdd_override <voltage in mV, eg. 1050>

The above example will set the VDD to 1.050 volt. Any wrong value out of
range of 0.8188 to 1.2125 volt or invalid string is ignored.

In addition to the command, if overriding VDD is needed earlier in booting
process, save an variable and reboot:

setenv t4240qds_vdd_mv <voltage in mV>
saveenv

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: check if core is disabled for showing status
York Sun [Mon, 25 Mar 2013 07:40:00 +0000 (07:40 +0000)]
powerpc/mpc85xx: check if core is disabled for showing status

"cpu <num> status" should check if core is disabled before printing
the spin table location.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agonet/phy: fix select line for TN80xx
Shaohui Xie [Mon, 25 Mar 2013 07:39:59 +0000 (07:39 +0000)]
net/phy: fix select line for TN80xx

TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoEnable L2 cache parity/ECC error checking
James Yang [Mon, 25 Mar 2013 07:39:58 +0000 (07:39 +0000)]
Enable L2 cache parity/ECC error checking

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4240qds: Add board detail for bdinfo command
York Sun [Mon, 25 Mar 2013 07:39:24 +0000 (07:39 +0000)]
powerpc/t4240qds: Add board detail for bdinfo command

Print more detail information including core voltage, RCW source, switch
settings, etc. with bdinfo command.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agocommon: Update cmd_bdinfo for PPC
York Sun [Tue, 14 May 2013 08:06:39 +0000 (08:06 +0000)]
common: Update cmd_bdinfo for PPC

Add board detail function to print more individual board information.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agocmd_mem: fix cp command
Masahiro Yamada [Mon, 20 May 2013 21:08:08 +0000 (21:08 +0000)]
cmd_mem: fix cp command

The "cp" command has not worked since
commit 0628ab8ec59834f98ede267edd21ddb8ba0bb57b,
because of the following lines, which set the destination
and the source to the same address.

buf = map_sysmem(addr, bytes);
src = map_sysmem(addr, bytes);

Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
11 years agoext4: assign get_fs()->dev_desc before using it
Stephen Warren [Thu, 23 May 2013 10:22:10 +0000 (10:22 +0000)]
ext4: assign get_fs()->dev_desc before using it

Commit 50ce4c0 "fs/ext4: Support device block sizes != 512 bytes"
modified ext4fs_set_blk_dev() to calculate total_sect based on
get_fs()->dev_desc->log2blksz rather than SECTOR_SIZE. However, this
value wasn't yet assigned. Move the assignment earlier so the code
doesn't crash or hang.

Cc: Egbert Eich <eich@suse.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
11 years agoarm: Enable -ffunction-sections / -fdata-sections / --gc-sections
Tom Rini [Thu, 25 Apr 2013 07:40:22 +0000 (07:40 +0000)]
arm: Enable -ffunction-sections / -fdata-sections / --gc-sections

While other architectures have enabled these gcc / ld options for some
time on U-Boot itself, ARM has only been doing this on SPL.  Enable this
on full U-Boot as well now.

Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@ti.com>
11 years agoARM: Add Seagate GoFlex Home support
Suriyan Ramasami [Thu, 11 Apr 2013 07:17:25 +0000 (07:17 +0000)]
ARM: Add Seagate GoFlex Home support

Add Seagate GoFlex Home support

Start with dockstar configuration
define support for RTC, DATE, SATA and EXT4FS

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
11 years agoARM: vexpress: enable bootz and hush parser for all VExpress boards
Andre Przywara [Tue, 9 Apr 2013 02:20:33 +0000 (02:20 +0000)]
ARM: vexpress: enable bootz and hush parser for all VExpress boards

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
11 years agoARM: vexpress: add support for Versatile Express Cortex-A15-TC2
Andre Przywara [Tue, 9 Apr 2013 02:20:32 +0000 (02:20 +0000)]
ARM: vexpress: add support for Versatile Express Cortex-A15-TC2

This adds support for the Cortex-A15-TC2 core tile for the Versatile
Express board by ARM. This is mostly a copy of the A5 support file,
but will be extended later with A15 specific options.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
11 years agoARM: vexpress: create A5 specific board config
Ryan Harkin [Tue, 9 Apr 2013 02:20:31 +0000 (02:20 +0000)]
ARM: vexpress: create A5 specific board config

This patch creates a new config for the A5 dual core tile that includes the
generic config for the Versatile Express platform.

The generic config has been modified to provide support for the Extended
Memory Map, as used on the A5 core tile.  A5 does not support the legacy
memory map.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
11 years agoARM: vexpress: refactoring of Versatile Express CA9x4 support
Ryan Harkin [Tue, 9 Apr 2013 02:20:30 +0000 (02:20 +0000)]
ARM: vexpress: refactoring of Versatile Express CA9x4 support

The current ca9x4_ct_vxp platform contains support for a Versatile
Express motherboard with a quad core A9 core tile.

This patch separates the Versatile Express motherboard code and the
A9 specific code, to ease supporting more core tiles in the next
patches.

Andre: merged the first two of Ryan's original patches and did some
checkpatch fixes.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
11 years agocfi_flash: return NULL for invalid base address input
Masahiro Yamada [Fri, 17 May 2013 05:50:37 +0000 (14:50 +0900)]
cfi_flash: return NULL for invalid base address input

When base address given was out of valid flash address ranges,
flash_get_info() function returned the pointer to the last
element of flash_info[i] array.

This patch changes this function to return NULL pointer
in such a case, which is more correct behaviour.

The function flash_protect_default() calls flash_protect()
immediately after flash_get_info() invocation.
With this correction, flash_protect() function would be
able to return soon, for NULL flash_info.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
11 years agocosmetic: cfi_flash: delete a space after an unary operator
Masahiro Yamada [Fri, 17 May 2013 05:50:36 +0000 (14:50 +0900)]
cosmetic: cfi_flash: delete a space after an unary operator

Linux Kernel Documentation/CodingStyle says:
 Do not add a space after unary operators such as &, *, ...

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
11 years agocfi_flash: Fix unaligned accesses to cfi_qry structure
Andrew Gabbasov [Tue, 14 May 2013 17:27:52 +0000 (12:27 -0500)]
cfi_flash: Fix unaligned accesses to cfi_qry structure

Packed structure cfi_qry contains unaligned 16- and 32-bits members,
accessing which causes problems when cfi_flash driver is compiled with
-munaligned-access option: flash initialization hangs, probably
due to data error.

Since the structure is supposed to replicate the actual data layout
in CFI Flash chips, the alignment issue can't be fixed in the structure.
So, unaligned fields need using of explicit unaligned access macros.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Stefan Roese <sr@denx.de>
11 years agoARM: at91: add NAND partition table and index
Bo Shen [Sun, 12 May 2013 23:28:40 +0000 (23:28 +0000)]
ARM: at91: add NAND partition table and index

Add NAND partition table, EK board support boot up NAND flash using
the same NAND partition table

Add Index in this file

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>