Paul Fertser [Mon, 29 Apr 2013 19:31:50 +0000 (23:31 +0400)]
efm32: fix FTBFS on ARM due to alignment issues
The following warnings prevent OpenOCD from building:
efm32.c: In function 'efm32x_read_lock_data':
efm32.c:373:8: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c:386:9: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c:394:9: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c:402:9: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c: In function 'efm32x_get_page_lock':
efm32.c:430:17: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c: In function 'efm32x_set_page_lock':
efm32.c:441:19: error: cast increases required alignment of target type [-Werror=cast-align]
cc1: all warnings being treated as errors
This patch is compile-tested only.
Change-Id: Ia3a8f342e0f5e30c8ea4de9435c5c7a80bc100e3 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1370 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Hsiangkai Wang [Wed, 1 May 2013 02:23:38 +0000 (10:23 +0800)]
gdb_server: remove target_handle_event from gdb event callback
In target_call_event_callbacks(), it will execute
1. target_handle_event (use Jim_EvalObj() to evaluate event
statements in config files)
2. call user registered callbacks
Before calling user registered callbacks, target_handle_event has
been executed. So, there is no need to call target_handle_event()
in gdb event callback. It will execute event statements in config
files twice.
Change-Id: I84629e324fa3eb909907badf2319b4138ba89f07 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1372 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Spencer Oliver [Fri, 1 Feb 2013 15:43:21 +0000 (15:43 +0000)]
target: rename cortex_a8 to cortex_a
Rename cortex_a8 target to use a more correct cortex_a name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Spencer Oliver [Fri, 1 Feb 2013 15:34:51 +0000 (15:34 +0000)]
target: rename cortex_m3 to cortex_m
Rename cortex_m3 target to use a more correct cortex_m name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Ensure FlexRAM usage is limited to half the FlexRAM size when programming.
Assume the FlexNVM sector size is equal to half the FlexRAM.
Fix sector erase checking which had an error introduced when the
kinetis_ftfx_command( ) signature was changed.
Spencer Oliver [Mon, 22 Apr 2013 14:10:56 +0000 (15:10 +0100)]
build: fix libftd2xx regression
Fix build when targeting closed src ftd2xx drivers.
configure is unable to find the dynamic linking loader lib (dl) as it
is included before ftd2xx library.
Change-Id: Ibe7308b66ed846288a31f7a27ff549b6f39baeec Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1355 Tested-by: jenkins Reviewed-by: Luca Bruno <lucab@debian.org> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Spencer Oliver [Tue, 23 Apr 2013 11:15:07 +0000 (12:15 +0100)]
arm: fix arm reg regression
Seems commit fc2abe63fd3cea7497da7be2955d333bd3f800b9 caused a regression
in that the arm reg cmd no longer worked. The issue was caused because we
changed the value of ARM_MODE_THREAD which was being checked in arm_init_arch_info.
Change-Id: Id571d4ab336d1b0e2b93363147af245d24b65ca5 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1362 Tested-by: jenkins Reviewed-by: Luca Bruno <lucab@debian.org> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Hsiangkai Wang [Tue, 23 Apr 2013 10:42:07 +0000 (18:42 +0800)]
gdb server: Fix bug. Parse 'M' packet error.
The format of 'M' packet is 'M addr,length:XX...'. The data
follows ':' immediately. No need to '+2' to SEPARATOR in
unhexify(), because SEPARATOR points to data correctly.
Change-Id: I15b5758b540816cc727752e7bf68cd45e623f603 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1360 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Matt Dittrich [Tue, 5 Feb 2013 16:53:49 +0000 (10:53 -0600)]
flash/nor: add lpc4300 variant to lpc2000 driver
This patch adds flash programming support for internal flash of the
LPC43x2/3/5/7 part, tested on a LPC4337 (also tested on a LPC1768
and LPC2468). It should also work with LPC1800's with onchip flash.
The "base" parameter of the "flash bank" command is now significant
for the lpc4300 variant and required to determine the bank number
parameter needed by the IAP routines.
NOTE: I could only program flash successfully when the chip is powered
with "P2_7" pulled low to put it in ISP mode. When running from flash
(and not the ISP ROM), the target fails to halt and the sector erase
fails. This is similar to the behavior I remember when trying out the
spifi driver on a LPC4350... lots of power cycles to make progress, one
To burn, one to run. So I am not confident my config is set up correctly.
Reword info about creating SSH key - it's not required to add it to
Github account. Mention adding created SSH key to Gerrit account -
without this step it's not possible to access Gerrit in further
steps.
R. Steve McKown [Fri, 19 Apr 2013 17:29:59 +0000 (11:29 -0600)]
Support newer OSBDM firmware
OSBDM: add new VID:PID implemented in OSJTAG/OSBDM firmware somewhere
between versions 30.13 and 31.21. PFLASH programming works with this
patch, tested on a Freescale Kinetis TWR-K20D72M using its onboard OSBDM
JTAG adapter.
Note: flash program testing required hacking kinetis_write() to force
longword programming, as the FTFL program section commands formulated by
kinetis_write() currently fail on this board's PK20DX256VLL7 processor.
Change-Id: Ib7b92ff2fe9ebf6158fb1489f554a19e96cd9651 Signed-off-by: R. Steve McKown <rsmckown@gmail.com>
Reviewed-on: http://openocd.zylin.com/1348 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Salvador Arroyo [Wed, 3 Apr 2013 15:12:01 +0000 (17:12 +0200)]
mips: m4k alternate pracc code. Patch 4
Now all the functions with only fetch accesses are modified.
The same delay between scans has been added to mips32_pracc_fastdata_xfer(), it should work
at the same scan rates as the other pracc functions, but it needs higher scan_delays
to work.
Salvador Arroyo [Sun, 3 Mar 2013 19:11:38 +0000 (20:11 +0100)]
mips: m4k alternate pracc code. Patch 3
Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified.
mips32_cp0_read() is very similar to mips32_read_u32() with one store access.
mips32_pracc_read_regs() is the only function that can not be executed from only one queue.
Now this function is modified to use reg8, it saves all the registers but does not restore reg8.
To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in
mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and
restore it from ejtag info instead of using DeSave for save/restore.
Salvador Arroyo [Sun, 3 Mar 2013 12:08:42 +0000 (13:08 +0100)]
mips: m4k alternate pracc code. Patch 2
Each pracc function defines a variable ctx of type struct pracc_queue_info.
To simplify the code tree auxiliary functions are defined: pracc_queue_init(), pracc_add() and
pracc_queue_free().
The second parameter in pracc_add() is the store address if the instruction is a store at dmseg,
otherwise it should be 0.
The code is executed by mips32_pracc_queue_exec(). If ejtag_info->mode is 0 mips32_pracc_exec()
is called and it should work like with current code.
To generate the delay between scans the number of clock ticks are calculated with the help of
jtag_get_speed_khz(). Due to delays in the execution of each single ftdi instruction the number of ticks
are higher as it should be, specially at higher scan rates.
mips32_pracc_read_u32() should now work with the new code.
Salvador Arroyo [Sun, 3 Mar 2013 09:50:42 +0000 (10:50 +0100)]
mips: m4k alternate pracc code. Patch 1
This patch and the following patches define another way of doing processor access without the need to read back
the pracc address as needed in current pracc code.
Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
Most of the processor accesses are fetch and some are store accesses.
After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
The pracc address for a store depends only on the store instruction given before.
m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
For reference: MD00249 mips32 m4k manual.
A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
current code or by the new one to generate the sequence of pracc accesses.
For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
The pracc bit is not checked before execution, is checked after the queue has been executed.
Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
between scans is added by calling jtag_add_cloks().
A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
current code is executed, if lower, new code is executed.
Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
Ben Nahill [Fri, 19 Apr 2013 15:10:04 +0000 (11:10 -0400)]
stm32w: Added sample target configuration for STM32W108 with STLink-V2
As requested, here is the target configuration that I'm using for an
STLink-V2-attached STM32W108C8. For some reason, it only seems to work
with "reset_config trst_only".
Ben Nahill [Wed, 17 Apr 2013 20:46:07 +0000 (16:46 -0400)]
topic: STM32W support added to em357 driver
The em357 driver only supported one page configuration (192k in 96 2048k)
pages. This is fine for em357 chips since that's the size they have, but
ST's STM32W chips (pretty much the same) have different flash
configurations available (64, 128, 192, 256k). I can't find anywhere
that would indicate the size of the chip anywhere in memory so the
selection must be manual, using the 'size' parameter. For backwards
compatibility, any size not known to be in use defaults to the 192k
configuration. I don't have any em357 devices to test, but I also found
that I had to re-assert the FPEC clock enable before performing an
erase. This is a single line and shouldn't break any configurations.
My testing so far has only been with a 64k device with 8k of RAM.
Change-Id: Ic0ac400a9696efaa09d1407dd4a4d456bc2c318b Signed-off-by: Ben Nahill <bnahill@gmail.com>
Reviewed-on: http://openocd.zylin.com/1336 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
Spencer Oliver [Fri, 12 Apr 2013 12:10:35 +0000 (13:10 +0100)]
program: do not poll target after reset run
Disable polling the target before we issue a 'reset run'. This stops errors or
warnings if the target disables the SWD or JTAG interface as part of the
application code.
Change-Id: I5019dffdad41a8e210003ece1caf89069ee0f223 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1331 Tested-by: jenkins
Spencer Oliver [Tue, 26 Mar 2013 15:23:16 +0000 (15:23 +0000)]
parport: fix parport_toggling_time regression
If parport_toggling_time is called before the adapter speed has been
configured then the call fails. Probably not the best fix, but does at least
enable parport_toggling_time to be used again.
Michel JAOUEN [Mon, 18 Mar 2013 15:45:40 +0000 (16:45 +0100)]
arm_adi_v5: fix for csw nonsecure access.
Add command to fix CSW_SPROT in register AP_CSW.
This solves dap apmem access in non secure access.
Change-Id: I7cfcb6434d75f5cfd4a2630a059901cdeea010ce Signed-off-by: Michel JAOUEN <michel.jaouen@stericsson.com>
Reviewed-on: http://openocd.zylin.com/1276 Tested-by: jenkins Reviewed-by: mike brown Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sun, 24 Feb 2013 16:05:28 +0000 (17:05 +0100)]
mips: change in restoring debug working register
In current devel code there are 3 functions (related to m4k code) that need to restore register 8 from pracc stack:
mips32_pracc_read_u32()
mips32_cp0_read()
mips32_pracc_write_mem_generic()
And mips32_pracc_read_mem() needs to restore regs 8 and 9 from pracc stack.
Values in this registers should be the same as read by mips32_pracc_read_regs() when entering debug
mode and can be modified by mips32_pracc_write_regs() when leaving debug mode.
There is no need to read their values from the processor registers every time.
The fields reg8 and reg9 are added to struct mips_ejtag to store these register values
and the call to mips32_save_context() is shifted in mips_m4k_debug_entry() in order
to store them before any other function needs to restore these registers.
For the same reason in function mips_m4k_step() the call to mips_m4k_set_breakpoint(), if needed,
should be made after calling mips_m4k_debug_entry().
For single word write the number of pracc accesses are now 9 or 8, from 13 or 12 in current code,
single word read takes now 10 instead of 12.
This patch is really the first in a set of patches for an alternate m4k pracc code
much faster that current code. At least for me with pic32mx works fine.
Change-Id: Ibd9df5e8b9f78ce05a180949ba6a561c761b61d6 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1146 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sat, 23 Feb 2013 21:53:35 +0000 (22:53 +0100)]
mips: mips32_pracc_fastdata_xfer() little modification
In this function after loading the handler code and the jump code there is a call
to wait_for_pracc_rw() to verify that a pracc access is pending.
Next the address is read to verify that the handler is running, the address should be at
fastdata area.
Next, another call is made to wait_for_pracc_rw(). This call is not needed, we now already
that a pracc access is pending.
Better we call this function before loading the end address to be sure it is loaded correctly.
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Change-Id: If311450ea634786fc28cf1a8e18ed24ce5257d20
Reviewed-on: http://openocd.zylin.com/1142 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sat, 23 Feb 2013 19:00:21 +0000 (20:00 +0100)]
pic32mx: 0 wait state option
By default pic32mx starts after any reset with 1 wait state for RAM access/exec.
It can be changed to 0 wait states by clearing the BMXWSDRM bit (bit 6) in BMXCON register.
With 0 wait states near doubles the execution speed. CRC check sum can be done much faster
increasing verify_image speed. Fast data transfer also works with a bit higher scan rate, up to 1500 Khz.
This option can be set at any time with
mww 0xbf882004 0x40
or cleared with
mww 0xbf882008 0x40.
Some numbers for FTDI/HS with current devel code and a elf file:
Core clock / wait states verify_image speed
------------------------------------|------------------------------
Salvador Arroyo [Sun, 17 Feb 2013 18:23:16 +0000 (19:23 +0100)]
pic32mx: false pending at low core clock
To show up the fail try to step with the core clock set to 31.25Khz
and with a ftdi/hs adapter or with a wiggler, -not with ft2232-.
The scan frequency should be set to 300Khz or higher, at lower frequency probably will not fail.
The code exits with error because the pracc address is at 0x0.
It also fails when using the "all" register, but in this case the code works without any message because the
pracc address is at 0xff202004 when it fails.
I never saw this fail with the core clock set to 500Khz or higher, but ...
The workaround simply puts a 1 ms delay after the execution of the DERET instruction.
Change-Id: I38e8c01a9c39aedd3282140543b83a0844d8ad29 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1139 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Moved JTAG code out of transport-neutral file (arm_adi_v5.c) into
transport specific file (adi_v5_jtag.c).
Added ap_block_read to dap_ops interface (arm_adi_v5.h) to support
the move.
Change-Id: I796d3984f138aad052b97c77ac9c12ffd1158f74 Signed-off-by: mike brown <mike@theshedworks.org.uk>
Reviewed-on: http://openocd.zylin.com/1277 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Spencer Oliver [Thu, 14 Mar 2013 21:38:19 +0000 (21:38 +0000)]
docs: fix html anchor xref links
makeinfo has a long outstanding bug that means @anchors are not correctly
formatted for split html, see:
http://lists.gnu.org/archive/html/bug-texinfo/2012-06/msg00000.html
The issue relates to using spaces or hyphens in the @anchor name.
Issue also reported via Trac #44
The commit "gdbserver: use common hexify/unhexify routines" [3d62c3d]
mis-replaced a call to "str_to_hex" with a call to "unhexify". "hexify"
should have been used instead.
Change-Id: I5f5904b1b422f819a6308e2c0740ea43d22c7d0b Signed-off-by: Christian Gudrian <christian.gudrian@gmx.de>
Reviewed-on: http://openocd.zylin.com/1308 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
The only caller was arm_nandwrite(). Replace that call with
target_write_buffer() instead, which in turn may end up calling the same
bulk_write_memory target API function.
Change-Id: If34c7474df5cf14af3b732fb4774816818f28e79 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1214 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
target: Add default implementation of bulk_write_memory
Remove dummy implementations from all targets except arm7_9 and mips, which
are the only ones with real implementations. Replace with a single default
implementation simply calling target_write_memory().
Change-Id: I9228104240bc0b50661be20bc7909713ccda2164 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1213 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
If command parport_cable is not executed, parport_cable points to
const char array in read-only memory as default. On exit free()
will try to free this read-only memory. This patch uses strdup to
allocate memory when defining default setting.
Change-Id: I290e707ac6a37e9dc1b45c85ca51d8bd6aac6761 Signed-off-by: Stefan Mahr <stefan.mahr@sphairon.com>
Reviewed-on: http://openocd.zylin.com/1223 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Rodrigo Melo [Thu, 27 Dec 2012 22:31:21 +0000 (19:31 -0300)]
ft2232: ft2232_channel option added
With this option a different channel of the ft2232 chip can be selected using
a previously existing layout. It was made for a partner called Salvador
Tropea.
Alex Austin [Sun, 3 Mar 2013 10:08:18 +0000 (04:08 -0600)]
Kinetis: Flash command function matches datasheet
The kinetis datasheets specify the flash registers as bytes rather
than as words, as the previous implementation did. This also makes
a few code sections slightly less endian-magical.
Change-Id: If8f4adfc7f4341085ae5b6eacbf7d74bbd74cf08 Signed-off-by: Alex Austin <alex.austin@spectrumdsi.com>
Reviewed-on: http://openocd.zylin.com/1192 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Spencer Oliver [Wed, 27 Feb 2013 12:48:11 +0000 (12:48 +0000)]
flash: fix stm32 failed probe using incorrect flash size
This fixes an issue if the device is manually probed after the initial probe
fails due to being unable to read flash size register. In this situation the
driver assumes the user has overridden the flash size when infact this may
not be the case.
It also seems on the older stm32f1 devices the flash register is not readable
when locked, this does not seem to apply to the newer parts - f0, f3, f4.
Change-Id: I125f872fcb2d962ca6705f97b62d957e2b31303b Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1187 Tested-by: jenkins Reviewed-by: Johan Almquist <johan.almquist@assaabloy.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Peter Henn [Sun, 28 Oct 2012 21:08:37 +0000 (22:08 +0100)]
speed up ftdi by reorder to out-in
When the ftdi driver calls finally the mpsse_flush function, it first
initiate the USB in and finally the corresponding USB out transaction.
Because data in is requested too early the USB device will always answer
the first USB in by a NAK. That can prevented by a simple reordering of
the out and then the in transfer and can improve the Jtag performance for
high JTAG clock rates.
Change-Id: I17abf1487c914c92e2e447ee6d30562ef629f327 Signed-off-by: Peter Henn <Peter.Henn@web.de>
Reviewed-on: http://openocd.zylin.com/942 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Xiaofan <xiaofanc@gmail.com>
projects / openocd / log